 Today, we will look at two important characteristics in the context of nano transistor. One is what is called narrow width effect. The other important aspect is what we call sub threshold conduction and this in turn will lead us to the discussion of the issue of static power in today's state of the art CMOS technology. It has really surfaced as one of the very important challenges to deal with right. In the last lecture, we have looked at short channel effect that is when you decrease the channel length of the transistor what happens to the threshold voltage of the transistor. So, first let us start with the discussion today that is narrow width effect. So, when we are talking of width of the transistor, let me just refresh you with the top view of a transistor as you may recollect. We have seen in one of the earlier lecture, we call this as an active area and typically whenever you have two rectangles one called active and the other one called gate in top view which crisscross each other that indicates a transistor. So, now in top view, this is a transistor. You have a gate here and you know active area and in turn you see this side of the transistor is source, this side of the transistor is drain and this distance is what we have been calling as a channel length which is essentially the distance between source and drain junctions. Along this direction, this is our channel width right. Now, last lecture we saw the transistor cross section by essentially taking cross section in this direction right. When I do a cross section here and I take a side view as you know we essentially see something like this right here I have the source junction and here I have this drain junction right and on top I have gate insulator and this is my gate electrode right and looking from the top what you see is essentially this gate electrode which is sort of crossing this active area. The active area then includes in this direction the source channel and the drain region all these put together are active area. When we talk of integrated circuits with millions of transistor, two neighboring transistors are always isolated from one another right. It used to be in olden days junction isolation, but junction isolation is just not feasible and we have been doing oxide isolation for last several generations of the technology. In other words, you have this transistor and you have a neighboring transistor let us say out here I am just going to sketch only active area I am not going to sketch the field area and similarly in this direction also you may have another transistor right which will be going like this. And this transistor one transistor one transistor two and transistor three have to be isolated if they do not have to talk to each other there has to be perfect electrical isolation. So, in other words where all these are called active areas and wherever you do not have these active rectangles rest of the area is called field area and in this field area you essentially have grown silicon oxide or deposited silicon oxide to create isolation. In other words if I were to you know look in this direction right I have silicon right underneath this active region, but underneath these regions I will initially see an oxide if I see the you know depth profiling and then later on I will see silicon coming in I will draw that for you in a minute. So, in other words if I were to take a cross section along this direction here and look at it from the side because I have taken a cross section and I am looking at it from this side. So, then what you will see is the following right I will keep that out here. So, you have that for your reference. So, I am taking a cross section and looking at from the side view. So, what you have then is this is your active area that corresponds to your width of the transistor and here immediately under this silicon oxide remember this is silicon oxide this is the same silicon oxide which is this gate oxide immediately under that you have this silicon and this is the edge of your active area this is the edge of the active area which essentially corresponds to this area correct edge of the active rectangle that you have. So, from here on if you see here what you will essentially see is something like this is also silicon oxide this whole thing is silicon oxide and this is also silicon oxide you see, but this is what is called a gate oxide of the transistor and this is a field oxide of the transistor and the field oxide is typically very thick. There by if there is a transistor here another transistor this field will extend like this you see this is what we call a field region and when there is a next transistor that comes in you again have a thin oxide and next transistor which you know we looked at in this direction this is the next transistor. So, between the edge of this active and edge of this active you will have a thick field oxide as is indicated out here and you know this is what is called isolation. Now, you know in CMOS technologies there are two different ways of doing isolation you know we will come to that in a minute, but the point I am trying to raise right now is you have this isolation oxide here as well S I O 2 and this is your gate oxide a very thin S I O 2 and remember you know what you see on top here is this polysilicon correct, because you see this polysilicon red area rectangle goes beyond this active edge right. This is the active edge it is going to go beyond this active edge by this amount that is why I have shown this polysilicon going on top of the field oxide as well. So, this is what you see right in the in the side view when I take a cross section along the drain along the width axis of the transistor. Now, you see there is something interesting that comes up typically again when we apply a voltage right we have to create a depletion and then we have to create an inversion right. Earlier we essentially said that whenever we apply a voltage you will have a depletion region created in this area and then of course this region will be inverted and that is when you have a inversion and current will flow when the transistor is on, but you see when I apply a voltage here to this gate V G this V G will set up certain charge on gate our earlier assumption was that that charge was balanced by an equal and opposite charge which is found only in this area. But in reality you will have what are called fringing fields here correct at this edge even though that oxide is little bit thicker and hence you will also start creating the depletion region here right. In other words you see whenever I apply a voltage on the gate the gate not only have to deplete this region, but it will also have to deplete this region before you start talking about inversion. In other words gate has to do extra effort as opposed to what we had in a very simplistic model right which is just this rectangle this is exactly opposite of charge sharing effect that was coming in short channel effect because in short channel effect source and drain charge sharing was helping you to really invert the transistor because part of the depletion which was taken by source and drain regions. But here gate will have to take care of additional depletion area right. So, what would you expect you would expect that V T should start increasing because of this effect. However, again when the width is very large this small area which is essentially due to the fringing field is so small that it is just insignificant. But when width is shrinking when width is becoming comparable to this area which is being depleted because of the gate. Now gate is doing extra effort that is visible externally and hence you need to apply more voltage to invert the transistor. In other words if you were to now sketch your V T as a function of channel width it should be flat right as per our simple one dimensional derived equation. But when the channel width decreases to the order of 500 nanometer 100 nanometer then you start seeing an increase in V T. So, V T increases and this is what we call narrow width effect. This effect shows up only when the width is very narrow very narrow in this regime not in this regime when the width of transistor is very wide this area is insignificant compared to the actual active area of the transistor. So, this is a very important point that you need to also remember when we talk of very small feature sizes of the transistor. Now narrow width effect is a very strong function of how we make this oxide how we make this field area you see because this field essentially depends on you know this oxide thickness. You just imagine two cases in one case where this oxide thickness is incrementally smaller than this gate oxide then this fringing field is as strong as this vertical field. In another case where it is a very thick oxide then that fringing field is just negligible correct. And you would imagine obviously that the structure of this isolation will have a very very strong impact on how this narrow width effect will look whether it looks like this whether it looks like this or almost flat it does not depend on width at all. So, in this context I just want to sort of highlight that when we talk of isolation technology there are two kinds of isolations that we talk about one is what is called abbreviated as low course this stands for local oxidation of silicon. This was a technology isolation technology that was used from the you know early days of CMOS you know way back in 70s all the way to I would say mid 90s till about 0.35 micrometer generation or 350 nanometer generation. CMOS in all these technologies we used to have locus isolation, but all modern technologies use what is called trench isolation. And it turns out narrow width effect is very severe very bad in locus isolation and narrow width effect is negligible in these technologies. Where we are talking of less than 0.35 micron now you can appreciate why we moved from locus to trench isolation right. If narrow width effect starts becoming very very strong it is very difficult to control the threshold voltage of the transistor right. So, we want to minimize the narrow width effect and that is why we went to trench isolation technology. So, what is different between these technologies is the following in locus isolation that is number one which I showed earlier your isolation area looks like this. This is what we call active area which is where your transistor width is defined lithographically the by printing and this is your field area. Typically you know if this oxide thickness is of the order of let us say 10 nanometer which is about 100 angstroms this could be as large as 500 nanometer which is 5000 angstrom you know almost 50 times more right. And that is what is going to give you the isolation from one transistor to the neighboring transistor, but very interestingly when we try to actually define this field region by this process we always end up with this kind of a transition region. In fact sometimes in locus technology you know nomenclature this is actually called birds beak because when you look at it it looks like a birds beak coming in here. This birds beak is a major problem in locus technology right you know no matter what you will have this effect. Whereas if you have a trench isolation technology trench isolation would look like this. If this is your silicon and if this is your active this is your silicon oxide you actually have what is called a trench dug in silicon which is completely filled with oxide this whole thing is filled with oxide. And this is why it is called trench isolation this is your active area which is your width and outside the width is this region here. If you have very thick oxide right at the edge of this active your fringing field here will be very very small right as a result of that you will not see much narrow width effect. Whereas although you had thicker oxide here right where it matters you know as far as narrow width effect is concerned it is really thin the oxide is very thin and hence your fringing fields can be very strong here. Whereas here your fringing is not very strong it can be neglected for all practical purposes. And that is why your trench isolation technology is what is used for all technologies less than 0.35 micron it minimizes the narrow width effect it minimizes this birds beak problem as well. We will not really go into the details of how one would actually get this structure because that is really the details of the semiconductor processing right. We will not really talk so much about this in this part of the course we will only focus mostly on device physics part. But there are ways to do that for example as the name suggest here local oxidation of silicon meaning oxidation can be done locally in silicon wafer by masking certain regions of silicon wafer right. So, you mask the active region of the silicon wafer by a dense material such as silicon nitride. So, oxygen does not diffuse through silicon nitride and the rest of the area is exposed and oxidation takes place in those area that is conversion of the silicon into silicon oxide. Whereas in the active region since they were protected by silicon nitride they do not get converted into silicon oxide. And that is how selectively I can convert part of the region into a thick field oxide region rest of the region is what I use to build a transistor. Similarly, there are ways to build a trench isolation technology we will not really go into the details. So, that completes the first target that we had for today's lecture the what is meant by narrow width effect. The fact that as I start miniaturizing the width of the transistor I need to start considering the fringing fields which would be there typically you know at the edge of the gate along the width direction specifically where gate electrode is going on top right beyond the active area. And because of that your threshold voltage will have a increasing trend then that is narrow width effect by going to trench isolation technology as opposed to locus isolation technology we have been able to minimize the narrow width effect. Now let us go to another very important aspect that we wanted to discuss for today's lecture and that is sub threshold conduction. This essentially means this is a condition when my gate voltage is less than threshold voltage right that is you have a transistor and this is your V G gate electrode and these are your source and drain junctions. I apply a drain voltage V D S and we say that typically if we look at I D S drain to source current as a function of V G S this being an N channel transistor we say it would look something like this especially for when V D S is small that is when the transistor is in linear region otherwise the transistor is in saturation region. Now this point here is what we call threshold voltage we say that I D S is equal to 0 for V G S less than V T H correct then I D S will be non-zero right for V G S greater than V T H and then it could either be in linear region or in saturation region depending on what is your drain value voltage value that you have. But what we are really now interested is this region what happens when V G is less than V T H is current indeed 0 or there is a non-zero current if there is a non-zero current what is the basis of that non-zero current. Remember this is a P type substrate when I have reached V G is equal to V T H that is when I have created a channel here correct and when there is a channel you have current which is a drift current correct the current flows because there are lots of carriers and you have applied drain voltage that sets up electric field and hence you have a current flowing to the transistor. But when I have V G S less than V T H I do not have a channel really in other words in this region N is small and hence your drift current also fields are small your drift current can be ignored really. However N is small but non-zero you see N cannot be 0 even when it is P type silicon which is doped with 10 to the 15 acceptor impurities my N here is still 10 to the 5 right which is a minority carrier concentration. Now we are talking of a situation where I have applied a voltage here non-zero voltage and applied ground potential here. Now I am asking the question there is no drift current but could there be a diffusion current if there is a concentration gradient of electrons from source to the drain we could certainly expect diffusion current to flow through right because if you recall the diffusion current density is given by where you Q is the electron charge d N is the diffusivity of electrons of course d N as you know is given by d N by mu N is K T over Q the so called Einstein's relation where K T over Q is the thermal voltage mu N is the mobility right d N is essentially diffusivity of the carriers. So, this is a diffusion current the diffusion current exist whenever there is a concentration gradient N can be small but d N by d x can be there. So, we need to really worry about what is d N by d x. So, let us really find out what is d N by d x now. Now if drain voltage were to be 0 source voltage were to be 0 then there would be absolutely no gradient in electron concentration. The electron concentration gradient will come in only when I create an asymmetry by applying a unequal voltage on the source and drain terminal as is the case here 0 and v d s which is not equal to 0. In fact we will see little later that the electron concentration here will be more compared to the electron concentration here. In fact we will derive the expression for the electron concentration but qualitatively you can think about this in the following manner. This is a reverse bias N plus p junction and this is a reverse bias N plus p junction right. But here I have a non zero reverse voltage right. If you recall your p N junction theory there is something called a law of a junction at the edge of the depletion region your carrier concentration is really governed by what is the reverse bias voltage that you are applying. In other words if you recall your N in general is given by N p naught times e to the whatever reverse voltage that q v r by k t in a diode in this is in a simple diode right. The minority carrier concentration gets modulated based on what is the applied reverse voltage. Now let us actually come from the other perspective that we have been talking about right. From the MOS theory right if you recall we can write electron concentration in general as e to the q psi s by k t where psi s is what we call surface potential. And in fact we have seen that when I reach inversion psi s is equal to 2 phi b in a p type silicon the you know surface potential to begin with psi s when you do not have any applied voltage it is a flat band condition. Your electron concentration will be much lower than the whole concentration. But as you start applying the forward bias voltage you know your psi s starts increasing right and eventually it becomes equal to 2 phi b. And that is when we have inversion condition right you remember that right. And essentially what you know we are talking about now when we are talking about this diffusion current d n by d x is to really find out n at source region I will call it n at s minus n at drain divided by the distance between source and drain which is the channel length. So, if you can find out you know what is the electron concentration at the source and electron concentration at the drain that in turn will you know give me what is you know your diffusion current because from there you can get the carrier gradient right. So, here we can essentially write the electron concentration at the source side as you know something like this right n p 0 e to the q psi s by k t right with an assumption here that under flat band condition psi s is equal to 0 that is how we set up the convention for measuring the surface potential right. You know flat band condition for that is psi s is equal to 0. In fact, when psi s is equal to 0 remember the bands are flat in silicon and as a result of that your whole concentration is really n p naught n p naught stands for I mean electron concentration electron concentration in p side under thermal equilibrium condition right that is not at all altered. Now as you start applying more and more gate voltage you know this psi s starts increasing eventually psi s becomes 2 phi b when psi s becomes phi b n p n 0 is equal to n i correct because that is when your intrinsic level will bend and come to the Fermi level location because that is a band bending of phi b and when psi s is equal to 2 phi b intrinsic level will fall below the Fermi level and that is when it has become n type ok. So, that is when you go from n p naught all the way to the carrier concentration which is equal to whole density in a p type doped semiconductor right. So, that is how we have this carrier concentration. On the other hand at the drain junction because my drain voltage is non-zero your electron concentration would actually go down below the source electron concentration by this modulation factor which is q V d s by k t ok. When V d s is equal to 0 as you can well see here your drain concentration is equal to source concentration that is what you expect in a symmetric device right. But here you have created a symmetry by applying voltage and hence you know you have a carrier gradient and that will set up a diffusion current ok. So, now given this you know we can write the expression for d n by d x which is simply n p naught e to the q psi s by k t into 1 minus e to the minus q V d s by k t divided by length. Now I can use this in my drain current equation that I had here replace d n by d x with that expression and multiply that with q d n then I get the current density multiply that with area you get current eventually right. So, then let us find out what happens to your current right. So, your current then j n diffusion is minus q d n you know we could replace d n as mu n times k t over q because d n by mu n is k t over q remember that. So, I have just made that substitution there and then n p naught e to the q psi s by k t by l into 1 minus e to the minus q V d s by k t. A very important observation that you can make right away in terms of the sub threshold current and it is dependence on the drain voltage is that when V d s is a few times thermal voltage you see q V d s by k t. So, q bring it to the denominator it is k t over q in the denominator at room temperature it is about 25 millivolt and if your V d s is let us say 7500 millivolt then e to the minus 4 is negligible compared to 1. In other words when V d s is little more than thermal voltage your sub threshold current is more or less independent of drain voltage. In other words it just sort of flattens out it only is dictated by what is the psi s value and psi s value we will see in a minute is governed by your gate voltage. So, you know for we will just look at this condition for V d s greater than a few k t over q you can approximate this J in diffusion as this right this is what we have. Now, what I am interested really is to replace this psi s in terms of gate voltage because I my interest eventually is to find out when V g is less than V t for any given value of V g what is the corresponding drain current now I already see that it is non zero current. So, now let us find out what it is then psi s you see we can write psi s in general as V f b I am sorry not psi s we will just rewrite this. So, what I mean here is V g that is applied gate voltage is really V f b plus drop across silicon and that is what we are calling psi s. In fact when I reach inversion that is when I replace left hand size V g as V t h and write 2 phi v for psi s correct and what is this here it is 2 epsilon q times n a psi s again when I reach inversion I replace psi s by 2 phi b and this becomes 4 epsilon q n a phi b the classical equation that we had earlier right divided by C ox. Let us see the dependence here let us let us look at this d V g by d psi s V f b is a constant flat band voltage you know that depends only on the work function difference that you have. So, that is 0 and here d we are differentiating left hand side and right hand side with respect to psi s. So, here what you essentially get is this is 1 plus differentiation of this and you know if you do that and if you simplify you know I will just skip a few steps just for you know brevity here eventually you can show that this is given by this expression you differentiate this psi s is psi s to the power half then half you know psi s will come to the denominator as root psi s when you differentiate psi s to the power half with respect to psi s right you can do all that algebraic simplification and eventually you write C d depletion capacitance as epsilon s divided by W d and W d in turn depends on psi s because psi s is the voltage across the depletion width right if you do all that you will come up with this very interesting expression. And you can even sort of rewrite it if you want as you know C ox plus C d divided by C ox both are one and the same in fact sometimes we call this factor here as m where m is greater than 1 right which is very obvious because it C ox plus C d divided by C ox. Now you can rewrite this to get d psi s as C ox divided by C ox plus C d times d Vg yes. So, what is this telling you you know this is this is telling you something very interesting and that is it appears now as a series capacitance circuit that we have what is there in the series capacitance circuit I have Vg here I have C ox here and I have C depletion here which is silicon capacitance and this is my psi s. And when there is a voltage change on the gate correspondingly there is a voltage change at psi s meaning that is a voltage drop across this C d as you know in a capacitive divider the voltage across this capacitor is the total voltage that is being applied or the change in voltage divided by other capacitor divided by the total capacitor correct. And that is exactly what we have here in other words what this is telling you is that the only fraction of the change in gate voltage appears as a change in surface potential. And what is that fraction is determined by this ratio as we will see this ratio becomes extremely important and that in turn determines what is your sub-ratiold slope. And you know given this as I said already you know you have this d psi s is you know d Vg by m correct. And because you know C ox plus C d divided by C ox is m and I do know that when psi s is equal to 2 phi b Vg is equal to Vt. And now we are asking the question when psi s is not is equal to 2 phi b accordingly Vg is not is equal to Vth what happens right. So, based on that I can sort of rewrite this equation as psi minus 2 phi b is equal to Vg minus Vth divided by m right ok. And the particular case when you know as I said we are now talking of psi being less than 2 phi b that is Vg being less than Vth right. And that is when we are trying to ask the question what is the current right. In other words your psi again here is 2 phi b plus Vg minus Vth divided by m ok. Now let us go back to this equation that we had your drain current Jn diffusion is all this factor ok times e to the q psi s by k t divided by l. Now I can replace this psi s because I have an expression for psi s below Vt psi s as a function of Vg is now derived. Let us make use of that equation and also let us you know instead of current density we will write the current I n or I ds simply as Jn diffusion times area ok we will not worry about what that area is you know area is the width of the transistor times the thickness over which the current is flowing because that is the cross section for you available for the current to flow ok. But let us just keep it as a ok and also let us club all this pre factor that we have as some constant ok some constant k ok because we are only interested in this exponential factor right that is our region of interest right now ok. So, in other words you know your current is some constant k which will absorb this a area and all other parameters such as mobility minority carrier concentration temperature and all that right. And this exponent e q psi s by k t that I am going to rewrite now as e to the you know q 2 phi b by k t ok this ok times e to the q Vg minus Vth by m fine ok. I am just looking at that exponential factor that I have here this exponential factor L is also absorbed in that constant right do not worry about that and in fact I make an observation that for a given doping concentration phi b is fixed and this is also constant I will also absorb that in a final another constant some k prime ok. So, if I do that then you know I have an expression here I ds is some k prime e to the q Vg minus Vth divided by m very very simple equation now which says drain current has now an exponential dependence on gate voltage you see when the transistor is on in a MOSFET drain current has linear or quadratic dependence when it is in linear or saturation region but now the drain current has an exponential relationship ok. And more importantly we are really interested in this quantity actually that is log I ds if you were to take here again some log constant some you know constant will not worry about that right then what you really have is q Vg minus Vth by m by log 10 to the base e or ln e here I am taking the log to the base 10 here log to the base 10 you see right this is what you will get the quantity that I am interested eventually is this d log I ds to the base 10 by d Vg this is the quantity that I am interested. So, if you do this differentiation what you get as you can see here is somewhere I have when I substituted that I think I have missed this k t right in the denominator right. So, here this is q by k t right this is here but I forgot to write it here right q by k t ok. So, you know that k t is out here and accordingly and that is also here ok and what you essentially have is k t m log 10 to the base it is ln natural log of 10 ln e ok. Now, I define a quantity called sub threshold slope which is inverse of this ok. In fact, that is why the unit for sub threshold slope is typically milli volt per decade this is this is volt and this is log 10 which is decade variation right you know because you have taken log the y axis is you know how many decades you are changing right and that is the unit that you have come up to right. So, now this essentially 1 over slope which means you invert this right. So, your sub threshold slope which is an extremely important quantity for a transistor. Now, we have observed and we have derived this from first principle as m times log 10 to the base e it turns out ln natural log of 10 is 2.3 and k t over q at room temperature is 25.8 milli volt approximately you multiply that with 2.3 you get 60 a good number to remember ok. So, in other words your sub threshold slope is 60 times m milli volt per decade because I took thermal voltage in milli volt right that is why it is coming in milli volt per decade ok. As you know m is really 60 times 1 plus c d over c ox milli volt per decade what is the significance of this sub threshold slope you see sub threshold slope as you can see depends on absolute temperature ok. So, if your chip has to operate no matter what technology you are using it will always remain at the same value it cannot change whether it is 1 micron technology or 50 nanometer or 40 nanometer k t over q is same ln 10 2.3 is same that 60 factor will never change. What this is telling you is that the very first picture that we saw here below threshold voltage current is small. However, current decreases exponentially it will never go to 0 it will decrease with exponential rate and the rate is fixed and the rate is fixed which essentially says every certain milli volt current decreases by so many decades. In other words if I were to now look at the drain current versus gate voltage with the drain current in log log axis what you will see is the following this is i d s. Now, this I am plotting in log scale this is your v t h value very interestingly what you see is this is above v t h above v t h the variation is only linear or quadratic. So, it looks almost flat, but below v t h current starts dropping very fast, but at v g equal to 0 this is v g which is your off state current is never 0 remember that because this slope is determined by sub threshold slope. The typical sub threshold slope is always more than 60 let us say it is 100 milli volt per decade. It means that below threshold voltage every 100 milli volt decrease in gate voltage decreases your transistor current by one order of magnitude. In other words if you are v t well to be 600 milli volt 0.6 volt which is what you use to have in older generation technology this is 100 milli volt per decade and let us say you are on current you see on current really does not change once you are above v t it is only a linear dependence. Maybe here you will have 1 milli ampere and here you may have may be 3 4 milli ampere or so. Let us say this current is in milli ampere that is on current of a transistor. If you have a 600 milli volt v t threshold voltage and 100 milli volt per sub threshold slope you can very easily calculate that when I come from threshold voltage to 0 voltage gate voltage my current should come down by 6 orders of magnitude because every 100 milli volt decrease in gate voltage decreases the current by one decade. So, 600 milli volt decrease you decrease the current by 6 decades. In other words if you have a milli ampere current your off current is nano ampere very good because your ion by ion of ratio is now 10 to the 6 on current is milli ampere off current is nano ampere that is what we said at least we need to have 10 power 6 on to off current ratio. We have a problem today the problem is as per the scaling theory we have been decreasing the dimensions of the transistor. We have decrease the gate voltage when we decrease all the voltages supply voltage today's transistors operated 1 volt. So, we no longer have 600 milli volt threshold voltage today's transistors will have to have threshold voltage of the order of 0.2 volt 200 milli volt threshold voltage. In other words I am actually looking at a highly scale transistor today which has a threshold voltage of 0.2 volt from 0.2 volt it starts dropping, but look it can drop only at this rate it cannot drop faster than this because this is the fundamental limit. This is the fundamental limit which is fixed by our derivation that we had k t o r q does not change 2.3 does not change and m no matter what you do is anywhere between 1.1 1.2 you know 1.5 you know in that range you may try to do little better and may be bring it very close to 60, but 60 is ideal you see you can never do it better than 60. So, this cannot be improved. So, what does it mean my on to off current ratio is going to degrade phenomenally. So, when transistor is supposed to be off you will have large current. If fortunately if you have done some good transistor design you have improved this sub threshold slope from let us say 100 milli volt to 70 milli volt let us say you know then you know if you have 200 milli volt as your threshold voltage or 210 milli volt just to so that we get round numbers right. 70 milli volt is a sub threshold slope 70 times 3 is 220 milli volt and hence when I come from 220 milli volt to 0 volt I would decrease the current by 3 orders of magnitude milli ampere current will only come to micro ampere my on to off current ratio will suffer when transistor is supposed to be off you will have lot of leakage current right. So, this is a fundamental problem we have today. In fact, that is the reason why if you look at the historical trends in CMOS technologies. In fact, we always said that CMOS is so nice compared to BJT because there is no static power dissipation you see this is my CMOS inverter circuit when I apply let us say VDD is older generation technology 5 volt I apply 5 volt here PMOS is off PMOS is really off because you know in order to turn on PMOS you have to apply 0 you know when you have 5 it is compliment right you really are having very very low current because your threshold voltages here are of the order of 1 volt right you have luxury to have several decades of decrease in current and hence this leakage is this current is almost negligible similarly when you have a 0 volt which is a static case right when your input logic is 0 NMOS is supposed to be off right it is indeed off because NMOS will have a positive threshold close to 1 volt 1000 millivolt even if I have a 100 millivolt per decade which is easily achievable my current will come down by 10 decades 10 orders of magnitude of current is 10 orders of magnitude lower than on current and hence no static power there is no static power we always ignored static power and that is why if you look at the power as a function of CMOS technology generation you know let us say starting from 5 micrometer technology going to 1 micrometer and today going to you know 0.1 micrometer which is 100 nanometer and below right today we are talking of 16 nanometer 40 nanometer and all that power has active power that is when circuit is switching it is doing some work for you it is a useful power because you are extracting some work from the circuit passive power is circuit is not doing anything ideally it should be 0 power but it could still consume power but in CMOS in older generation technology you know your active power when we look at the active power your active power you know would be somewhere out here let us say and your passive power or a you know off state power or was almost 0 very very small in fact you know I can plot this in a log scale right compared to active power this is several orders of magnitude lower that used to be the case but today because of the sub pressure leakage off state current is trying to catch up with on state current you see and what has happened over the technology generations is that with technology scaling power per units transistor decreases but we also put large number of transistor in a chip and chips are becoming bigger and bigger and hence the total chip power is increasing although if you look at one unit gate that is more efficient as we have already seen earlier as per the scaling theory but now we are talking of total chip power here right this is the chip power which includes active power P active and leakage power leakage power was almost negligible but today the leakage power really is looking like this this is P static in today state of the art technology especially high performance state of the art technology your static power can be as much as 30 to 40 percent of your total power no humongous that is of course we do lot of very interesting things both at the technology level and system architecture level we put the device in sleep when it should not really do anything your mobile phone screen sets off right. So these are some very interesting system architecting that we do so that you we essentially disconnect the supply voltage because if we supply voltage is there all these transistor will leak phenomenally right but this is really a very serious problem and especially because today we are talking of mobile devices right and mobile devices are becoming technology drivers and we need to really arrest the static power and this static power increase is simply because of the fact that I have to decreases threshold voltage you may ask why increase the decrease the threshold voltage you have 1 volt supply right you still make the threshold voltage 0.6 and that is exactly what is done in so called low power technologies ok. If you really are worried not about performance ok if you have a microprocessor which goes in your cell phone and a microprocessor which goes in a desktop PC both of them presumably are done on 45 nanometer let us say however the transistors that go in desktop PC microprocessor are really called high performance low VT transistors because you do not worry about power there you get power from your you know wall socket right you know it is continuously supplies power but you cannot afford that you know you do not want to recharge your battery of a cell phone every hour right you are willing to hit get hit on performance you know if the download file download takes may be 10 minutes instead of 5 minutes that is ok but you do not want to waste power ok and hence even though it is a 45 nanometer technology you may actually say that ok I do not really need this VT I would really increase this VT and hence my on current will accordingly decrease on current would not be up here on current will be lower but what you really get benefit is your off current can be decreased ok. So, you know you do lot of such tricks really you know it also turns out you have today technology is called dual VT technologies you see the idea there is that you know typically you know when you have chip right you know such as microprocessor chip which is essentially a very high performance chip it turns out the speed of the microprocessor chip is really governed by some transistors in the so called critical paths of this circuit. In other words you have let me get this correct here you have this chip this chip may have million transistor a few hundred million transistor it turns out at the end of the day when you actually do lot of circuit design and analysis there may be only specific transistors in so called critical paths critical paths from input to the output that matter all others really do not matter it only is important to make these transistors in critical path very fast because these are the bottlenecks in your speed and it also turns out typically the trans number of transistors in critical paths may be 10 percent of the total number of transistors. So, let us say 10 percent of the transistors of 100 million transistors that you have are in critical paths and these can be done with low VT whereas 90 percent of the transistors that you have in the rest of the chip can be high VT transistors. Now, you are trying to get best of both worlds you want speed and you have discovered that speed is only dependent on certain number of transistors in your chip make those transistors very fast they may also leak more, but that is it is only a part of the total number of transistors 90 percent of your transistors have much lower leakage current. So, thereby using the so called dual VT technology in other words if you have N channel transistors you will have two flavors of N channel transistors. You have low VT N channel transistors which will be sitting out here very low VT very large current, but very small fraction of the transistor and large number of transistors will be sitting out here which are high VT transistors and as a result of that you get high speed and low power by doing this you know some trick intelligent way of doing process technology and transistor design. All this is not really there in electric field scaling theory right I mean it all assumes that all transistors are identical you know single VT for all transistors, but now we are saying no look this is a problem, but this problem can be solved by having this intelligent solution and hence we adopt this right. So, you know that sort of concludes the targets that we had today. So, narrow width effect is important that impacts threshold voltage we use trench isolation to overcome that sub threshold conduction is always there right because of the diffusion current you have turned off the MOS channel, but there is a diffusion current and you know because of that you have an implication on the off state current of the transistor solution you have ways to intelligently design technologies to overcome those difficulties as well. So, let us stop here and we will continue in the next lecture.