 This paper proposes an area-efficient unified hardware accelerator for elliptic curve cryptography, ECC, which combines wirestress, Edward, and Huff curves into one design. The proposed architecture is designed to reduce the amount of memory required while maintaining high performance. Additionally, it uses a modular multiplier and square arithmetic unit to reduce the number of operations and clock cycles. The resulting design is able to achieve higher performance than other existing ECC designs with similar resource constraints. This article was authored by Mohamed Araf, Almar S. Sambal, Mohamed Rashid, and others.