 So, in this what I plan to cover is a few more ARM processors ok, there are 20 of ARM processors after we having discussed on ARM 17.9 in detail about the instructions and what are the features of a particular processor base and then we talked about a lot on other memory management and cache and hamburgers and there are lot of lot many things we discussed. So, I would like to conclude this feature with brief introduction to various processor goals that are available in the market and what their target applications for which these processors are being developed. And so, this will give you some flavor of what on is there you know the learning about ARM is cannot end with this, it can in fact go deeper into the recent architectures, the features and the multiprocessor course which are very very unique and very interesting to go deeper into as well as lot of features which are DSD specific for Java support and you know there is a technology will be said in talk about. So, plenty of architectural innovation continue to be going on in the ARM family. So, you know support of 64 bit processor you know a lot. So, having gone to this course and having understood all the major functionalities, now learning about the feature processors and the advanced features will be very interesting and it will add on to your knowledge and suddenly the knowledge that you have gained through going to this course will be helpful to read up and understand future processors as well as you can be in architectural design being designing new processors ok. So, my intent was to introduce you to the beauty of architecture processor architectures taking on as an example because this is a very good example to take up to teach processor architectures and with a lot of practice in assembly language programming you will be you can become an expert in assembly programming as well as in the processor architectures getting up ok. So, let us go further. So, you all of you are familiar with instruction set architecture and then I will talk about few instruction set architectures you know what we saw so far was on repo now I am starting off with a 6, 5, 6, 7 and 8 ending with the 8. So, there is a 20 still coming and now there is a lot of innovations happening in this area and I am pretty sure that you will go deeper into the future areas and then contribute for new architectures and then the developing solutions based on these factors ok. So, this I have already talked about which I showed you in the earlier classes. So, this is where we spent a lot of time initially on the instruction that takes know every instruction in very little detail of ARM 70DMI which it is where ARM V4T is my essay sorry. So, let us talk you know see what are the additional instructions that are coming into it. So, you can say that this is you know everything is actually inclusive of whatever there is before. So, it has got ARM thumb mode ok extra instructions we have added and then enhance multiplication instructions and then DSP type instruction and Java acceleration ok as you all may be aware that Java runs on a byte code ok Java is converted into a Java byte code and then runs on Xenium. So, ARM provides that shall support a state where Java code can be run next natively on their architecture. So, with the architecture support Java execution will be possible and then you do multiprocessor instruction and then even accessing unaligned data as well as CND and data handling. This can be which have come into this ARM 9 and level families is called under this with the since that architecture. So, the intent of this course is to just give you the list of features and what all is there may be you know we do not have time to go in deeper into any of them, but this is a overview which will make you go into deeper you know by looking at the description of the description. So, in the view of based on your interest and what you are looking for ok. So, these are all different families and this is all the additional DSP and other instructions which are coming to different ISAs we will see them in detail. So, this is a higher level view of how the instruction that architecture has evolved. So, there is a security is very important especially in networking and there is a all the encryption and you know key generation those kind of things which are required for network protocols. There is a lot of support from the on developer with the separate module for it and then come to this additional add on to the some mode some state where not only 16 bit instructions that is included in the comes to a technology even a few some 32 is bit instruction set also gets included being in some state. So, actually the power of come to the some state has been improved as an understanding into in this introduction of this particular feature into ARM and then we saw the vector floating point processor and it is it is improved as well as there is advanced assembly architecture which has been went into the architecture you know and the V8 ISA has both 32 as well as 64 bit architectures. So, I will talk about this in the subsequent slides here and this model is also added to it. So, the plenty of additional hardware and features that have gone into this then design is our support. This is the overview of what are the features that have gone into the data processors. So, let us start with ARM V5 into the efficiency of ARM and thumb detail that is how they work together and then the new instructions just a few examples counting meeting zero. So, suppose we have bit pattern like this and then one and then some zeroes. So, suppose if there are no zeroes one after this now how many number of zeroes here ok that you can easily count using one instruction which will be there nothing you can give even if we may have to you know do a rotation ok or shifting operation to find out how many are there ok. So, it will be encoded as one in this course into a carry bit this has to be shifted to the left which will involve lots of taking. So, to avoid that there is no there are barely shifted is there which will take only one second, but what happens is we may have to see whether carry flag is set or not and then we have to find out we have to keep track of how many zeroes were there. So, it cannot be done with just a shift of where we may lose the number of zeroes that we counted. So, so that is why I am saying that it will involve lot of instructions, but whereas, if you have the two registers and then you say that I pass one and bit pattern you know one and bit value and then I want the count in another register. So, that will be easier to get run with a single cycle execution. So, this kind of features which have been added and then break point is another instruction which is actually when you are debugging inside the assembly you can put an instruction on break point. So, what happens is if the execution stops and then there is a debug unit inside the arm on this side ok inside the debug debug for debugger as I mentioned some hardware you where you set it you know unit and then some debugging capabilities are built into the hardware. So, when it encounters a break point instruction then the control is forced on to be debugger. So, the execution stops and then later on what happens is this will be replaced with another actual instruction. So, based on the break point that you set in the debugger that particular instruction is replaced with the break point instruction in the assembly and then when it reaches there it will come to the next level suppose if you are giving a every instruction in the assembly then this will be possibly put into the instruction which is getting executed. So, let us process the break stop you can contact this kind of features are very very important for debugging purpose and then introduction of any variant this is a DSP processing of course, now DSP algorithms there are you know instructions you know instructions have been added very easily. So, if you see we execute the number then it is actually a DSP features are added to it from the instructions which we help you in implementing DSP not that it is a implemented algorithm, but from the instructions which we help you in developing DSP algorithms which is normal process. So, a J variant is the for Java generally a architecture execution is there. So, by code it will be written as a standard code. So, that is all about v5 from 7, 3, m, i ok these are the enhancements in the next ISA which came up. So, DSP has come Java components from and then few instructions and then it will be got there as the new code. Now, we see the next instruction that I have. Here what happens new instructions for in do with the exception handling. So, exception handling handling has become much simpler with the you know additional instruction and then extremely access instruction. So, this will you know from month and then multi-core processors where you have variables which are to be accessed with the concurrency of other processors ok. So, it should be exclusive of the processor to be done where the particular variable is shared between two processors. So, it is useful in the multi-core system and this exclusive access instruction help you in achieving that. So, how do you do with that? A set of any instruction essentially media instructions as I have know may be the same amount where is the lot of media instructions have been implemented and supported in the processor. And additional function only instruction is assimilated into a 64 processor. So, some more multiplication instructions have been added and the both virtual and instruction memory system have been derived. And then a new we saw arm and thumb state, but thumb to technology is the little improvement on that from v62 or you know versions. So, what exactly this does is you can have both thumb state between the instruction as well as a few particular instruction space ok in the thumb state. So, what happens is here the format is different ok you may wonder what is the another particular instruction that arm support. So, arm instruction if you remember they were always a 4 bit value which is conditional flag. It was most of instructions before have this conditional flag. So, in the thumb to technology the some other particular instruction which have been introduced in thumb state or do not have this option. So, it is used for some other purpose the input it can be used for some other purpose. And then the conditional where a conditional instruction is given by another instruction. So, that instruction has been added. So, there are lots of improvement like this. And come to the major enhancement of the instruction which act effectively with the instruction mostly and conditional that can be really intermixed with the instruction you know. So, in the original arm seven when we are in thumb state we are restricted with you know we have to operate only with a few instructions. We did not have the flexibility of using technical instruction in thumb state, but that instruction will be removed from after introduction of the instruction. Similarly, I gave a small instruction about tightly coupled in memory. So, that support has been you know given from V6 new hardware support for word accessors are to be two byte aligned. So, there is no question of reading it half word which is not two byte aligned ok. So, that instruction has been removed ok. So, you can even even if it is not aligned you know not both it will be read for you know and load. So, that time that instruction has been removed ok. So, you can even even if it is not aligned you know not both that kind of flexibility is there formalized adoption of debug architecture. So, co-processor 14 is reserved for a debug architecture and it has been formally included into the architecture definition. And high vector extension say so far we have seen that interpretable has to be at the 0 of the hybrid right. The IVT interpretable needs to be at a 0. So, some cases where this memory cannot be given for you know initializing the interpretable some systems will have issue because of this right it cannot be anywhere help. So, this location is reserved for that purpose. So, the vector extension has been given and then it has been the mandatory from the V6. So, another after higher address also is for that purpose. So, that helps you in terms of deciding where the interpretable is and then on this it appears that base restored abort model is used. Here then it can be only base updated abort model. So, if you recall suppose we were doing the LDM or HM inspection ok which has got a base which is there of course and then it was talking where from memory to multiple copies of memory to register or LDM registration memory. During the time if there is an abort then if you recall we mentioned that in the arms on delivery it will update the base register as if this inspection has been successfully implemented ok. So, you will always see that updated abort model only when it comes to abort exception this base register has been updated. But from basic there is a support for restore abort model that means when it comes to executable exception it would have been restored as if nothing has happened. So, if it is restored it is easier for after the exception to restart the inspection because you do not see that the base will be changed when you enter the exception handler whereas in the previous case it is updated. So, the exception handler has to replace where there in the register and then how many would have been updated to and then go back the base register value to the original and then start it. So, it would it was little involved in terms of you know writing a lot of code in the exception handling. So, now that has been removed. So, we can choose one of this model and mostly you may prefer this because we want to restart the and let it happen. So, that is all about V6. Then talking about V7 the next advanced ISA of on is a optional floating point extension. So, that has come in enhanced exception and memory model. So, both exception and memory models are given now. So, I am not going to give you because it is pretty involved. So, we do not have time planned it for covering all of that. So, our focus was to learn everything about 70DMU which you have done. Now, I am just giving you in a in a cell what all has happened after that. So, it is interesting to know you know we should not think that no arm 70DMU will be the best architecture way, but there is the better than architecture then that is there from our company. So, it is better to be aware of that. So, people architecture that provides software access so, this is a lot of great point and other features that that can be accessible software of the building of V7. And optional SMB and 50DMU as I told you in the section and that seems to be implemented in this. It is also defined the virtual and protective memory system aspect enhanced both memory models. Now cortex wave series ok it is a family of application process of complex voice and user aspect ok. It follows this arms V7A. So, A means application process and comes to technology which I have mentioned we about ok now. So, this if you hear cortex family which is immediately remember that ok you know this at least the some of the almost 7A PSA. So, that will help you to know what are the features are there in that particular period. So, there are 20 of processor number A5, A7, A4. So, A4 is a magical processor. So, let me tell you what are the features in this process. So, cortex A5 is the smallest member of the cortex wave of the family. Remember this is ok V7A let me write it here. So, that is the instructions that are taken there high performance low power with the alone catch ok. So, this is the smallest member. Then A7 NP go to large physical address expansion expanding the physical address accessibility and media processing as well as advanced and then A8 provides free virtual memory technology ok. That is another I am going to question that. So, this is the how the complexity increases and the features get added. So, the previous features are also supported so that they are not mentioning them. Only the additional things is that also not all of them and just highlighting a few of the features which are there. So, from A9 A5 Java byte code in general state were introduced. And then A15 NP that little advanced to other course. So, you can imagine what we saw in 7 CDMA was a 3 stage pipeline right. Here 15 stage pipeline ok. And out of water super scalar what I mean by out of order is the program assembly sequence will be in some way ok. Now, if the processor has multiple ALU multiple Mali Mali is there add unit is there. Now, this super scalar what does it do is it insert all the instructions and then schedules them if there is an execution in it available and there is no dependency from the previous instance. So, in the particular 7 CDMA what we saw was all the instructions go in the same order in which it has been written. Whereas in super scalar though as a program is there may be this instruction can get executed before ok before this completes because may be this is the Mali instruction and then this could be done with the add or no one. But character is assured because in you know it is this instruction the later instruction is not dependent on the previous instruction execution completed. So, what really we gain is the processor keeps all the execution units and the Mali instruction may be the executing the instructions ok it is it fits dynamically allocates the continuous instruction so, improving the performance that has been added in this it is all I mean you know advanced architecture features and tightly coupled low latency L2 cache. Now, you will see that L2 cache after that L1 cache was there previously and L2 cache after that. And then we because as you know only the course can be made. So, multiple process we have worked as in this discussion but that is very interesting and rest of research is going on in the multiple processor and issues that are there in sharing data between the now cache coherency that is cleared with 20 of research and 20 of instructions on multiple processor architectures. And what a case is being running up to this kind of processor. And what are the applications which are now useful for advanced smartphones whatever new latest smartphones you have mostly you will see that there will be an arm coordinate and there will be an arm coordinate mobile control range as well as high end digital coordinate and wireless infrastructure. So, that is the one great thing that now it the arm is the wireless infrastructure that means BTS are and then you see that your mobile is there ok and drawing it like this but no mobile is having an antenna like this just to make you understand that this is the mobile. So, the tower that you see which is the mobile is up to even the tower has arm based processors in it it will have its own network processor or other additional hardware added to that to enable the wireless protocol to run efficiently. But there are high end arm processors which are used in the wireless base station. And you see that a low power arm processor also there in the mobile so you can see the rate of the presence of arm in the network in domain so the arm a 15 for after a 15 you know can be used for this infrastructure also and it is being used ok. And then low power servers it now arm cores are going into the server environment. So, the enterprise server environment the powerful multi power processors are going in rate. So, it is not only low power and used for only embedded system it is also arm cores are used in servers and the enterprise environment. So, the wide variety of family of processors coming from arm has enabled it to penetrate into different market not only restricting to its own embedded mobile or embedded template or embedded product it blessing to wide variety ok. Into the network and you know both wireless and the wired network infrastructure as well as in the server environment. So, this is something which we should be aware if you say well that you know I have gone to arm and I have come down maybe then there will be some questions on this so it is very interesting innovative idea in arm so what it really does is it plants a high performance core ok like part of a 15 multi core processor with a power optimist companion core. So, it is a two family you know two is both are arm processor both are from arm really but this is a 15 ok and then there are two cores co-exist in the same story ok. Now what is the advantage actually when you are running a process ok the OS running there knows which core this is a 15 and which is a 7 and then it can optimize there by choosing an up and down right right core for right processor application. So, it could even move into this and then move it back into this based on you know what processing is involved so you may wonder why is there a need to processor. So, this is a big big little means this is a big processor that means very powerful in terms of performance and of course, in terms of consuming power core ok. There are case 7 is a low end you know it is not as high performance at a 15 core but it consumes less power. Now if if a solution has both a core in it and then application based on the more in it we might have heard about sleep mode and hibernate mode so many things right it is all done to save battery. So, whenever there is no need for this high end processor to be running then the task the job is given to the low end processor and which will take care of mundane task and then which is not does not involve similar performance. Task which is not performance critical is done in this low low end core. So, it is by keeping these two together in a solution we get the advantage of low power at the same time performance of a high high performing device. So, it is a combination of both and it is done using this core link because it is an you know the private I will show you some diagram that enables sharing memory and then where you will draw data between two multi core processors and both we can detail processor ok. Fine this sharing solves the quantitative challenges of increasing the performance by increasing the back to back. So, that means by reducing the power consumption by ensuring that the high right processor core is assigned to the right part. So, the task is inverse high performance core will be assigned to this a 15 core and then the task which is involved a low end job will be done by the arms. So, if you try to do a low end job between these four you will be wasting the you know power. So, this is a better optimization of this. So, the core link cache covalent network offers sharing to 16 percent. You can imagine that a 15 processor could be there in the ISOC. So, this core link is a covalent network this is also defined by arm and it can connect multiple cores using this and it is a very easy to implement also in terms of design. So, time to mark it is good. So, an optimal solution for enterprise application because you know you may need 16 processors kind of a powerful processor only when the enterprise application. So, after lower or mesh working processor this processor core can be used. So, this is the idea of big detail. So, if you know in a single solution in ISOC have one bigger high performing core and then low end core also and then the software as well as the hardware running there you know you can with the support of hardware we will be able to alert a particular core for a particular processor. Now, moving on to V8 let us see what are the extensions architecture extension for many videos. So, this I told Java acceleration as well as security as zone is called well done in the same this is all I have already listed on. Now, V8 architecture adds cryptographic extension to it apart from all this you have seen in V7 and this architecture adds cryptographic extension. And then the extension of the basic as we enable ARM processor actually a good balance between high performance and the low power and small core base and that means, yeah. So, this is a very good compromise between V2 and good balance between them. Now, V8 provides there are multiple family of processors and ARM architecture forms the basis for every ARM processor of course. Over time ARM architecture has evolved to into architectural features to meet growing demand of high performance and meet up new emerging market. So, there are currently now two ARM V8 profiles ok. One is V8A which is meant for enterprise ok or mobile high performance market and that one is R which is the real time solutions which are embedded applications and automatically one industries. So, you can you can find out from the target it is aiming for this is high performance device architecture with the may be power consumption will be more but high performance. Here real time embedded applications responsive time will be very very good and power construction is better. So, but it follows the same V8 architecture yes same ok. So, what all is there in V8A that is application processor with a high end enterprise unit of V8 processor we suppose 64 bit ok. So, what are the but maintaining the same power efficient implementation. So, in 64 bit what happens is the addressing range become 64 ok. So, far we saw that 32 bit addresses and it was 4 GB was the limit. Now, 64 bit gives you a wide range of address ok. So, and it access the performance also because 64 bit processors are there a greater addressing range as per cryptography instruction it has been in the V8 and a 64 bit general processor so all are 64 bit and as you know exclusive experience PC it is not part of general processor as we have seen in the previous architecture R-perfume and R-perfume. So, that restriction has been removed and it has got a 64 bit data processing as well as extended virtual addressing mode and they have two kinds of execution states ok. So, 64 bit execution state as well effectively. So, maybe you can have much of both in the implementation ok based on the application. And then let us see a few examples of on a this part is one you saw up to 15 now got a 53 quality on V8 architecture ISA power efficient processor was supporting 64 bit code in USB ok. Highly efficient 8 stage in-order pipeline ok. You saw out of out of of execution super strategy in the previous discussion right. So, here it is an in-order and what we saw in 7.2 that by entry levels smart mode ok. And it can be a standalone application processor are paired with a a 57. So, 53 can be a low end one and 57 can be high end. So, we can be parallel you know pair following the big little technology that I have discussed. So, 57 of course it is a high end processor with multi core processor but out of order super scalar. So, you can include this and 57 and 53 to form a big little configuration ok. And it has got a low latency level to that also. And it actually this I have talked about the coherence in the base source interface. So, this amplifier and score is compatible with this particular processor ok. So, an example of this so, multiple cores up to 3 are there in this ok. And then the core link helps in connecting all this cores multi cores we each each of them is up to 4 cores cluster cluster each block what you see is a cluster which is got the core L2 cache in them of course if L2 is there L1 is inside ok. As well as multiple processor cores are there. And this 8 core clusters can be interconnected using this cache coherent network with a shared memory which is the unicom system memory. So, they can share using this link they can communicate over this. So, it is the AMBA high level you know versions of AMBA specification again. And then there is a L3 cache also present in this L3 cache and then we saw we see that you know the DVR3 and 4 these are double deteriorate external memory can be interfaced using this DVR3 and 4 interfaces and then peripherals are on this bus ok flash and GTIU all could be placed here. And then you can see that some some other cores here ok DHP core is here ok you know DHP core is here and then we have GPU you know GPU is also Mali that is the processor you can just go through that the graphic processor from ARM ok. And then other interfaces are time interface for the hard disk and then PCIe for you know other peripherals so there is three of things could be there you know this link helps to achieve in this ok. This is a simple example of how complex the ARM disk position will be with multiple cores in them memory in them. So, these are all used for networking process are enterprise solutions or server of it ok. So, ARM V8 RSA this is a R series I told you that this is a real time series so for that Cortex R series is a family of embedded process for real time systems. It has got a R4 which is a mid-range real time processor ok. There are also multiple family of process so, you see that R4F it has got a CPU support R5 is for high performance ok and then if you see F it has got a CPU support. So, embedded application you do not have to think that it may not made a floating point processor because there may be for advanced processing involved in the real time system we need a floating point processor. So, there should be a processor architecture which is meant for real time systems which allow for our capabilities as well as has the floating point processor in it. So, we can choose based on the application whichever processor suits our needs. Cortex R7 NP-core processor is a high performance multiprocessor and using all kind of deeply embedded application ok. Even we like you know there are lots of embedded applications where multi-course are used ok. So, this is the right choice for deciding the situation. So, with this we have come to the end of this session as well as we are end of this course. So, here what I intended to do I level overview of various inspections of architectors and then some of the features and a later technologies which are there in both for application domain as well as real time domain. So, it has been a great journey and I really appreciate your perseverance to learn and having continued on this particular vector. I really enjoyed sharing a lot of information both on. And I I argue to not stop with this actually the intent of this course was to create interest in the minds of the people is a natural interest. Once you go through this once you know how one processor behaves how it you know why it behaves the way it is and then how it is actually executing the instructions how what is inside once you are aware of that it really opens the way for knowing more and more about processor architectors. It not only makes you confident about processor architectors it also makes you confident about what is happening underneath. So, most of the time when we develop software computer science background and we develop software we always assume sometimes that ok hardware is something which I do not have to worry about ok that mindset is actually very very wrong for you to be a successful software engineer you need to have a good hardware knowledge. In the sense you may not be a good real estate designer, but you should know processor architectors how it behaves why it behaves the way it is so that you will be able to exploit the support provided by software architectors. Similarly if you are on a real estate area and you are designing a big processor or SOC you may wonder that my area is hardware so how should I bother about this word please remember whatever we design as real estate engineer we want the software engineers to run their software on our hardware. So we need to take care of what they need what their interest are we need to make them run their software on our hardware efficient with minimal power with the high performance. So the hardware and software interaction is very very essential to be a successful engineer or a system designer ok the knowledge of both will actually help you out in terms of building a solution which is which meets the requirement of the software in the you know whatever hardware wants it is there in the hardware and then similarly software is tailored or written in such a way that the hardware features are exploited and they are used properly so that should be a dialogue a constant dialogue that is in these two workings for building a successful system so my intent was to bring that kind of a favorite there doctor bought lot of architectural feature but I also gave you some why it is used a particular feature enough in the software world so knowing both actually make you a successful engineer and at the end of the day you feel that you know what is happening the software when it is running on a particular hardware we know what is happening in the hardware so that really makes you comfortable and especially when you are in debugging something when there are some some problems and the crash is the software is not working then then only you will see the handicap of not knowing what is happening in the hardware okay and similarly when you are a design engineer when you are developing a hardware and software architecture and designing new software architecture you need to keep in mind what would be the requirement of the software designer what can be added to the solution so that it is easy for the software to run on them so these two kind of a they have to hold hands together and won't make a journey then only the system that will will be successful and I hope I have made a small contribution towards this and my intent was to make as well as appreciate both the size of the world okay and both are interesting in its own way and knowing something about one side and knowing everything about other side will be always helpful for you to be a successful engineer either you are on this side of the fence or other side of the fence but I don't want to call it as a fence but there should be this particular what are the areas should actually vanish and the engineers should work together understand each other's issues and problems and the requirement so that under the date what is required for the users and we can make the world better and safe because if you are an embedded software engineer or a hardware doesn't matter whatever you do might be very very time critical in the sense it can also be like determining too so it is very important that whatever we do we do a good job of it quality is very important and whatever what we do doesn't matter whether software or hardware please make sure that it's our way of testing and understand what is happening so that you take care of all the conditions it's not that if the system that we build should go to the field or the customer premise that to be tested we have to anticipate all the worst case scenarios that could happen and then build our solutions so that we really meet the requirements of the end market as well as the customers and we make systems that we prefer and it consumes less power so that it is economical in sense equivalently as well as it is a past perspective it is economical and it needs the requirement of the people and thank you very much for all your help and all your support during this time and I hope it was useful and I really enjoyed and if you can take any time for any characterization or help I really appreciate you and I wish you all the best for your career in whichever part you take and I also wish you if you are interested in taking a process architecture as well so that we are asked to further go deeper into it I really appreciate if this you take a process architecture as your goal and your future career thank you very much and I wish you all the very best thank you bye bye