 In today's session, we are going to get introduction about IC-55 timer. At the end of this today's session, students will be able to describe the features, PIN diagram and internal functional block diagram of IC-55 timer. These are the contents of today's presentation. You have already studied a flip-flop and the different types of flip-flops. Please recall what is SR flip-flop. SR flip-flop is one of the internal functional block of IC-55 timer. SR flip-flop is set-reset flip-flop. It has two inputs and two outputs. The two inputs are set and reset and the two outputs are q and q bar. The two outputs are complement of each other. When set input is high and reset input is low, flip-flop sets. Its q output becomes high and q bar output becomes low. High output equals high voltage level and low output equals low voltage level. When reset input is high and set input is low, flip-flop resets. Its q bar output becomes high and q bar output becomes low. So, q bar output equals high voltage level. So, flip-flop remains in one of the stable state, either in set state or in reset state. Using S input that is set input, we can set the flip-flop, make q output high and q bar low and using R input that is the reset input, we can reset the flip-flop. Its q bar output becomes high and q output becomes low. The IC-555 timer is most versatile general purpose linear integrated circuit named as AC-555 or NE-555 from manufacturing company Signetic Corporation. It is highly reliable, easy to use and cheaper in cost. It is a timing circuit that can generate very accurate and highly stable time delays or oscillations. IC-555 timer has a variety of applications like monostable, multi-operator, a stable multi-operator, waveform generator, digital logic probe, etc. Now, let us see the features of IC-555 timer. IC-555 timer operates on wide range of DC power supply voltages from plus 5 volt to plus 18 volt DC. It operates on wide range of temperature. The temperature range for IC-555 is minus 55 degree centigrade to 125 degree centigrade. For IC-555 timer, NE-555, the operating temperature range is from 0 to 70 degree centigrade. The output voltage level of IC-555 is compatible with TTL logic circuit voltage levels as well as CMOS logic circuit voltage levels. The output signal voltage level of IC-555 timer is equals with TTL voltage level as well as CMOS voltage level. The output of IC-555 can source or sync current up to 200 milliampere. IC-555 timer generates a timing from nanoseconds to hours. Basically, IC-555 timer can be operated in two modes, a stable mode or monostable mode. These are the two basic operating modes of IC-555 timer. This was a pin configuration of IC-555 timer. Physically, IC-555 is available in two packages, DIP package and metal can package. It is an 8 pin IC. Pin number one is a ground pin and pin number two is the trigger input of IC-555. Pin number three is the pin that is output of IC-555. Pin number four is a reset input for IC-555. Pin number five is a control voltage input for IC-555 and pin number six is named as a threshold. It is an input for timer IC. Pin number seven is named as a discharge and pin number eight is a plus VCC. This was internal functional block diagram of IC-555 timer. Internally, IC-555 timer consists of a voltage divider which consists of two equal resistors. It is acting as a resistor network and it consists of two voltage level comparators, comparator one and comparator two and a single SR flip flop. And the two transistors, transistor Q1 is a discharge transistor and transistor Q2 is a resistor transistor. The resistor network which consists of three equal resistors acts as a voltage divider. It is used to generate threshold voltage or reference voltage for a comparator. It generates reference voltage of two-third VCC. It is applied to inverting input of upper comparator, comparator one. And it generates one-third VCC. It is applied as a reference voltage for non-inverting input of lower comparator, comparator two. The voltage level comparator compares voltage applied at threshold input with the voltage applied to inverting input. And comparator two compares voltage applied at trigger input, number two with the reference voltage of one-third VCC from internal voltage divider. The output of two comparators are given to set and reset input of a flip flop. When the voltage at non-inverting input is higher than the voltage at inverting input output of a comparator becomes high. So that is given to set or reset input of a flip flop. When set input is high and reset input is low, flip flop sets. So its key output becomes high and Q1 output becomes low. When output of comparator two is high, it resets a flip flop. And so that Q1 output of a flip flop is high and Q output is low. Transistor Q1 and Q2 are used to, Q1 is used to discharge external capacitor and Q2 is used to reset a timer IC. Now let us discuss the pin configuration of IC triple-oper timer, pin description. Pin number one is a ground terminal. All voltages are applied and measured with respect to this terminal. Pin number two is named as a trigger terminal. This pin is nothing but inverting input of internal comparator two that causes a transition of internal flip flop from set to reset. Internally, this pin is connected with the inverting input of a lower comparator. The comparator compares a voltage at this pin with one-third VCC. So whenever the voltage at pin number two becomes just less than one-third VCC, the output of lower comparator that is comparator two becomes high and that resets internal flip flop. So that the output of timer becomes high. The output of timer depends on the voltage level of trigger pulse applied to this pin. When the voltage at pin number two just falls below one-third VCC, the flip flop resets and its Q output becomes high and Q output becomes low. Pin number three is named as output terminal. The output signal of timer is high level at this pin with two possible voltage levels, either high voltage level or low voltage level. The output load can be connected either between pin number three and ground pin number one and the load is known as normally off load or it can be connected between pin number three and power supply pin pin number eight known as normally on load. The output has two possible voltage levels either high voltage level or a low voltage level. Pin number four is a reset terminal to disable or reset timer at low voltage level or negative pulse is applied to this pin. That's why it is known as a reset terminal. When it is not used, it is connected to plus VCC to avoid false triggering. Pin number five is named as control voltage terminal. This pin is internally connected to inverting input of comparator one. This pin is used to control or change threshold and trigger levels by connecting external potentiometer in between VCC and ground and its variable terminal is connected to pin number five. When this pin is not used, connected to ground pin one through 0.01 microfarad capacitor to avoid any noise problem. Pin number six is a threshold terminal. This pin is connected with non-input input of internal comparator one. The comparator compares the voltage applied to this pin with the threshold voltage that is the reference voltage of two-thread VCC obtained from internal voltage divider. If voltage at this pin is just above two-thread VCC then flip flop sets and output of timer is at low level. Pin number seven is named as a discharge terminal. This pin is internally connected to collector of N-pin transistor. Mostly external capacitor is connected between this pin and ground. When transistor turns on, capacitor discharges through transistor. Hence this pin is named as and this transistor is named as discharge transistor. When transistor is off, the capacitor charges at the rate decided by the time constant of external capacitor and resistor. Pin number eight is a supply terminal. A DC power supply voltage of plus five volts to plus 18 volts can be applied to this terminal with respect to a ground pin. For the working of IC-555 timer. This is the reference. Thank you.