 Hello and welcome to this presentation of the STM32L5 USB 2.0 Full Speed Interface. It covers the features of this interface, which is widely used to interface with a PC. This figure shows the connections between an STM32L5 microcontroller and a USB connector. The STM32L5 features a USB 2.0 Full Speed Communication Interface, allowing the microcontroller to communicate typically with a PC. The simplest implementation is a USB peripheral device. It provides a 16 endpoint capability, which can be configured, for example, as 8 bi-directional endpoints. It also supports the battery charging detection specification version 1.2. Application benefits include crystal-less operation, a low power implementation, and faster charging, thanks to the charger detection function. Let's look at some of the key features of this USB Full Speed Interface, which is a USB 2.0 compliant interface that operates at a 12 megabit per second bit rate. A USB FS device can be implemented. Crystal-less operation is supported. A total of 16 endpoints, 8 bi-directional, can be supported. Full support for isochronous endpoints. Bulk endpoints are able to use a double buffering mode offering higher performance. Inbuilt support for link power management adds enhanced power modes on top of the USB 2.0 specification. Battery charger detection allows for increased current to be drawn from BCI 1.2 compliant chargers, allowing up to 1.5 amp charging. The block diagram of the USB Full Speed Device Controller shows the various building blocks inside along with its analog transceiver, which manages the physical layer shown above. The physical layer, or FI, handles the analog signal levels including specific level detections as well as battery charger detection functions. The USB Interrupt goes to the Cortex processor to signal various USB events. The AHB Peripheral Bus, or APB, enables read-write access of the controller. Other key elements are the packet buffer memory and the suspend timer allowing low power operation. Several related peripherals work in conjunction with the USB Device Controller to link the USB activity to the system power mode and the requirements of the software. The clock recovery system allows operation without an external crystal using the integrated HSI oscillator as the main clock source. The interrupt events are sent to the non-vector interrupt controller via a single line. The system events can cause the system to wake up from stop mode. For example, at the moment we resume from USB suspend mode. The USB Device Controller generates interrupts in different circumstances which generally require handling by software. The first two listed interrupts cover various error and warning conditions. The remaining interrupts correspond to normal USB protocol events. The USB Peripheral is fully active in run mode. After a suspend event, it is still active in sleep, stop zero, and stop one modes. Standby mode should not be used. The USB Peripheral is not available in low power run, low power sleep, and shutdown modes. Some debug help is available using a single status bit which corresponds to an interrupt event. Within the USB Device Controller, the dedicated ERR status bit provides some debug functionality in a USB application in relation to various events. The events that can trigger this debug bit are listed in this table. There is also a way to directly read the states of the D plus and D minus lines. Here is an application example of a low power peripheral device. Power is drawn directly from the USB VBUS signal. No crystal is required. For complete USB specification documents, please refer to usb.org. The USB 2.0 document home page has a zip file containing the USB 2.0 and OTG 2.0 specifications and an engineering change notice or ECN for link power management or LPM. The USB Device Class Documents page has the battery charger specification. Additional information can be found in these application notes.