 Hello, and welcome to this presentation of the STM32H7 power controller. The STM32H7's power management functions and all power modes will also be covered in this presentation. The STM32H7 has several key features related to power management, including several low power modes, where it is still possible to wake up the MCU with an event on an I.O. as well as a large number of peripherals that can wake up from the various low power modes. The D3 autonomous mode allows transfer of data on communication peripherals without waking up the CPUs. Several power supplies are independent, allowing reduction of MCU power consumption while some peripherals are supplied at higher voltages. Thanks to the large number of power modes and independent power domains, STM32H7 devices offer high flexibility to minimize the power consumption and adjust it depending on active peripherals, required performance, and needed wake-up sources. The integrated step-down converter reduces STM32H7 power consumption at minimal cost. STM32H7 devices have several independent power supplies, which can be set at different voltages or tied together. The main power supply is VDD, supplying almost all IOs except for some IOs of ports A, C, and B. VDD also supplies the reset block, temperature sensor, and all internal clock sources. In addition, it supplies the standby circuitry, which includes the wake-up logic and independent watchdog. VDD supplies the step-down converter, which may directly provide the V-core supply. V-core supplies the three domains, CPU1, Cortex-M7, CPU2, Cortex-M4, and D3 domain with most of the digital peripherals and the SRAMs. The flash memory is supplied by both V-core and VDD. V-core may be supplied through the voltage regulator, which is supplied on VDD LDO. The STM32H7 features several independent supplies for peripherals. VDDA for the analog peripherals. VDD50 USB and VDD33 USB for the USB transceiver. VDDDSI and VDD12DSI for the DSI physical layer. The VRF plus pin provides the reference voltage to analog to digital and digital to analog converters and can be used as an external buffer reference for the application. A backup battery can be connected to the VBAT pin to supply the backup domain. The main power supply VDD ensures full-featured operation in all power modes from 1.71 up to 3.6 volts, allowing supply by an external 1.8-volt regulator. Device functionality is guaranteed down to 1.62 volts, the minimum voltage after which a brown-out reset is generated. Other independent supplies are provided for peripherals operating at a different voltage. The analog power supply VDDA can be connected to any voltage other than VDD. When the analog to digital converters or comparators are used, the VDDA voltage must be greater than 1.62 volts. When the digital to analog converters or comparators are used, VDDA must be greater than 1.8 volts. When operational amplifiers are used, VDD must be greater than 2 volts. The USB regulator supplied from VDD50 USB at 5 volts generates the USB power supply VDD33 USB. When the USB is used, VDD33 USB must be greater than 3 volts. The DSI regulator supplied from VDDDSI greater than 1.8 volts generates the DSI power supply VDD12 DSI. When the DSI is used, VDD12 DSI must be greater than 1.2 volts. The backup domain is supplied by VBAT, which must be greater than 1.2 volts. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator, and the 128-byte backup registers. The ADC and DAC voltage references can be provided either by an external supply voltage or by the internal reference buffer. This allows the converter's performance to be improved by providing an isolated and independent reference voltage. The SMPS step-down converter or SD converter can be used in three different modes or disabled. 1. Directly supply the V-core domain as shown in configuration 2. This offers the lowest power consumption. 2. Use to supply the voltage regulator at an intermediate supply level as shown in configuration 3. This offers low power consumption with a low noise V-core supply. 3. Use to supply external circuitry as shown in configurations 4 and 5. In this case, the voltage regulator can still be supplied from the same external supply provided by the step-down converter. 4. Disabled as shown in configurations 1 and 6. This offers a low-cost solution at higher power consumption rates. At STM32H7 startup, the supply configuration is programmed in the PWR controller's CR3 register. This register is right once to protect against accidental overrides. The step-down converter cannot be used to supply the STM32H7's VDD supply, but can be used to supply the VDD-IO2 supply. When directly supplying the V-core domain, the step-down converter provides the supply level according to VOS and SVOS scaling. The step-down converter's operating mode follows the device's modes. When used to supply the voltage regulator, the step-down converter may provide an intermediate voltage at 1.8 or 2.5 volts. The step-down converter's operating mode follows the device's modes. When the step-down converter is used to supply external circuitry, it may provide a voltage at 1.8 or 2.5 volts. In this case, the operating modes are fixed to high performance. When used, the voltage regulator provides the V-core supply level according to VOS and SVOS scaling. The voltage regulator's operating mode follows the device's modes. When the V-core is supplied from another supply, the voltage regulator is placed in bypass mode. The backup regulator is used to keep the context of the backup REM in standby and V-bat modes. The backup regulator is enabled by the BREN bit in PWR Register CR2 and checks its readiness before entering standby or V-bat mode. An independent USB regulator generates the VDD33 USB from a 5 volt supply. The power supply supervisor ensures dynamic power supply management. STM32H7 devices embed power management on main VDD, analog VDDA, V-bat supply input, V-core domain, backup VSW domain, backup regulator VBKP supply, step-down converter VFBS MPS, USB interface VDD33 USB supply, and DSI V-CAP DSI supplies. The main VDD supervisor handles reset management and voltage detection via the Programmable Voltage Detector or PVD when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby modes. Seven thresholds can be selected by software. In addition, comparisons can be done with an external pin. The analog VDDA supervisor handles voltage detection via the analog Voltage Detector or AVD when VDDA crosses the selected threshold. The AVD can be enabled in all modes except standby modes. Thresholds can be selected by software. The V-bat supply voltage is monitored to detect when V-bat crosses the minimum and maximum thresholds. The V-bat voltage detection function can be enabled in all modes. The main V-core supervisor handles reset management and over voltage detection. The backup domain VSW supervisor handles reset management when the supply drops below the operating level. The backup regulator VBKP supply supervisor verifies that the regulator is ready to supply the backup RAM before entering standby mode. The step-down converter VFBS MPS supply supervisor verifies that the converter is ready and the supply is at the selected level. The USB interface VDD33 USB supply supervisor verifies that the USB interface supply is present. The USB supervision can be enabled in all modes except standby modes. The DSI regulator V-CAP DSI supply supervisor verifies that the DSI regulator is ready to supply the DSI interface. The VDD power supply supervisor guarantees a safe and ultra low power reset management. STM32H7 devices embed an ultra low power brownout reset or BOR which is always enabled in all power modes. The BOR ensures reset generation as soon as the MCU drops below the selected threshold regardless of the VDD slope. Four thresholds from 1.62 to 2.78 volts are selected by an option byte programmed in flash memory. The BOR consumption with the 1.7 volt threshold is indicated in the datasheet. The temperature supervisor detects when the junction supervisor crosses the minimum and maximum thresholds. The temperature detection function can be enabled in all modes. The battery charging feature can charge a super-CAP connected to the V-BAT pin through an internal resistor when the VDD supply is present. The charging is enabled by software and is done either through a 5 kilo ohm or 1.5 kilo ohm resistor depending on software. Battery charging is automatically disabled in V-BAT mode. By allocating peripherals to a CPU or the D3 Autonomous mode, the boundary of the subsystem can be controlled. The subsystem will follow its associated CPU or D3 Autonomous mode operating system. This is used to optimize the subsystem's power consumption. Peripheral allocation is done in the RCC via the P-E-R-X-E-N and P-E-R-X-A-M-E-N register bits, enabling the automatic wake-up of the domains associated with the woken-up subsystem. When CPU 1 is in C-run mode, the fixed allocated D3 bus matrix and D3 bus matrix peripherals are clocked. Other peripherals may be allocated as needed. When allocating a peripheral in the D2 domain, the D2 domain will be powered and the D2 bus matrix with its fixed peripherals and the CPU allocated peripherals will be clocked. When CPU 2 is in C-run mode, the fixed allocated D2 bus matrix and D3 bus matrix peripherals are clocked. Other peripherals may be allocated as needed. When allocating a peripheral in the D1 domain, the D1 domain will be powered and the D1 bus matrix with its fixed peripherals and the CPU 2 allocated peripherals will be clocked. When D3 is in Autonomous run mode, the fixed allocated D3 bus matrix peripherals and the D3 domain Autonomous mode allocated peripherals are clocked. Power management functions control the power supply for the different domains based on the domain operating mode. The system and domain operating mode depend on the CPU operating mode and the CPU subsystem boundaries. Thanks to voltage scaling, the various run modes offer flexibility between the required performance and consumption. In run mode range 0, enhanced performance with high power consumption, the system clock is limited to 480 MHz. In run mode range 1, high performance with high power consumption, the system clock is limited to 400 MHz. In run mode range 2, medium performance and power consumption, the system clock is limited to 300 MHz. In run mode range 3, low performance with low power consumption, the system clock is limited to 200 MHz. The internal and external oscillators as well as the PLL can be used in all modes, respecting the maximum frequencies. The run mode range is determined by the system clock frequency even when a CPU is in C stop mode. In stop mode range 3, the peripherals with wake up from stop mode capabilities, UART, SPI, I2C and LP TIM are operational. In stop mode ranges 4 and 5, the peripherals with wake up from stop mode capabilities are disabled. Each peripheral clock can be configured to be on or off in run and low power run modes. By default, all peripheral clocks are off except the flash interface clock. The SRAM clocks are enabled in run mode. When running from D1 SRAM, D2 SRAM or D3 SRAM, the flash memory can be put in power down mode thanks to software, and the flash clock can be switched off. The flash memory must not be accessed when it is switched off. Consequently, interrupts must be mapped in SRAM using the Cortex-M vector table offset register. The CPU entering low power mode is controlled by the Cortex-M WFI and WFE, and the deep sleep bit allows selection between C sleep and C stop mode. When the CPU enters C stop mode, the domain and system operating mode depend on the other CPU and the D3 autonomous modes. A CPU NVIC interrupt with sufficient priority will wake up the CPU after a WFI or return from ISR. A CPU event input or RX EV will wake up the CPU after a WFE. In addition, when the Cortex-M SVON PEND bit is clear, an NVIC interrupt with sufficient priority will wake up the CPU after a WFE. When the SVON PEND bit is set, any NVIC interrupt will wake up the CPU after a WFE. Power management functions control the power supply for the different domains based on the CPU operating mode and the domain power down deep sleep selection through the PWR register bits PDDS-DN. Each CPU has its own control bits for the three domains. A domain will only enter D stop mode when the domain CPU is in C stop mode and the other peripheral has no allocated peripherals or is also in C stop mode. The STM32H7 system or D3 domain operating mode is controlled from both CPUs and the D3 autonomous mode. The system will only enter stop or standby mode when both CPUs are in C stop mode and there is no active wake up source or if the D3 domain is forced in run mode. The system will only enter standby mode when the power down deep sleep selection in PWR register bits PDDS-DN allows all domains to enter standby mode. The D3 autonomous mode can set the system in run mode either by a CPU forcing the D3 domain in run mode via its run D3 register bit or by a peripheral wake up source request. This figure gives the complete overview of the power modes in relation to the CPU operating modes and the D3 autonomous mode. Sleep and low power sleep modes enable all peripherals to be used and feature the fastest wake up time. In these modes the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep and low power sleep modes. These modes are entered by executing the assembler instruction wait for interrupt or wait for event. When executed in low power run mode the device enters low power sleep mode. Depending on the sleep on exit bit configuration in the Cortex-M7 system control register the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupts a routine. This last configuration saves time and consumption by removing the need to pop and push the stack. STM32H7 devices feature three stop modes. Stop range three, range four and range five which are the lowest power modes with full retention and fast wake up time to run mode at XX megahertz. The contents of SRAMs and all peripherals registers are preserved in all stop modes. All high speed clocks are stopped. The 32.768 kilohertz external oscillator and 32 kilohertz internal oscillator can be enabled. Several peripherals can be active and wake up from stop mode. System clock on wake up can be the internal high speed and low power or CSI oscillators up to 64 megahertz with only a 12 microsecond from flash. Stop range four and range five consumption is lower than stop range three but support less active wake up peripherals. To be able to reinitialize the clock system by a so-called master CPU when exiting from stop modes the stop hold function holds the so-called slave CPU until the master CPU has reinitialized the system. To do this a slave CPU wake up from stop mode interrupt will hold the slave CPU and wake up the master CPU with a wake up hold interrupt. Once the master CPU has reinitialized the system it clears the slave CPU hold where afterwards the slave CPU will receive the initial wake up interrupt. When comparing stop modes stop range three consumption is higher than stop ranges four and five but the wake up time is shorter and the number of active peripherals is higher. Stop range three keeps the v-core domain at the same supply level as run range three allowing a very short wake up time lower than 12 microseconds when restarting from the RAM to the expense of a higher consumption than stop mode with ranges four and five. It is possible to wake up from stop range three with peripherals supporting wake up from stop mode. UART SPI I square C and LP TIM. The standby mode is the lowest power mode in which four kilobytes of backup RAM can be retained the automatic switch from VDD to VBAT is supported and the IOS level can be configured by independent pull-up and pull-down circuitry. By default the voltage regulators are in power down mode and the SRAMs and the peripheral registers are lost. The 128 byte backup registers are always retained thanks to software it is possible to retain four kilobytes of backup RAM. The ultra low power brownout reset is always on to ensure a safe reset regardless of the VDD slope. Each IO can be configured with or without a pull-up or pull-down which is applied and released thanks to the APC control bit. This allows control of the input state of external components even during standby mode. Six wake up pins are available to wake up the device from standby mode. The polarity of each of the six wake up pins is configurable. The wake up clock is HSI with a frequency of 64 megahertz. The backup domain allows us to keep the RTC functional and to preserve the backup registers in case the VDD supply is down. Thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low speed external oscillator at 32.768 kilohertz. Three tamper pins are functional in VBAT mode and will erase the 128 byte backup registers also included in the VBAT domain in case of intrusion detection. The backup domain also contains the RTC configuration register. In case VDD drops below a certain threshold, the backup domain power supply automatically switches to VBAT. When VDD is back to normal, the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the battery backup level. When VDD is present, the battery connected to VBAT can be charged from the VDD supply. A CPU will enter C stop mode when executing a WFI or WFE with a deep sleep bit set. The domain and system state will also depend on the other CPU's operating mode and wake up source status. Only when the other CPU has no allocated peripherals in the domain or the other CPU is also in C stop mode, the domain may enter D stop or D standby mode. When in addition none of the wake up sources is active, the system may enter stop or standby mode. When a CPU wakes up from its C stop mode, it has to know from which mode the domains and system have woken up. For this, the CPU has dedicated flag bits SBF-D1, SBF-D2, SBF and STO-PF. These bits inform the CPU about the state of the system and which parts may need to be re-initialized. The Cortex-M sleep-deep bit allows selection of the CPU to enter C sleep or C stop modes. When the CPU enters C stop mode, the PWR control bits PDDS-D1, PDDS-D2 and PDDS-D3 select which state the domains may enter in. The state of the domains also depend on the other CPU's subsystem configuration and operating mode and the wake up source status. From C sleep mode, the CPU will always wake up through an interrupt or event. In this case, the Cortex-M deep sleep bit is zero. From C stop mode, the CPU may wake up through an interrupt or via a reset depending on the domain state. If the domain was in D stop mode, the CPU woke up through an interrupt. In this case, the Cortex-M deep sleep bit is one. When in addition the stop F bit is zero, the system remained in run mode so there is no need to re-initialize the clock system. If the stop F bit is also set, it means the system woke up from stop mode and the clock system needs re-initialization. If the CPU has allocated peripherals in the other domain, check the other domain's SBF-DN flag to learn if the domain was in D standby mode. In this case, the peripheral in the other domain needs to be re-initialized. If the domain was in D standby mode, the CPU will wake up through a reset. If the SBF flag is also set, the system was in standby. In this case, a full system initialization is needed. When the SBF flag is zero and the CPU sub-domain SBF-DN flag is set, the system remained either in run or stop mode and only the CPU domain has exited from D standby. In this case, only the CPU and its domain need to be re-initialized. Afterwards, the system state must be checked to learn if the system remained in run mode or was in stop mode. When the CPU domain SBF-DN flag doesn't indicate D standby, the CPU woke up via a system POR reset. This table gives a complete overview of the CPU domain and system mode and the wake-up flag bits. It also shows how the CPU was awakened through an interrupt or an event or a CPU reset. Here is a summary of the PWR control-related interrupts. Two bits are available in the flash option bytes to prohibit entering a given low power mode. When cleared, these option bits trigger a reset when entering either standby or stop modes. This is a security feature used to reduce the impact of unintentional entry into these low power modes. If these low power modes are not used in user code, the option should be enabled. The debug control register is used to enable debugging in standby modes. When the related bit is set, the regulator is kept on and the domains are supplied in standby modes. This maintains the connection with the debugger during the low power modes and continues debugging after wake-up. Remember not to clear these bits when the MCU is not under debug because the consumption is higher in all low power modes when these bits are set due to the fact they force the regulators to remain enabled. In addition to this training, you can refer to the reset and clock control and interrupts trainings as well as those for all the peripherals with wake-up from stop and standby capability.