 So, now, how do we define these low and high margins? Well, we will go back to that transfer characteristic and in fact, compute the noise margin. So, let us look at this transfer margin, this margin. We draw tangents to this curve and pick those tangents which have a slope of minus 1. So, wherever the tangent is 45 degrees with respect to 45 degrees in this negative direction that means, the slope is equal to minus 1 and there are two such points on this curve where the slope is this much as you can see. Now, everything to the left of this is considered 0, everything to the right of this is considered high or 1. So, these are our definitions of low and high. If I read the coordinates of this point on the x axis, then it gives me v input low and v input high. If I read the coordinates of the same thing on the y axis, then it gives me the v output high and low and we have to based on the consideration that we have talked of, we have to make sure that the v output high is sufficiently higher than v input high. So, that there is no confusion even in the presence of noise. Similarly, v output low is sufficiently lower than v input low. So, that this difference between this value and this value is sufficient. So, that even in the presence of noise, the output low is never considered to be high. Similarly, the output high is so high that even though the noise is pulling down pulling it down a little bit, it is still considered high at the input of the next stage. So, that is the system which has non-zero noise margin and the amount by which this is true is called the noise margin of that technology. Now, actual geometries of these transistors are actually determined by using dynamic considerations and detailed derivation of the charge and discharge time of the capacitors are provided in these nodes and you can look that up later. There is not that much to explain and I would much rather discuss now in the class on how to design circuits which are not just an inverter. We have been able to design an inverter, calculate it is the value of W by L from dynamic consideration noise margin etcetera, etcetera. The point is that inverter is not very interesting, we need to have all kinds of logic defined and how do we design other kinds of logic using this. So, let us look at that and let us develop it on the white board here. Now, let us first look at a NAND gate which is one of the more common inputs. By the way a single stage of MOS logic indeed most of the logic, a single state logic is always inverting. So, let us look at NAND, let us write down the truth table of a NAND gate. Suppose there are two inputs A and B, they can acquire these four combinations of inputs and the NAND of A and B means that the output is true only when both are one in all other cases it is 0 and NAND which is just the inverse of that is then 1 in all these cases and is 0 when both inputs are one. So, we want to now implement not an inverter but a circuit using NMOS and P bus transistors such that when both inputs are one the output is 0 in all other cases the output should be 1 and let us look at the following. When is the output of the NAND 1? The output of the NAND is 1 when either A is 0 or B is 0 or both are 0. What does that mean? That means we want to connect the output to VDD if either A is 0 or B is 0 or both are 0 and this can be done by putting P channel transistors in parallel. If A is 0 then this has sufficient negative bias on it gate to turn on and this will connect the output to VDD. If B is 0 then this transistor will turn on and connect the output to VDD. If both are 0 then of course both will be on and it will be a parallel connection through to VDD. As a result the output will is guaranteed to be connected to VDD when either A or B or both are 0. We must also ensure that under the same condition when it is connected to VDD it is not connected to ground and to ensure that we put the N channel transistors in series. If A is 0 then this transistor is off, if B is 0 then this transistor is off and if both are 0 both of them are off. As a result in all these cases the output is connected to VDD and not connected to ground and therefore the output is 1. This takes care of these three cases that means if A is 0 or B is 0 or both are 0 then the output is now connected to VDD through the P channel transistors and isolated from the ground because either one or the other or both the N channel transistors are off. However what happens if both are 1. Now in this case A is 1 therefore this transistor is on, B is 1 therefore this transistor is on, this transistor A being 1 is off, this transistor B being 1 is off as a result both these are off and both of these are on and in that case there is a connection from output to ground and there is no connection from output to VDD. As a result the output is 0. So this circuit indeed implements the NAND function. So now we can take the inverter and replace one transistor by two putting N channel transistors in series and the P channel transistors in parallel and that will give us NAND gate. What about a NOR gate? We do exactly the opposite and we work out the logic as we had done before. Let us write down the truth table. The four combinations of A and B remain the same. The OR of A and B says that if either A or B or both are 1 then the output must be 1. So these three cases when either one of them or both of them are 1 the output must be 1. If both are 0 then the output must be 0. The corresponding negative logic NOR is the opposite of this that means for both inputs being 0 it is 1 and for either of them being 1 the output is 0. This time we put the P channel transistors in series and the N channel transistors in parallel. Notice that a 1 turns the N channel transistor on and turns the P channel transistor off. A 0 turns the P channel transistor on and turns the N channel transistor off. Let us now look at all these four conditions. There are only four conditions to look at. If both are 0 then both N channel transistors are off therefore the output has no connection to ground as we want it. Similarly, both P channel transistors are on connecting this output the output terminal to VDD through both these transistors which are on. On the other hand if either or both transistors are 1 then at least one of these two or may be both are on. As a result the output is then connected to ground. Since at least one of them perhaps both of them are off under these conditions therefore there is no connection from VDD to ground. So we have met the requirement. There is no connection to VDD and there is a connection to ground and therefore in all these three cases the output is in fact 0 and we end up implementing this logic and therefore this is the implementation of norm. In fact we can generalize this logic. The generalization of this logic says the following. You have this rule that you write down a logic expression which must be inverting that means it must have a bar on top. For inverting logic you can implement a single gate implementation. If you do not want inverting then of course you can put an inverter after that. So for example if you wanted or logic then you will make a nor logic and put an inverter after that. If you wanted and logic then you would take a NAND gate and put an inverter after that. So you take a logic expression it must have a bar on top and then you implement it by the same rule that we have followed in the simple logic. Namely for every plus in the expression every or in the expression put n channel transistors in parallel and p channel transistors in series. For every dot that means and function every dot in the expression. So our requirement was that the logic expression must have a bar on top and now we look at the expression itself. For every in the expression put the n channel transistors in parallel and put the p channel transistors in series. For every dot or end function every dot in the expression put n in series and put p in parallel. So this rule is actually quite simple. Just take an expression if it did not have a bar on top then force a bar on top and put an inverter after that. Therefore the implementation is always of a logic expression which has a bar on top. For every plus in the expression put n in parallel p in series for every dot in the expression put n in series p in parallel. Let us verify this rule first for the simple logic that we had already developed. What was the logic? We had NAND which is a dot b bar it does have a bar on top and you have a dot. What did we say for a dot? That put n in series p in parallel. So therefore the corresponding circuit is n in series and p in parallel and this is indeed the NAND gate that we had discussed earlier. What about NOR? NOR is a plus b whole bar it does have a bar on top it meets our requirement and therefore what we do? It has a plus for a plus what did we say n in parallel and p in series. So now n channel transistors are put in parallel and p should be put in series and this indeed is the circuit that we had discussed for NOR. In this case should either of a or b be 1 or both be 1 then the output gets this is the output. The output gets connected to ground only when both are 0 then both p channel transistors are on and both n channel transistors are off and therefore the output is connected through this path to VDD as a result the output is 1. So this logic works fine for the two simple cases that we had seen. Let us look at it in a slightly more complicated logic and for that we will go to the document. Let us consider this particular case where we are implementing a very complicated expression look at this it is a dot b plus c dot in bracket d plus e and whole bar. Notice that we need a bar. Now if you recall the rule what did we say for every dot n in series p in parallel for every plus n in parallel and p in series. So let us just scan this expression what do we have under the bar? Initially we have a dot b therefore we tell this expression we take two n channel transistors a and b and put them in series n channel in series for dot. Similarly we take two p channel transistors a and b and put them in parallel. So the a and b inputs the n channel transistors are in series and the p channel transistors are in parallel. What follows in the expression after a dot b a plus and what did we say for plus n in parallel p in series. Therefore in parallel for this n channel combination we must put some circuit and in series with this p channel transistors combination we must put some circuit and what is that circuit? That circuit is c dot something because it is c dot therefore c must be in series which is what is happening here c is in series and in case of p it is in parallel. So this c is in parallel with this rest of the circuit and c dot what? c dot d plus e. Now for a plus n channel transistors are in parallel and p is in series therefore d and e are in parallel and here d and e are in series. So let us scan through this instructions scan through this logic a dot b means let us first worry only about n channel transistors. a dot b means a series b a dot b plus means a series b in parallel with a dot b plus what? c dot d plus e that means c in series with d and e in parallel. So this makes the n channel proper according to this in according to this expression. Similarly let us read it for p channel a dot b means a parallel b a dot b plus means this parallel combination in series with in series with what? a dot b plus c dot d plus e that means c in parallel with a series combination of d and e. So it just follows exactly the rule that we had simply seen in case of n and a very complicated expression like this can be implemented in a single gate here. So this is how we can implement the most logic. We are nearly through with our time for this lecture and what we will do is to take a pause here for this and just use the two three minutes that we have to describe how it is done in TTL logic because in many of the lab you might be using TTL logic. TTL logic is quite similar and it actually uses bipolar transistors. TTL stands for transistor transistor logic and it is implemented with a special kind of bipolar transistor which is multiple emitter that means this is an NPN transistor in which you have essentially an n-tub inside which there is a p-type tub and now you have multiple n plus tubs to form the multiple emitters. This is the multi emitter transistor. The substrate is p in that you make an n-type tub that becomes the collector which is common. Inside the n-type tub you put a p-type tub that becomes the base and that is also common and now you put individual n plus pockets in that and each one of them is one of these emitter. This base is connected high and this output then goes to an NPN transistor which acts as a phase splitter and each one of them drives an NPN transistor and this output is brought down by a diode and this is the output. This is a basic TTL gate. Let us see how it works. If either of A or B or both of them are low then this emitter is grounded. The base is taken to VDD through this resistor therefore, a large amount of base current flows and therefore, this transistor turns on. When it turns on it grounds this node. So, this node becomes 0. This turns this transistor off. If this transistor is off, this base is connected to VDD and this base is connected to ground. Therefore, this transistor is on and this transistor is off and the output is then 1. So, again write down the same logic table and in these three cases at least one of the emitters is connected to ground which leads to forward biasing of the emitter base junction which causes base current to flow and therefore, a multiplied amount of collector current to flow. This turns this transistor on connected since the emitter is grounded for one of them. This grounds this terminal. If this terminal is then grounded then this transistor is off and because this transistor is off, this base is connected to VDD and this base is connected to ground. As a result, this being connected to VDD this transistor turns on, this transistor turns off and that makes the output high. So, therefore, for this for either input being 0 or both inputs being 0, our output is high. Only when both inputs are 1, then this emitter base junction is as if not there because there is no current flow here. In fact, this transistor is then said to be in the reverse active mode because now emitter is high, collector is low because of this path. So, therefore, after all it is an NPN structure. Therefore, this thing which was meant to be the collector starts acting as the emitter. These two which were supposed to be the emitters because they are taken to VDD start acting like a collector and this is like a transistor with a very low beta. Therefore, this transistor turns off. If this transistor is. So, if both of these essentially the transistor action does not matter and due to this diode which is forward bias, notice this is N, this is P, this is N. Since the emitter base junction is turned off through this junction, this junction is now forward bias. This is P type, this is P and connected to VDD. This is N connected towards ground. As a result, base current flows through this path. Because base current is flowing, this transistor is now on large amount of current flows that pulls this voltage low because of the R I drop here and that pulls this output to 1. If that is 0 and this is 1, then this transistor is off and now this transistor is on making the output high, making the output low. Sorry, this is on it pulls it to ground, this is off. So, that makes the output 0 and you can confirm that this is indeed the implementation of NAND. If you had only one inverter, this would be an inverter. If you have multiple emitters, it could be a 2 input, 3 input, 4 input NAND, but the structure remains the same. This output by the way is called a totem pole output and this TTL family is somewhat older type of logic. But it was used very widely and indeed was the model for the subsequent CMOS kind of logic that we just now discussed. The logic level for this on the input and the output are like this. Any voltage which is less than 2.4 volts is considered low. Any voltage, the corresponding low output is in fact 2.0. If the output is supposed to be 2.0, even if there is 0.4 volts of noise, the output will remain below 2.4 and therefore, it will be considered as low at the input. Similarly, the output input is considered high if it is above, sorry this is the definition of the definition that I gave you was for high. The low is 0.8 and 0.4. If the input is below 0.8 volts, it is considered low. The output is guaranteed to be below 0.4 volts. Therefore, even if there is 0.4 volts of noise, an output low will not rise above 0.8 volts and will still be considered low. Therefore, it has 0.4 volts of noise margin. The 2.4 and 2.0 that I was talking about is the high level. So, V input high is 2.0 volts and the V output high is 2.0 is guaranteed to be higher than 2.4 volts. So, if this is 2.4 volts, even in the presence of negative noise of up to 0.4 volts, this voltage will never drop below 2.0 volts and as a result will be considered high by the next stage. Therefore, TTL has a noise margin of 0.4 volts and by the way there are various kinds of TTL families, those using short key and without short key and so on. These values might change a little bit with that, but for the traditional TTL, these are the values. The output when it is supposed to be 0.4 is guaranteed to be, output when it is supposed to be low is guaranteed to be below 0.4 volts. On the other hand, a voltage as high as 0.8 volts would still be considered a low. Similarly, when it is supposed to be high, then at least 2.4 volts will appear at the output and a voltage as low as 2.0 volts will still be considered high and this constitutes that 0.4 volts of noise margin. So, these are the TTL versions of the same gates. We have seen a more detailed discussion of the MOS logic. Eventually, for logic design beyond this, we will not worry what is the implementation of the actual gate and see how logic can be implemented in our later lectures. In I D Warangal, could you ask your question please? Sir, how to reduce the threshold voltage in MOS? You have various choices in this. Recall that the threshold voltage is the voltage at which inversion will occur. So, you have the control, you can reduce the threshold voltage by using a thinner oxide, which will couple the gate voltage to the semiconductor better. You could also use slightly lower doping. You could use a different metal with a different work function and finally, you could have a small amount of implant right at the surface, which helps the turn on. So, there are multiple ways of generating, of reducing the output voltage. The question was how to reduce the voltage? So, let us take the n channel example that we had talked about. Now, if you want to reduce the threshold voltage, I can use a thinner oxide. Remember, I want to put a lot of negative charge here for a given voltage. So, therefore, the charge here is C ox times V and I can increase C ox by making this thinner. So, that is one way of using a thinner oxide. The other way is to use a metal with a work function difference, which makes it more positive, appear more positive than what it actually is. I could use lower doping here, so that it is easier to invert. I have to convert P to n type and it is easier to invert if it is not very strongly P type. So, I could use lower doping here and finally, I could already put a certain amount of n type impurity here, which helps in inversion. So, any or all of these options can be used for reducing the turn on voltage of an n channel transistor. There are corresponding versions for the P channel transistor. Again, use lower doping. Again, use thin oxide. Use a metal, which takes it to the negative side now and finally, put some implant here with some boron in it now for the P channel transistor. Over. Next question, NID Sura, can you go ahead with your question please. Hello, good morning sir. My question is related to one of the quiz question, where it was said that Fermi potential is equal to kT by Q L and P by Ni. Ni was given 1.5 into 10 to the power 10 per centimeter Q and it was said that phosphorus has been added with concentration 10 to the power 16. So, when we calculated I got it around with minus 0.3, but the answer means after submitting the answer was said to be plus 0.3. It was not that phosphorus is added, but a P type impurity is added. Just look it is possible that there was an error in the question. I will check back, but what was expected was that you are given a P type impurity using N P equal to Ni squared. You find out the N type impurity, find out the whole concentration and then calculate the Fermi potential. If you add P type, the Fermi potential will be negative and the energy will be above EFI. So, if you got that, that is correct. If necessary, we will make a correction in the answer. Sir, the question means I think it was written phosphorus in that. So, it is ok. We will make a correction in the answer. If it is phosphorus, it should be N type. The Fermi potential should be negative and the Fermi energy should be positive. Another question related to the CE amplifier, the question in the quiz, the why CE amplifier is generally used. So, there were four options out of this, two options low voltage gain is discarded, but two options were having high voltage gain, medium output resistance and one of them was having low input resistance and another one high input resistance. So, we most of us have selected that high voltage gain, low input resistance and medium resistance, but it was also shown to be wrong. The answer they have given right is high voltage gain, high input resistance and medium resistance for CE configuration. Yeah, I will check the answers once again as we studied for a CE amplifier. The two, there should not be any ambiguity in the options there. Let me check it again. For a CE amplifier, the input resistance is not high. Typically, say medium is the word used. I will check it again and if there is an error, we will correct it over to you. Thank you sir, it is over. Okay, see Jai Chandra Rajendra College, Karnataka, you can ask your question now. Good afternoon sir. Suppose a transistor amplifier circuit is given, how to determine in which type of feedback it is, whether it is a current feedback or an voltage feedback. Can you explain with a simple example sir? There is a lecture on feedback, which is the next lecture. So, let me postpone this question till then. Over to you. Hello sir. In case of diodes, we are going to assume 0.3 volts cut-in voltage for germanium and 0.7 volt cut-in voltage for silicon. Why it is so, sir? And what is the effect of reverse saturation current on the cut-in voltage of the diode? The diode equation says that the current through the diode is equal to the saturation, the saturation, reverse saturation current times exponential of applied voltage in units of KT by Q minus 1. From this, we can find out that I by I s minus 1, I by I s and plus 1. Anyway, this 1 is negligible. That is e to the power Q V a by KT and therefore, normally the current through a forward bias diode is so much larger than the leakage current that this factor would be of the order of a million or even more. Therefore, we can neglect this 1. If we do that, then V a is given by KT by Q ln I by I s. Now, there are two things which are apparent from this. First of all, the voltage across the forward bias diode. We are assuming that the diode is forward bias. Otherwise, we do not talk of the cut-in voltage. The voltage across the forward bias diode then is a logarithmic function of the current. First thing, second you can see that it is I s which equally determines the cut-in voltage. Now, typical values of I s for silicon might be of the order of 10 minus 14 ampere. If you take a current of the order of a milliamp and this of the order of 10 minus 14, this is of the order of a milliamp, then this is of the order of 10 to the power 11. Then, KT by Q is about 26 millivolts times log of this quantity which is of the order of 10 to the power 11. So, ln, so it will be 11 divided by 2.303 or whatever. Log of 10 to the power 11 will be 11. It is this quantity which gives you the built-in voltage. Now, the main point is that if I double the amount of current, how much will this change? Suppose it is some voltage V. If I double the amount of voltage, how much will it change? It will change by a factor which is KT by Q ln 2 and that is just 26 millivolts multiplied by some small number ln of 2 is less than e. So, it will be of the order of 1. So, it is of the order of millivolts. Therefore, even if you double or make the current 10 times, the amount of change in the voltage across this is not too much and that gives rise to the concept of the cut-in voltage. That means, for a large variety of useful currents, the voltage across the diode is roughly the same. It is not exactly the same and it is a very great error to suggest that there is some holy figure like 0.55 or 0.6 volts which is associated with the cut-in voltage. In fact, the cut-in voltage is associated with I s and larger the leakage current, lower is the cut-in voltage and because germanium is a direct band semiconductor, the value of I s is orders of magnitude higher and for currents of the order of milliamp, this expression then comes out of the order of 0.25, 0.28 or 0.3 volts. Therefore, the cut-in voltage is indirectly controlled by I s and it remains more or less constant for a very large variety of actual values of forward current. Therefore, we say that there is a cut-in voltage. In fact, the cut-in voltage is not constant. If you look at the forward characteristics of a diode, what we are saying is that when it is truly in forward bias here, then you may go over a large variety, large change in current but this voltage will hardly change. That is the point we are making. This may be orders of magnitude whereas, this will be of the order of milli volts and this might be say 0.6 or 0.65 volts for silicon and then you may change the current from 1 milliamp to 100 milliamp and still this will remain in the same range. That is why we say that there is a cut-in voltage of about 0.65 volts for silicon. I hope that answers your question. Sir, what is the advantage of using totem pole in teal logic families? The totem pole, the upper transistor is used for pulling the voltage up and the lower transistor is used for pulling the voltage down. The only thing which is mysterious is that diode and the answer to that is that in the TTL family, if you notice that the output high is actually not very high. It is only 2.8 volts whereas, the output low must be brought down to a very low value. Therefore, you use a diode to drop about 0.6 volts from the natural output of that. This results in lower power consumption. So, the totem pole output which is like this with a phase splitter giving either 1 or 0 here or the other way round. The point is that the output high need not be very high but the low is required to be as low as 0.4 volts. In order to do that, if you had taken the voltage here and not kept this diode, then this if this diode was not there, then the output low will not be low enough and the output high will be unnecessarily high because the levels guaranteed for TTL are such that output high is not all that high. It is nowhere close to VDD. It is only 2.4 volts. Therefore, you need a voltage shifter which will bring it down to this level and that voltage shifting is done by this diode and that forms the totem pole also. Over. Good afternoon sir. My question is related to clampers. What do you mean by peak clamper? How exactly we can differentiate general clampers from peak clamper? Clamping is a phenomenon. What you use it for makes it what kind of clamper it is. So, if you use a clamper to reduce the peak value of some input, then it is a peak clamper. I will give you an example. Consider a diode like this and you have a voltage actually should put a resistor there, but let us say it is some voltage. Now, if this voltage exceeds this voltage, then this diode will become forward bias and that will cause drops in this formation and the output will not be able to go. Actually, this is not the configuration. I will just redraw the configuration. Consider this output. This is V in and this is V out. As long as V in is less than V plus a diode drop, this is like an open circuit and V in is reproduced at V output. Should V in exceed V plus a diode drop, then this diode becomes forward bias and therefore, this output voltage becomes constant at V plus the diode drop. Now, this is the phenomenon of clamping. This can be used for lots of purposes. One particular purpose is that if your input is of this kind and this voltage could be dangerous to your circuit, then you can use a clamper and that clamper will make sure that this output looks like this, because this output will be limited to this voltage plus a diode drop. That means, everywhere else the voltage is the same, but the peak of this waveform has been cut off. So, this particular application is called a peak clamper. If you apply the same idea to some other circuit, then it will not be called a peak clamper, because you are not only removing that you could apply this for example, to maximize the DC voltage of a supply. So, if that is the case, indeed this configuration is that of a battery charger. So, if you put a battery charger here and this is the battery being charged, in that case this output voltage cannot exceed the battery voltage plus this diode. So, it will charge this battery, but this voltage will not exceed a particular value. Of course, you will have a path around it when you are using the battery. So, in this case, you are not clamping a peak. There is no peak. You are just adjusting the DC value to a particularly preset value. So, then that is not a peak clamper. So, what kind of clamper is it? That depends on the circuit application. The phenomenon is because of this diode limiting the maximum voltage to some value. The phenomenon of clamping is not related to where it is used. Over to you. Gachi Puram, could you please ask your question. Sir, actually in quantitative analysis of mass modeling, we are learning about static characteristics, dynamic characteristics. You also explain in that. There we are coming across one technical word, fused characteristics. Actually, if you are using an array of mass, we will be come across this word fused. The fused characteristic has to do with a programmable logic. So, essentially if you have a transistor and you can in arrays, if you have a transistor which implements programmable logic, then you use it like a fuse in the sense that it is permanently connected or permanently not connected and you program it by actually, I will just draw the diagram for you. If you have a transistor like this and now if briefly I put a high, very high gate voltage here, then it injects some charges into this oxide and this oxide becomes charged. Now, it is not necessary to apply a gate voltage to turn it on. It already has enough positive charge which is trapped in this oxide to turn this transistor on and therefore, it clamps this output voltage down to 0. So, then it acts as the fused logic and that it forces this output to be 0 and now this can then be connected in a logic passion to other transistors to program the logic to perform in some way. So, that is called fused logic. Now, we will come to the programming logic a little later and then the details of this can be taken up. Two questions sir. In signal conditioning, if you are applying any signal, maybe a detail or analog, while you are making that signal is a negative resistant or positive resistant. We are facing that problem down nice, ground nice or phase nice. That how will you quantitatively determine? Over. I am afraid your question is not very clear to me, but in any case it is not related to the things that we have done in the lectures up to now. So, I think in the interest of time we would be able to take these questions which are related to the lectures that we have taken and other questions are welcome, but let us take them offline through Boodle because then we will able to you will be able to explain the context and we will be able to understand your questions better. M K S S Pune, could you please ask your question now? My question is why we are preparing a capacitive load as compared to the resistive load for the CMOS logic especially in case of inverter. In digital design a gate drives other gates of the same kind. So, consider let us say that you have an inverter and it is going to some some logic like this. So, what is connected to the output of this? If you recall if I expand it in terms of transistors, this is our inverter and this is driving a NAND gate which is series connected N channel transistor and parallel connected P channel transistor. So, what is the output load of this? The output load is in fact this capacitor represented by this transistor gate. So, therefore, the common usage of in logic is that no current is provided by the output other than charging of this capacitor. No steady state current is drawn from the output. Therefore, in case of MOS logic we consider the load to be capacitive. In case of P T L base current for the transistor has to be provided and therefore, we cannot consider the output to be purely capacitive. However, in case of MOS only the gates of the subsequent logic are to be charged up and therefore, we consider the load to be capacitive over. So, my question is unlike Avalash the diode in case of the Zener diode with increase in temperature the breakdown voltage increases. So, why it is so over? Yeah, the temperature coefficient actually is determined by the avlanching process and the avlanching depends on how much field develops. At high voltage because there is conduction the field does not develop very easily. So, as a result the voltage at which the avlanched process which represents a Zener action occurs at a different field because part of the field is reduced due to the flow of current which is temperature dependent. So, that gives rise to the temperature dependence of the Zener voltage. It is relatively small, but it is in that direction and can then be compensated by a forward bias diode whose forward drop actually reduces as the temperature is increased. That is related by the way to the previous answer that had given because the forward drop across a diode is dependent on the leakage current which increases with temperature. As a result the forward drop across a diode will reduce as the temperature increases, but in this case the field required to breakdown a diode increases because that much avlanching field must be there even in the presence of additional current. So, larger field is required to breakdown the voltage. So, in case of Zener you have a slight positive tempo, in case of diode you have a slightly negative tempo. Questions from VNIT in Agpur please. Good afternoon sir. This is regarding MOSFET logic. I wish to know whether we need enhancement, a combination of enhancement and depletion mode transistors or only enhancement mode transistor would do for the proper implementation of the gate. The second question is regarding the TTL NAND circuit. Here in the first input the collector of first transistor is not has not given any supply voltage. So, how does it work as a transistor over you sir. I will take the two questions one by one. First of all in case of MOS the depletion mode transistor is not required for CMOS because if you recall a depletion mode transistor is like a resistor and we needed only switches not resistors in this case. So, the modern digital logic does not require depletion mode only enhancement mode transistors are good enough as explained in the functioning of the transistor. There was an older variety of logic using MOS transistors called depletion enhancement mode technology and there the equivalent switch was like this. It used a switch and a resistor. Now, if the switch was open the resistor brought up the output voltage to high. If the switch was closed then the switch shorted that to ground. The disadvantage of this technology was that whenever the output was reduced to 0 a constant amount of current will flow from VDD to ground which resulted in static power consumption. This is avoided in CMOS because both switches are never simultaneously on. Therefore, most modern almost all modern logic design uses CMOS which uses only enhancement mode transistor. This resistor was effectively the depletion mode transistor. So, you had a depletion mode transistor which even at 0 volts would draw some current and that was essentially this. So, in short in modern CMOS technology the depletion mode transistor is not required. On the other hand you require both polarities the NMOS and PMOS and they are both enhancement type. In answer to your second question if you look at this transistor with multiple emits this was our TTL gate I am not drawing the output stage. So, the interesting point is that what voltage is this node. Obviously, if this is pulling some current I and this is R then this point is at R times I and therefore, this voltage is R times I plus a diode voltage. So, the circuit configuration says that this collector voltage if this guy is pulling current is high. Therefore, you do not need to separately connected to VDD. Now, if I pull it low then the effective configuration is that I have shorted it to ground and now this transistor is then connected between this point and ground and because it draws a lot of current it pulls this voltage down and turns this transistor off. Now, this voltage is quite low no current is flowing through this, but because this transistor is on a lot of base current is flowing through this it keeps this voltage low yet it is positive compared to this. Only in the case that all inputs are high in that case this voltage is at some low voltage and all the emitters are high this transistor is acting in the reverse active mode and then the current flows like this and through this. So, it is not acting like a regular transistor at all it is acting more like a diode and this is connected through another diode and resistor to ground as it should be. So, in short if any of the inputs is 0 it acts as a transistor this is an emitter the collector is at a positive voltage and it acts as a switch which acts to pull essentially it shunts all the base current of this it does not allow any base current to flow in this. Whatever base current would have gone through this is is eaten up by this transistor rather than becoming the base current of this transistor as a result this guy turns off. In the other mode when all inputs are high this act does not act like a collector at all and therefore it does not require a positive voltage. In fact, the current flows in this direction in the reverse direction from the base to the collector and through that becomes the base current of the next transistor over. Related to saturation current please may I know the factors affecting this saturation current over to you sir. The factors are exactly like the J effect essentially what happens is consider a case let us take a easy case where the turn on voltage is 1 volt. Now, consider the source to be at 0 volts let us say this is at 2 volts. So, the transistor is on the voltage is greater than 1 volt. Now, if this is at 1 volt then at this point there is sufficient vertical voltage to turn this transistor on, but at this point it is marginal only 1 volt is available at this end. Should the drain voltage increase any further there will be no channel here and this is exactly equivalent to the pinch off case in case of the J effect. Therefore, the saturation current is the current that would have occurred at V d equal to V g minus V t which in our simple model is mu C ox W by L V g minus V t whole squared divided by 2. So, the saturation current is affected by all these parameters it is affected by mobility by C ox by the W by L ratio and how much above V t is the value of the gate voltage at that time. And of course, for saturation it is required that the drain voltage be higher than V g minus V t. So, that this voltage is less than V t over we will take the last question from Perrier Weller. At Perrier Weller could you please go ahead and ask your question please. Hello good afternoon sir. So, my I have two questions sir my first question is how to find the output resistance of an amplifier practically. My second question is how to give current source practically, how to give a current source practically, what what to use sir. The output resistance is actually a measure of how much current can the can the source can the amplifier provide for a particular voltage. So, essentially we model the amplifier as a Thevenin equivalent with this R. So, the output resistance can be measured by measuring the short circuit current of this. So, suppose you have a common emitter amplifier in practical terms if you want to measure the output current you have to measure the AC current through this path when this is nearly a short circuit. And the corresponding voltage by current the ratio of this voltage by current it is a Thevenin equivalent. So, the ratio of the open circuit voltage and the short circuit current will then give you the output impedance of this. Practical current sources in fact make use of saturation of current that we just now talked about. So, for example, you had seen that this kind of characteristic is quite common whether it is a JFET a MOSFET or a bipolar transistor. So, in this regime this device whether it is a bipolar transistor JFET or MOSFET will act as a current source. So, it could be as simple as this. This terminal will now act as a current source whatever current is flowing because of this resistor through this path. Because of the current mirror action because the VGS is the same for the two the current will come here and this current over this voltage range will remain constant. Therefore, this point will appear as if you have a current source here. So, in short you make use of the saturation characteristic of a device to make a practical current source. It will not act as a current source for all possible voltages. It will act as a current source over this voltage and will not act as a current source over this range. So, you have to make sure that the output voltage is such that at least this much drop is there across the tunnel. If you can assure that you can make it correct.