 So, welcome to this lecture on VHDL and the course digital system design with PLDs and FPGA. We are looking at the VHDL modeling or coding of the sequential element, sequential circuit like flip flops, registers and sequential circuit or data path using the sequential elements. So let us look through the starting with flip flops so that things are clear. We will go little back and let us look at the slides. So I said that the flip flop is model bytes behaviour not by what it is composed of. So the behaviour is upon the clock edge d goes to q that is a behaviour and we have seen if you write a code like this a process clock and begin if clock is 1 q gets t end if end process. Then as far as simulator is concerned there is an event on the clock say a rising edge then it comes from top goes from top to bottom. Then it checks if clock is 1 then q is assigned d that means this event and clock is equal to 1 makes it a rising edge and q gets d we say end if that is a memory so it memorises and it works properly. But the problem with synthesis tool is that it is not going to worry about that kind of real time behaviour and all that it looks at the code. The code say if clock is 1 q gets d as long as clock is 1 q gets d and if that means if when clock goes 0 it is a memory. So that represent a transparent latch than a flip flop as far as the synthesis tool is concerned so whenever there is clock is high the d comes to q whenever it goes low the value at that point is kind of is latched or memorized similarly here can see when the clock is 1 q reflects a change in d when it goes low that is latched till it is enabled. So the question is that as far as synthesis tool is concerned we have to bring that event part here in the code because that is what is missing from the code. So we have added an attribute called clock tick event and clock is equal to 1 then that represent a rising edge we are hoping ok and q gets d end if as far as simulator is concerned there is a kind of redundancy duplication duplicate statement that means this starts computing whenever there is an event again we say an event but it does not matter. But the question here is that event does not mean 0 to 1 and 1 to 0 like it can be you at the beginning of simulation then it can go to 1. So as I said this can create some issues like at the beginning of simulation and all that and that may not reflect in the real life circuit. So you could simulate something and you would think that a different behaviour and you will get something different in the real life circuit. So that can be avoided if there is a if the correct rising edge is caught. So there are two functions in IEEE standard logic 1164 package which is called rising edge clock and falling edge clock which will correctly you know return true if there is a 0 to 1 or 1 to 0 transition only thing is that it calls another additional function it might take a fraction of time extra which is not very significant. You can have an equivalent concurrent statement for this the flip-flop say you say q gets d when clock tick event and clock is equal to 1 and you do not mention else. So that is memory otherwise q is q itself you know that is the meaning of it and when we look at the d latch as far as synthesis tool is concerned if this code is enough if clock is equal to 1 q gets d and if that q is a latch for the synthesis tool. But for the simulator there is an issue the moment you write clock that catches an event on the clock and that becomes a flip-flop okay not a latch. So it means that if the d is changing when the clock is 1 this process is not computed as far as simulation, simulator tool is concerned, simulator is concerned. So the solution is to put d in the sensitivity list so that when the clock is 1 and there is an event on d that will trigger a computation and it comes here and we say clock is 1 q gets d and that is reflected here. So for the d latch the code for simulator and synthesis tool is process clock, d begin if clock is equal to 1 then q gets d end of end process. So this works for both simulator and synthesis tool, synthesis tool looks at this code and synthesise it and simulator you know looks at the sensitivity list and correctly simulate the behaviour of the d latch and you can have the equivalent concurrent statement here also can say q gets d when clock is equal to 1 and else you say nothing okay and we also said that it is possible to use a syntax called wait on whatever that was on in the sensitivity list. In that case you do not write the sensitivity list at the end this cannot be put at the beginning because that has to be computed then you wait on clock and d and even in process normal process when you write some process at beginning it is computed once okay. So that is what is this behaviour you have wait on clock, d in that case you should not write it here either of this you can use it. And we said that there are different wait syntax, wait on, wait under and wait for is definitely used for simulation and you have a mix of that and depending on the situation these both are for simulation anyway you cannot use it for synthesis because a time is specified but wait until count is equal to 10 you can think how a sensible circuit can be designed you know for synthesis we have discussed about the asynchronous reset, a flip flop with an asynchronous reset, resets whenever this is active or this is asserted irrespective of the clock that means it is that is why it is called asynchronous if there is anything is synchronous then upon the clock that happens but here asynchronous mean that anytime you make it 1 in this case then the Q gets 0 whatever may be the clock whether it is high, low or transiting though there is a I mentioned there is some kind of relation you have to maintain for the proper operation of the flip flop as far as reset is concerned not good time to discuss that here may be towards the end of the course we will discuss that. But for the time being we assume that it is anytime it can come and reset and it has priority okay so we will see how that can be coded first of all that means that the process has to be sensitive to that one so we write the reset here in the sensitivity list then it has priority so we will write before if clock event is and clock is equal to 1 the reset the code is shown if the clock and reset is in the sensitivity list and we write the code if reset is 1 then Q gets 0 else if clock tick event clock is equal to 1 then Q gets D and if okay we do not specify the else and here also mind you else if not the else okay we cannot be else because else only will catch the reset equal to 0 so else if clock event clock is equal to 1 then end if that represent the memory. So this gives you an asynchronous reset and if it is a register of you know multiple input and multiple output then you can say other 0 and this become a vector and this become a vector you get the same asynchronous reset for all the flip flop element in the register okay. Now you can have a concurrent statement which say that Q gets 0 when reset is 1 else D else D when clock event and clock is equal to 1 then you do not say else okay. So here Q gets 0 when reset is 1 else D when clock tick event and clock is equal to 1 and we do not say else then you get the same thing. We have looked at this code the last class here the difference is that instead of Q gets D we say Q gets A, X or B okay and as I said we know that any flip flop upon the clock D is transferred to Q. So in this case if you say upon the clock if Q is getting a combinational circuit output would mean that you have to connect that exclusive or gate at the input of D because the only input which is transferred to the Q is D so naturally you have to connect your X or A gate here then upon the clock A, X or B will come to the Q. So that is what the synthesis tool is going to do the exclusive or gate with A and B as input is connected to the D and upon the clock the Q gets B okay. So it means that you can write a single process which can combine a flip flop and the combinational circuit preceding it okay or you can say if it is a register with a vector input and vector output you could say a register with the preceding logic which can be very complex can be coded using a single process okay. So anytime you see a register and some logic behind it that can be coded using a single process and so it means that you say if clock T given and clock is equal to 1 and if and within that you write some code for combinational circuit which can be complex using you can say case some input is when for each value for each of that cases you can say if some input and additional inputs and so on. It can be complex code here but what happens is that whatever you write here comes at the input of the D. So this combinational circuit the code of that appears here okay that is crux of the matter and mind you as I said anything you write here okay you say suppose Z gets something that Z become a flip flop okay. Any assignment you do under clock T given clock is equal to 1 you will get a flip flop or if it is a vector you will get a register and this should be kept in mind otherwise you will carelessly code something and you will find that everything is delayed by one clock or two clock just because you have forgotten that under this clock T given clock is equal to 1 everything is synchronous it means a flip flop at the assignment now whichever output you get a flip flop that should be kept in mind. So that is what I am saying that this a register or a flip flop with a preceding combinational circuit can be coded as a single process like that okay. So that should be kept in mind and now let us move to the synchronous reset okay now as the name suggests the synchronous reset would mean that if it goes active the Q will not go 0 immediately upon the next positive clock edge the Q will become 0 okay. So you assert at any time but the Q the flip flop is reset when the next clock comes that is the meaning of synchronous reset and we have seen the code for asynchronous reset which has priority over the clock. So we wrote it you know the reset we wrote in the sensitivity list we wrote the reset before because it has priority if reset is 1 then Q gets 0 else if clock given clock is equal to 1 Q gets T okay. But here first of all this is synchronous with the clock it has no priority. So the first thing to do is that the reset has to be removed from the sensitivity list because anytime reset changes it does not respond only when the clock comes it check if reset is 1 then the Q gets 0 as far as the coding is concerned I am not talking about the real circuit part of it that we will worry a while later but I am talking about how to code it you know when the reset when the clock comes if reset is 1 then Q gets 0 else Q gets D. So once the clock comes we have priority for reset over the D okay that has to be kept in mind. So that shows that code has to come under here because it is synchronous to the clock. So we are not going to write reset in the sensitivity list we are going to remove this we are putting back if and we say if clock tick given clock is equal to 1 then we say if reset is 1 then Q gets 0 else Q gets D okay. So that is the code for the synchronous reset we need not we should not write the reset in sensitivity list. So process clock begin if clock tick given and clock is equal to 1 then underneath we say because there is synchronous reset if reset is 1 that has priority Q gets 0 else Q gets D end if okay and this is end if because that represents the memory this if is this end if is for the outer if and this is the inner if okay this is a nested if. Now we are able to write a synchronous reset using the process using if syntax or if construct it is because if can be nested okay. Now if you look in the concurrent statement we told the previous slide we put the concurrent statement and in the concurrent statement there is no way to nest it. So it is very difficult to write synchronous reset in a meaningful way it is not that you know you could maybe you can write Q gets 0 when reset is 1 and clock tick given clock is equal to 1. But it does not kind of convey the right meaning it looks as if you are you know gating the clock with the reset and so on. So it does not convey but maybe if the problem is that the people start writing a statement like that the tool vendors will start incorporating such a thing. So I am not really worried but some synthesis tool will kind of go and synthesize such a statement but what I am saying is that meaning wise the code wise it does not make much sense. So we should not probably try you know coding synchronous reset using the concurrent statement okay. So that should be kept in mind. So this is what is stated here if then allows nesting and synchronous circuit can be coded using synchronous reset can be coded here. In concurrent statement is not possible it is kind of does not make sense to write a code for synchronous reset. Also look at this statement it is a if reset is 1 Q gets 0 else Q gets d okay. So if you carefully look at the code because I am now going to talk about the synthesis tool. Now we talked about the simulator synthesis tool will look at this code okay which say that if clock tick event clock is equal to 1 then if reset is 1 Q gets 0 else Q gets d. So we know that the moment you have if clock tick event clock is equal to 1 and if that is a flip flop okay. There is a d there is a Q that is it. But now we are saying additional if which say that if something is 1 Q gets 0 else Q gets d. So if you think what structure is this then you can think it is a it is a kind of multiplexer 2 to 1 multiplexer where the select line is reset okay which say that if reset is 0 reset is 1 Q gets 0 else Q gets d. So it is a 2 to 1 MUX okay. Now since this is synchronous that 2 to 1 MUX should come should be connected to the d because earlier we have seen we say Q is ax or b then the ax or b should come at the d naturally this 2 to 1 MUX should come at the input d input of the flip flop. So that is what is shown here. So there is a 2 to 1 MUX at the input of the flip flop and the select line is connected to the synchronous reset. And you see when it is 0 and 1 when it is 1 a 0 is connected when it is 0 the real d is real d input is connected. So if reset is 1 the 0 goes there upon the next clock edge if it is 0 then whatever is the input directly goes here again upon the clock edge okay. So you see that this is how the synthesis tool makes sense of the code you write it is natural if clock tick given clock is equal to 1 and if will give you this flip flop and underneath anything within that you write will be connected to the d and there you are saying if reset is 1 Q is 0 else Q is d that is a 2 to 1 MUX. So that is how the synthesis tool is synthesising okay using the known components okay we said that that register transfer logic the RTL coding is based on the registers and the high level blocks we have studied so that is what is shown here. So let us so that should be clear in your mind. So let us look at one other code okay please have a look at this particular code okay. I have not shown the reset but mind you in all the code you please write the reset just because we are learning I did not want to write reset and you know add to the complications I wanted to concentrate on the real the code. So I have removed the reset but then please whenever you code any register any flip flop always add reset to it okay this is just for learning so I have not written the reset. So which says now the process clock begin if clock tick event and clock is equal to 1 Q gets d and R gets Q and if N process so it in a very kind of trivial way if you look at it say Q gets d R gets Q so you can say R gets d or something like that but mind you by definition this assignment has some delta cycle significance it is not an immediate assignment. So if there is an event on clock at t nanosecond then we know that when the meaning is that this Q gets assigned t plus delta so there is an event whatever may be the value at the d will be assigned Q of t plus delta and when it comes to the R statement whatever was the value of Q at time t is assigned to R at t plus delta okay. So R will get the previous value of the Q and the Q will get the new value of the current value of the d after t plus delta okay. So you see that it is not that the r gets d after t plus delta so you see that the event has happened at t so whatever was the value of d at the time instant t is assigned Q at t plus delta. Now whatever was the value of Q is assigned to R you know whatever was the value of Q at time t is assigned to R at t plus delta now the game is over. So the R gets the previous value of Q Q gets the previous value of d. So it is like a chain of flip flops it is not a single flip flop and when the simulation time is moved now to t plus delta then the t plus delta value of d will go to t plus 2 delta value of Q and so on okay. So that is how it proceed but the essence is that you get something like this okay. You will get two flip flops the first flip flop will give you the Q the second flip flop will give you the R okay. So if you do and that is consistent with whatever we have told you write any assignment you get a flip flop. So the Q gets a flip flop R gets a flip flop so that is what it goes so that gives you an idea how to code a shift register okay. So let us look at the this kind of 8 bit shift register okay I should have shown it kind of instead of left to right right to left because I treat Q7 as the MSP but I hope you just get it we treat Q7 as the MSP. So normally we write the MSP on the left hand side but you instead of flipping it I did not get time to flip it out. So assume that the Q7 is MSP so when the clock comes D0 go to Q0 and the Q0 go to Q1 and so on Q1 goes to Q2 and the Q6 go to Q7 this is just the continuation I have not shown what is in between. So this code gives you a clue what to write so which say that if clock given clock is equal to 1 Q0 will get D0 then Q1 gets D1 Q2 gets D2 and so on you have to write all the way now all the way up to Q7 okay. Now we know that another way of writing instead of writing it you know each assignment distinctly we can write a loop we can say for I in initially we will make an assignment like Q0 get D0 then we will say for I in like 0 to 6 loop QI plus 1 is QI so like that we can say so that is what I am saying here plus clock begin if clock tick event and clock is equal to 1 then Q0 get D0. So that makes the first assignment out of the loop then for I in 0 to 6 loop QI plus 1 is QI so if the index is 0 then Q1 is Q0 when index is 1 then Q2 gets Q1 when the index is 6 Q7 get Q0 sorry Q6 and you could definitely we have made a little goof up probably in naming this as D0 if we had named you know like Q0 Q1 like that we could have written everything in a loop that depends on your naming convention but there is another way of looking at it instead of looking at kind of bit by bit we can treat it as a vector okay. So if you instead of looking at bit by bit let us look at it as a vector so if you look at the vector what happens is that basically Q7 to Q0 that is Q7 Q6 Q1 Q0 is going to get Q6 because Q7 is getting Q6 Q6 down to 0 and D0 so we can say if you look at it as a vector then you can say Q7 down to 0 which is nothing but Q as we have defined then we will get Q6 down to 0 and D0 so we are viewing instead of kind of bit by bit we are viewing it as a vector. So that is a more convenient way than writing a loop so you can say in one shot if clock tick even and clock is equal to 1 then Q which is 7 down to 0 gets Q6 down to 0 and D0 and that is if you write 7 down to 0 it becomes very clear the 7 gets 6 and 0 gets D0 and everything in in the same order okay. So this is a better way of coding than this and in one shot it is done it is easy to look at the picture and code it and it is kind of consistent with the diagrams we do because I said I will not be drawing you know kind of individual flip flops. So in principle we can show you know 8 flip flops together with tick line here which says Q is here and here we say Q6 down to 0 and D0 then in one shot it becomes a flip flop very kind of concise way of representing it so that is the code for a shift register. So now let us look at a code for counter a simple binary counter which is kind of 8 bit. So this counts from 0 to 255 so you see here the main code I am going to show first. So here we have declared a signal this is kind of it shows how to use a signal signal Q standard logic vector 7 down to 0 and we have in the entity clock and reset is input. You see here process clock reset okay if reset is 1 then Q gets others 0 because it is an 8 bit output else if clock tick event clock is equal to 1 Q gets Q plus 1 it says that if reset is there Q is initialized 0 otherwise Q gets incremented value of the Q that means Q gets whatever was the previous value of Q plus 1 because this is at t plus delta this t plus 1 okay. Now you realize actual output in the entity is called count which is of type out which is standard logic vector 7 down to 0. We will not be in a position to write count here because if you say count others 0 is fine but here if you say count gets count plus 1 cannot be done because count is an out kind of mode output and output should come on the left hand side of the assignment not on the right hand side of the assignment. So the trick we do is that we define a signal internally which is exactly same data type as this output port. So we define that signal Q standard logic vector 7 down to 0 and this is not signal as both you know there is no direction like output or input one side is input the other side is output. So we can happily say Q gets Q plus 1 and we say in the before the process or anywhere in the architecture declaration region we say count gets Q okay. So that is how we use we avoid the use of buffer because buffer has restriction. So we use signals to circumvent this scenario of using something some output gets output plus 1. So we declare signal and that signal is assigned to the real output okay that is the meaning of it and this plus which is now you look the entity clock and reset is standard logic input count is standard logic vector 7 down to 0. So is the Q now we are saying that a standard logic vector gets standard logic vector plus 1 and 1 is an integer okay I am not writing 1 with within the codes okay. So this plus is not the standard plus the standard plus is for basically for integer here one side is standard logic vector one side is integer. So this operator is overloaded in this particular package use say standard logic underscore unsigned package that is why we say here use IEEE standard logic unsigned dot all okay. So that is the code for the counter once again you have library you have use IEEE standard logic 1164 that is the one which is defining the standard logic and we use standard logic unsigned for this plus to be used and we have clock and reset as input port as output since we are somewhere going to say Q get something plus 1 we declare in the architecture declaration region we say architecture a name of this particular count 8 is signal we say Q standard logic vector 7 down to 0 then begin in the first thing we do is that not to forget is that the count gets Q because that is the same thing we circumvent the problem of the right hand side you know the output for right hand side by declaring a signal and assigning the signal to the output and we say process clock reset begin if reset is 1 Q gets others 0 else if clock tick event and clock is equal to 1 Q gets Q plus 1 end if end process okay that is how we get the counter. Now with the previous synchronous reset if you look at the code then which say that look at this code which say Q gets Q plus 1 upon the clock okay. So this is a synchronous reset but when the clock comes the Q is Q plus 1 so that means that the output is you know taken back to the D and an incrementer comes here and give it to the D that is a meaning of it. So you get such a circuit you have 8 flip flops all the clocks are tied together and connected to the clock all the resets are tied together and connected to the reset. So upon the reset this is reset and upon the clock Q is taken and given to an incrementer and the output is given to the D. So that is the meaning when the clock if clock 1 and clock is equal to 1 Q gets Q plus 1. So when the clock comes this Q gets Q plus 1 that is how it is synthesized symbol 1 incrementer at the input D and you see this is the signal Q and this is the output port count and we say Q is coming all the way here because Q is Q plus 1 and this is the count output so the Q is assigned to the count that is the meaning of it. That is how the synthesis tool synthesize and now let us make it little more complex. We will write a preset about counter that means same thing we have clock reset load okay which is input and we have a data input which is 8 bit vector we have a count which is 8 bit vector output. So the game is that when the load is 1 and when the clock is it is a synchronous load okay synchronous sleep preset above. When the load is 1 when the clock comes this data in goes to the count and then if the load goes 0 whatever was the loaded value the count starts from there okay so you preset a value load a value to the counter and start counting from there that is the meaning of it. So that is it and we use we are going to use incrementer plus 1 so that plus come from here. So use IEEE standard logic unsigned clock reset load is standard logic in D in is again the preset value in is standard logic vector 7 down to 0. The count is out standard logic vector 7 down to 0 by now we are very clear that we have to say something plus output gets output plus 1. So we declare a signal which is of same type as count which is used inside and we assign count gets q. Now in the code you say process clock reset if reset is 1 then q gets other 0 else if clock tick event and clock is equal to 1 now the synchronous load start okay. Now when you say else if clock tick event and clock is equal to 1 and if that is where you get the flip flop now we say if load is 1 then q gets the D in. So when the clock comes if load is 1 q gets D in the load is not 1 then q gets q plus 1 okay. So that gives you so the load as priority over incrementing the load is 1 and the clock comes does not increment it loads a new value and if load is 0 then the q gets incremented and anyway we are assigning q to count then the count get incremented. Now once again look at this code this says that upon the clock load is 1 then q gets D in else q gets q plus 1 this shows a kind of 2 to 1 marks. So with the select line as load so when the load is 1 q that marks will get D in the one part this otherwise 0th part will get q fed back through an increment. So that is what is the synthesis tool is going to do. So it put a marks here because it has priority over the counting. So the load is a select signal of the 2 to 1 marks when it is 1 because it has priority D in is connected to the D. So upon the clock this comes here and if it is load is 0 then whatever is here is incremented and it is keep on incrementing as long as the load is 0. So that is how the synthesis tool synthesize a circuit in terms of flip flops in terms of maxes in terms of decoders the increment, adder, subtractor and so on. So you can practice some kind of exercise I will as we go along I will show you a real tool how to simulate this and we will see the simulation with the tool and so on. So that is the kind of the sequential circuit coding we have looked at basically today the asynchronous reset. So the reset is coded as a priority before the clock tick event clock is equal to 1. Then we looked at the synchronous reset when we looked at the combinational circuit before the flip flop or registers where under the clock tick event clock is equal to 1 any assignment you make become a combinational circuit at the input of the flip flop or registers. So that is how to do it only thing is that you have to be cautious so anything you write you get a flip flop and we have seen how to write a shift register like if you write 2 assignment then 1 get the other then you get a chain of flip flops chain of 2 flip flops. So you can extend that to form a shift register and we have seen how to write a loop to implement a shift register or treat it as a vector which is much more concise, elegant, easy to understand otherwise if you write a complex loop then somebody has to put the index work through the index and so on. So writing is as a vector is a much more much better way to code shift register and we have looked at the counter how to write the counter. So we have looked at how to declare a signal and write the code like q gets q plus 1 because q is a signal you cannot write the count is count plus 1 because count is an output which cannot come on the right hand side. We circumvent this problem by declaring a similar signal and assigning that signal to the output in the architecture statement region as a concurrent statement. We also have seen how to write a synchronous reset so it becomes as for a synthesis tool is concerned it becomes a 2 to 1 marks because in the under the clock tick event clock is equal to 1 we say if reset is 1 q gets 0 else q gets t that represent the structure of a 2 to 1 marks then we have seen a similar a pre-setable counter a synchronously loadable counter. So the load and dean is input so which is synchronous so again under the clock tick event clock is equal to 1 we say if load is 1 then whatever is input value goes to the q else q gets incremented. So it again comes as a 2 to 1 marks at the input of the flip flop or the register. So when it is 0 the input goes directly when it is 1 then the q gets incremented or other way whatever is the polarity ok. So let us come back to the coding scenario. So when we code it when you have a top level code like a CPU at the top most level a complex circuit not simple circuit like adder and all that. So mostly at the top level we will have a structural code which is a interconnection of various components ok. So in the case of CPU you have maybe registers a program counter ALU. So all will be a structural coding mostly and you take ALU say and further divide into pieces again this could be structural code composed of adder, subtractor, logical unit and so on. But at this level when you take further divide you take the adder then we do not write maybe a structural coding. Maybe we write some kind of a combination of various concurrent statement and processes at the lower most level ok. So when you write a component you write it using number of processes concurrent statement which are all concurrent. But at the second level at the next top level we use structural coding to interconnect and top most level is almost always structural coding. But this maybe combine the structural code some concurrent statement and things like that. But that is how the coding scenario is now we will go little more with the VHDL before we go to the digital design. So maybe because there are some part to be able to do some exercise we need something called test benches. So we will complete this kind of sequential part to a decent level then look at the test bench then come back to the maybe we will have a tool demo then we will come back to the digital design then continue with the PLDs FPGA. Once again come back to the digital circuit and so on ok. So let us go ahead with the libraries and packages these are mainly nothing very serious and most of it is syntax. So we can quickly run through that. But to illustrate the packages I want to take a very simple example basically in the package we are trying to write some component and instantiate in a top level code. Ok. So let us take a very simple example because if I take a complex example then we have to understand the circuit the code becomes big it may not go in a kind of slide. So I have limited this so let us take this is the component a simple D flip flop. Once again I have not shown reset for brevity but in real life always add reset the clock input D and the Q. This shows a top level entity which is an instantiation of two flip flops basic component flip flops and interconnected as a shift register. You can say it is a two stage shift register but this has a use which is called as double stage synchronizer. Once again we will see what is a double stage synchronizer towards the end of the course in timing issues. I will touch upon it because that is I would not have the time to go through all the details of the synchronization but then at least I will state the problem state the issue and a quick solution using some of the synchronizers ok. So this is a simple enough circuit which is like two flip flops in chain ok. So this is the first flip flop this is the second flip flop the D for the first D is connected to the input the first Q is going to an internal signal that is going to the next flip flop D and the real output is called SOP which is synchronous output ok. This is an internal signal this is the real input and the clocks are tied together it is called S clock which is synchronous clock ok. Now we will see how in a simple code how do we construct this which you should be familiar by now because we have seen a structural coding of a ripple adder using the flip flops sorry using the full adder as a component. So the same thing we will repeat it then we will see how to write this component in a package and instantiate it from a package that is our idea to start with. So this is the flip flop code you say library IEEE use IEEE standard logic 1164 because that is for the standard logic entity data flip flop that is this one is port D, clock is in standard logic these are standard logic Q is out standard logic and data flip flop then we write the architecture. Architecture behave of data flip flop is begin process clock begin if clock tick event and clock is equal to 1 then Q gets t and if and process and behave now I think you are quite familiar. So I am kind to save space by writing this in a single line. So normally we used to write Q gets t with an indenting Q gets t so that is one point you should remember when you write the code do the proper indenting okay. So the VHDL does not have any significance on the carriage return or a line feed. So like earlier we used to write library IEEE then in the new line we used to write use IEEE as far as long as the semicolon is there you could write it in one kind of line to save space I have written like that but you do write in a decent form. So in principle you can start the entity here but then nobody will be able to understand. So please write entity separate you know I have given some blank line in between and I have also indented what is inside a bit inside. So you can see that in the process the begin so what is inside I have indented and normally whatever is underneath I will indent it one or two lines one or two characters. So please do the proper indenting so that people can read and understand. Suppose if you write another if nested then definitely it has to come with a little 2, 3 characters inside. So that the people can understand like in the earlier code here we see here if else if and if that is in one kind of line and underneath here if else if in one line. So if I had written everything in line then when it comes to end if you have no way to match it and very difficult to understand. So please use proper indentation but mind you some people it is better to give some 2, 3 characters do not press a tab sometime because if you keep on indenting then some 2, 3 level of nesting then it goes all the way out of the screen out of the paper when you take print out. Also some people have the habit of writing everything in capital letters please do not do that it is quite irritating there is no need to write everything in capital and some people are very bad at you know it looks everything is kind of in a single line that is quite horrible nobody will be able to understand it. So please use proper indentation similarly when you use an operator give some space around like equal you could write in principle reset without space equal to 1 but in some places you can confuse the tool wherever there is there could be need of separation okay. So please give I should have told this at the beginning but then we have come to a decent stage of looking at the code you please indent it properly please write it neatly so that people can understand because unless you cultivate that habit if you pick up some bad habits and it proceed and like your code can become obscure nobody will be able to understand that okay. So here this is the code for the flip flop and now we will see that is the library entity and the architecture okay. Now we are going to write a top level code where this particular component is instantiated assume that this is written in the same project. Of course you may not know what is a project I will demonstrate that at least think that this is written in the same file maybe and in the next kind of what comes next in the file is a top level entity which is the double synchronizer which is this one okay. So we say library use close then entity double sync is port input S clock is in SOP is out. So here you have input S clock is a input and SOP is out and that say that this is an internal signal because this is now the top level component where this is instantiated twice and this is an internal signal. So we have to declare this particular component declare this internal signal instantiated twice okay. So we are going to the architecture architecture some name of this double sequence then we say component data flip flop that is the component we have written here you say port D clock is in standard logic Q is out standard logic. So N component so that is the component declaration and we have to declare this particular signal. So that is signal in one is standard logic. So we have declared after the entity we start to the architecture before the begin we have declared the component we have declared the signal. Now we are going to instantiate this two times and with this connection input is connected to the D of the first flip flop the output of the first D flip flop is in one input of the second flip flop is in one the clock is same and the output of the second flip flop is SOP okay. So we say begin C1 the data flip flop port map the input S clock in one. So input goes to D, S clock is clock and in one is Q. C2 data flip flop port one. So that in one output goes to the input D, S clock is same clock and the output is SOP. So you get the kind of double stage synchronizer with the D flip flop as component and this is how we write normally. Now what we are going to see next is that how to put this in a package and compile it into a library and we write a top level component of double stage synchronizer with that component now coming from the library rather than from our own file our own code okay. That is what we are going to see now we are coming to the end of the lecture. So I will take that up in the next lecture. So we have seen towards the last part basically how to write we are going to like we have done the preparatory work how to write a component in a package and put it in library. As an example we have chosen the case of a top level entity double stage synchronizer which is nothing but a two stage shift register composed of D flip flop. So we saw how to write the D flip flop code how to instantiate in the top level component by declaring the component and declaring the internal signal. So as I said in the next lecture we are going to see how to put this in a package and that package in a library and instantiate it from the library and we will proceed you know how to a little more about the standard libraries and so on. So today we have seen all of that sequential circuit basically the synchronous reset how to code combinational circuit along with the registers. We have seen some example shift registers counters then we have proceeded to the packages and libraries how to write components and at least the beginning part of it. So please go back and revise it try to understand that if you already are using a tool try to write some proper code see how it is getting synthesized and so on. So I wish you all the best and thank you.