 Chavan, Assistant Professor, Department of Computer Science and Engineering, Walton Institute of Technology, Solopu. Now I am here to explain IC8259 which is Programmable Interrupt Controller. At the end of this session, the student will be able to describe the block diagram of IC8259 which is called Programmable Interrupt Controller. Let us see the features of IC8259 Programmable Interrupt Controller. It can handle 8 interrupts at a time. This chip can vector and interrupt requests anywhere in the range of 0000 to FF, FF according to 85 microprocessor. So, it can solve 8 levels of interrupt priorities in a variety of modes. One IC8259 can handle 8 different interrupts IR02, IR7. So, it can resolve those interrupt requests based on priorities. Each of the interrupts which is requested through IRR can be masked individually as that of the RST 7.5, 6.5, 5.5 interrupts of microprocessor 8085. So, these interrupts which are coming those interrupts can be masked. The status of pending interrupts which was requested and the status of service interrupts all these can be identified and along with the interrupts which are masked those also can be read at any time as that of RST interrupts according to 8085. Normally the requested interrupt may be in pending or it may be in service state or it may be masked. This chip it can be programmed so that it can accept the interrupt request based on two concepts. One is a level trigger and another is edge trigger. So, edge trigger may be falling edge or may be rising edge. So, like this it can be accept interrupts. If required the maximum 8 number of 8259 can be cascaded so that it can handle 634 different interrupts and it can be cascaded in the master slave configuration. So, one 8259 supports for 8 different interrupts and 88259 leads 64 different interrupts. Next topic which is about PIN Diagram of 8259. This is the PIN Diagram of IC8259. It has total 28 pins. PIN number 14 is ground and PIN number 28 is VCC. PIN number 1 chip select which is going to select 8259. Headbar, Readbar, Actualosignals these pins involve for writing and reading of data from or towards the external device. The data lines D0, D1, D2, D3, D4, D5, D6, D7 these are used which is 8 bit in nature. Next CAS which indicates cascade CAS0, CAS1, CAS2 these 3 pins are used for cascading 8259. Normally 3 pins are there 2 raise to 3 8 different 8259 can be cascaded. Next SP and EN bar these are used for slave purpose. INT indicates interrupt and INTA is a interrupt acknowledgement. When the external interrupt comes then that will be indicated through PIN number 17. With respect to this the acknowledgement will be sent through INTA PIN, A0 address lines and this is for powers. Moving to next bit which describes the pins like chip select, signal, write these are active low then read signal data D0 to D7, data bus then cascade signals CAS0, CAS1, CAS2 so these are used for cascading 8259. So 3 pins in the sense that 2 raise to 3, 64, 2 raise to 8, 64 different interrupts can be handled. Slave program and enable buffer. Next interrupt with respect to requested interrupt there is acknowledgement called interrupt acknowledgement this is active low PIN. The interrupt requests are coming from IR0 to IR7 interrupt request inputs address line is 0. So this is about pins of 8 to 5 9 just think about this question and try to answer the question is which pins are used to cascade in a master slope configuration mode to handle 64 interrupt inputs. Pause this video and answer for this question. The answer is PIN CAS0, CAS1 and CAS2, cascaded lines. Normally these 3 pins 2 raise to 8, 2 raise to 3 which is equal to 8, 8 different interrupt request are supported and for each one there is 1, 8 to 5 9 is connected means 8 into 8, 64 different interrupts can be handled. Let us see the block diagram of 8 to 5 9. This block diagram consists different units like in service register, priority resolver, request register, interrupt mask register, control logic, data bus buffer, read write logic, cascade buffer or comparator. These are the different units used in block diagram of 8 to 5. These units are connected in this way and control logic is connected to all the units. Let us see the block diagram in detail. Initially the interrupt request is coming on control logic and with respect to the request the control logic unit sends the acknowledgement. If acknowledgement is accepted then the further interrupts are going to interact with 8 to 5 9. So this interrupt request register IRR, this unit accepts the interrupt request. At the time maximum 8 interrupts can sense IR0 to IR7. Out of these 8 interrupts 1 interrupt is supposed to be silent at a time. So for that those interrupts are forwarded towards priority resolver. This priority resolver selects one interrupt among 8 based on priority. So the interrupt which is selected is further forwarded to in service register called ISR. So this interrupt is going to serve further. Next the interrupt mask register. So this register helps to mask the interrupts which are requested. So normally the requested interrupt may be in service or it may be mask or it may be in pending state. So once the interrupt is selected by a particular service routine then the further communication takes place between requested device and external device through internal data bus. Through this bus the data will be fetched and stored in data bus buffer and this read write logic controls whether to read or write the data to or from the external device. This cascade buffer and comparator it helps to cascade the 8 to 5 nines. There are 3 pins 8 combinations each combination supports for 1 8 to 5 nines and hence 64 different interrupts it can handle. So data bus buffer stores the data temporarily read write and control logic helps for reading and writing the data and to generate the appropriate control signals. Interrupt request register this register holds all the 8 interrupts. Interrupt mask register it helps to mask the requested interrupts. So the priority is cascade buffer and comparator helps for cascading. These are the references. Thank you.