 Hello everyone, I am Prasanthesmalgay, Assistant Professor, Department of Electronics Engineering Vulture Institute of Technology, Solapur . Today, we will discuss some of the techniques for testing the logic circuits, learning outcome. At the end of this session, student will be able to derive the test set for the given circuit for detecting faults, contents, introduction, fault model, stuck cat model, single and multiple faults and complexity of a test set. Once the circuit is designed, we need to verify that whether the circuit performs as required or not, how one will verify this. So, today we will discuss some of the techniques for verifying the functionality of a circuit. The basis of all the testing methods is to apply a set of inputs known as a test to a circuit and to compare the output results with the responses that the correct circuit is supposed to produce. The challenge here is to derive a small number of test set to ensure that the circuit is functioning correctly. Now, we will see a fault model. The circuit behaves incorrectly if something goes wrong with it, may be a transistor fault or may be an interconnection fault . See for example, a transistor switch can break so that it is permanently either closed or open. A wire in the circuit can be shorted to either VDD or to ground or it can be simply broken. Unwanted connection between two wires or maybe a logic gate generates a wrong output signal because of some fault in the circuitry which implements that particular gate. Only to deal with all the varieties of these faults is a difficult, but it is possible to restrict these faults to some simple faults and obtain satisfactory results. Now, stuck at model, most of the circuits which we deal with consist of the logic gates as their basic building blocks . So, a good model for representing the fault in such circuits is to assume that all the faults appear as if a wire may be input or output of these gates being permanently stuck at a logic 0 or logic 1. Say for example, if a wire W has an undesirable signal that always corresponds to the logic value 0, we say that the wire W is stuck at 0 which is denoted as W slash 0. On same lines, if W has an undesirable signal that is always equal to logic 1, then we say that W is stuck at 1 which is denoted as W stuck at 1. So, the stuck at model is also useful for dealing with the faults of other types which often cause same problems as if a wire is stuck at 0 or stuck at 1. So, we restrict our discussion to stuck at faults and discuss the testing process assuming that these are the only faults available in a circuit . Now, single versus multiple faults. Now, the circuit may be faulty because of either a single fault or possibly be possibly many faults, but dealing with multiple faults is difficult because each fault can occur in many different ways. So, a practical way is to consider single faults only. Practice has shown that the test set that detects a single faults in a circuit also detects majority of the multiple faults in a circuit. So, actually a fault is detected if the output value produced by the faulty circuit is different from the value produced by the good circuit when an appropriate test is applied. Each test is supposed to be able to detect the occurrence of one or more faults. So, a complete set of tests used for given circuit is referred to as a test set. So, our aim is to derive a minimal test set required for testing a circuit. So, now, we will see the complexity of a test set. So, one possible method for testing is to apply a test set that comprises all the possible input valuations and check if the output values produced by the circuit are same as a specified by the truth table. But this particular method is effective if the circuits are small because where the test set is not too large, but it becomes impractical for a larger circuits with many input variables. Fortunately, it is not necessary to apply all two raise to n valuations as test for a n input circuit. A complete test set capable of detecting all single faults usually consists of smaller number of tests. Now, consider the circuit shown in figure. Here we have three inputs W1, W2, W3. There are four wires A, B, C, D and fifth is an output. Now, think about which faults will be detected by applying inputs W1, W2, W3 equal to 000. Pause the video for a minute and write down your answer. Okay. Now, I will see what happens when the inputs are 000. When W1, W2, W3 are 000 the correct output is 0, but a faulty circuit will give you an output 1 and this fault may be due to either this wire A stuck at 1 or D stuck at 1 or F stuck at 1. So, in case when we are applying 000 and the output generated is 1, in that case the circuit may be having either A stuck at 1, D stuck at 1 and F stuck at 1. So, these three faults will be detected by a test vector 000. Similarly, we can obtain the faults detected by each of the different test vectors. Say for example, 001 in case of 001 once again the correct output is 0, but faulty circuit will produce 1. This may be due to once again A stuck at 1, F stuck at 1, D stuck at 1 or this B stuck at 1. So, additionally here this B stuck at 1 is also detected. The same way we can do it for others and we get with 010 as the faults detected. Similar procedure we can follow and we can see that different vectors which detects the different faults. Say for example, in case of 111 the last one correct output is 1, but it may be 0 and this particular 0 output may be possible only with F stuck at 0. So, this is how for all the different test vectors we have detected the faults. Now to derive a minimal test set what we can do is we will select the input test vectors so that all the faults will be detected. Now for example, B stuck at 0 is detected by only 011. So, this must be taken as a test vector in a test set. Similarly, B stuck at 1 with only 001, C stuck at 0 with only 011 and D stuck at sorry. So, this 001, 010 and 011 will be taken and this 100 will detect A stuck at 0 as well as F stuck at 0. So, therefore, a minimal test set that covers all faults in the circuit can be derived from the table as 001, 010, 011 and 100. So, in this case as we have seen instead of 8 test vectors only these 4 test vectors will detect all the possible faults in a circuit. So, this is how a test set can be generated. References. Thank you.