 Hello and welcome to this presentation of the STM32G0 power controller. The STM32G0's power management functions and all low power modes will also be covered in this presentation. STM32G0 devices feature flex power control, which increases flexibility in power mode management and further reduces the overall application consumption. Run mode can support a system clock running at up to 64 MHz with only 100 microamps per MHz. At 16 MHz the consumption is even lower, 93 microamps per MHz. STM32G0 devices support 7 main low power modes. Low power run, sleep, low power sleep, stop 0, stop 1, stand by and shutdown modes. Each mode can be configured in many ways, providing several additional sub modes. In addition, STM32G0 devices support a battery backup domain called VBAT. The high flexibility in power management provides both high performance with a core mark score equal to 125, together with an outstanding power efficiency. The STM32G0 has several key features related to power management. Several low power modes down to 30 nanoamps while it is still possible to wake up the MCU with an event on an I.O. For only 320 nanoamps, 36 kilobytes of SRAM can be retained assuming a 3 volts VDD power supply. A large number of peripherals can wake up from the various low power modes. Dynamic consumption is down to 100 microamps per MHz, executing from flash memory. A battery backup domain called VBAT including the RTC and certain backup registers. Several power supplies are independent, allowing to reduce MCU power consumption while some peripherals are supplied at higher voltages. Thanks to the large number of power modes, STM32G0 devices offer high flexibility to minimize the power consumption and adjust it depending on active peripherals, required performance and needed wake up sources. STM32G0 devices have several independent power supplies which can be set at different voltages or tied together. The main power supply is VDD, supplying almost all I.Os except those part of the VBAT domain. VDD also supplies the flash memory, the reset block temperature sensor and all internal clock sources. In addition, it supplies the standby circuitry which includes the wake up logic and independent watchdog. VDD supplies voltage regulators which provide the V-core supply. V-core supplies most of the digital peripherals, SRAMs and flash controller. VDD A voltage is the same as the VDD 1 and supplies the analog peripherals. The Vref plus pin provides the reference voltage to the analog to digital and digital to analog converters and can be used as an external buffer reference for the application. A backup battery can be connected to VBAT pin to supply the backup domain. The main power supply VDD ensures full feature operation in all power modes from 1.71 up to 3.6 volts, allowing to be supplied by an external 1.8 volts regulator. Device functionality is guaranteed down to 1.6 volt. The minimum voltage after which power down reset is generated. Other independent supplies are provided to allow peripherals to operate at a different voltage. The analog power supply VDD A is always connected to VDD. When the analog to digital converters or comparators are used, the VDD A voltage must be greater than 1.62 volts. When the digital to analog converters are used, VDD A must be greater than 1.8 volts. When the voltage reference buffer is used, VDD A must be greater than 2.4 volts. A backup domain is supplied by VBAT, which must be greater than 1.55 volts. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator, and the TAMP block containing the 20-byte backup registers. The ADC and DAC voltage references can be provided either by an external supply voltage or by the internal reference buffer. This allows to improve converters performance by providing an isolated and independent reference voltage. The Vref plus pin, and thus the internal voltage reference, is not available on low-pin count packages. In those packages, the Vref plus pin is double bonded with VDD VDD A, and the internal voltage buffer must be kept disabled. The voltage reference can be provided through the VDD A pin in those packages. The power supply supervisor guarantees a safe and ultra-low power reset management. STM32G0 devices embed a power-on reset called POR and a power-down reset called PDR, which are always enabled in all power modes except shutdown mode. STM32G0 devices embed an ultra-low power brown-out reset called BOR, which is active periodically instead of continuously monitoring the power voltage. The BOR ensures reset generation as soon as the MCU power supply drops below the selected threshold, regardless of the VDD slope. Four thresholds from 2.0 to 2.95 volts can be selected by option-byte programmed in flash memory independently for rising and falling edge. It can also be disabled to save power consumption. A power voltage detector called PVD can generate an interrupt when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby and shutdown modes. Seven thresholds independently configurable for rising and falling edges can be selected by software. In addition, comparisons can be done between Vref int and the PVD in external pin. In the STM32G0 devices, the reset monitoring circuitry BOR and POR-PDR can be enabled in a periodic sampling mode. This mode is activated by setting the ULPEN bit to 1. The resistor bridge necessary for their functionality is powered only during a short time periodically. It reduces consequently the power consumption. The power resets BOR and POR resets all registers except those in backup domain powered by VBAT, which contains the RTC and TAMP blocks and the external low-speed oscillator LSE. When exiting standby mode, all registers powered by the main regulator are reset. When exiting shutdown mode, a power reset is generated. When the BOR is enabled, four BOR levels can be selected through option bytes with independent configuration for rising and falling thresholds. The backup domain reset occurs when the BDRST bit is set in the RCC backup domain control register. It also occurs when VDD and VBAT are powered on if both supplies have previously been powered off. It resets the RTC and TAMP registers, the backup registers, and the RCC backup domain control register. Two embedded linear voltage regulators supply all the digital circuitries except for the standby circuitry and the backup domain. The regulator output voltage VCOR can be programmed by software to two different values depending on the performance and the power consumption requirements. This is called dynamic voltage scaling. Depending on the application mode, VCOR is provided either by the main voltage regulator for run, sleep, and stop-zero modes or by the low-power regulator for low-power run, low-power sleep, stop-one modes. The regulators are off in standby and shutdown mode. When SRAM content is preserved in standby mode, the low-power regulator remains on and provides the SRAM supply. In run mode, the CPU is clocked and program can be executed from flash or SRAM memory. In range one, the system clock is up to 64 MHz. In range two, it's up to 16 MHz. By default, the SRAM clock is enabled. It can be gated off during sleep mode by software. All peripherals can be activated in range one. The run mode consumption is 100 microamps per MHz in range one at 64 MHz with the flash memory on at 25 Celsius degrees. In range two, all peripherals can be active, but the flash memory cannot be programmed or erased. The run mode consumption is 75 microamps per MHz in range two at 16 MHz with the flash memory off. In low-power run mode, the CPU is clocked and program can be executed from flash or SRAM. Additionally, the flash can be completely unpowered to save power. The system clock is limited to 2 MHz. The main regulator is switched off and supply to digital blocks is provided by the low-power regulator. In low-power mode, all peripherals can be active. The run mode, thanks to voltage scaling and the low-power run modes, offer flexibility between required performance and consumption. In run mode range one, the system clock is limited to 64 MHz and the internal and external oscillators and the PLL can be used. In run mode range two, the system clock is limited to 16 MHz and the internal and external oscillators as well as the PLL can be used, but must be limited to 16 MHz. In low-power run mode, the system clock must be limited to 2 MHz. Each peripheral clock can be configured to be on or off in run and low-power run modes. By default, all peripherals clocks are off except the flash interface clock. The SRAM clock is always on in run mode. When running from SRAM in run or low-power run modes, the flash memory can be put in power down mode thanks to software and the flash clock can be switched off. The flash memory must not be accessed when it's switched off. Consequently, interrupt vectors must be mapped in SRAM using the Cortex M0 plus vector table offset register. The current consumption in run or low-power run modes depends on several parameters. First, the executed binary code. That means the program itself plus the compiler impact. Then it depends on the program location in the memory, the device software configuration, the IO pin loading and switching rate, and the temperature. The consumption also depends on whether the code is executed from flash memory or from SRAM. Energy efficiency is better when the flash prefetch and the instruction cache are enabled. Executing from flash consumes more than executing from SRAM because the flash memory belongs to the VDD power domain while the SRAM belongs to the Vcore power domain. Sleep and low-power sleep modes allow all peripherals to be used and features the fastest wake-up time. In these modes, the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep and low-power sleep modes. These modes are entered by executing the assembler instructions wait for interrupt WFI or wait for event WFE. When executed in low-power run mode, the device enters low-power sleep mode. Depending on the sleep-on-exit bit configuration in the Cortex M0 plus system control register, the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupt subroutine. This last configuration allows to save time and consumption by saving the need to pop and push the stack when exiting the low-power mode. However, all computations must be done in Cortex M0 plus handler mode because the thread mode is no longer used. Batch acquisition mode is an optimized mode for transferring data. Only the needed communication peripherals plus the DMA plus the SRAM are configured with clock enabled in sleep mode. Flash memory is put in power down mode and the flash memory clock is gated off during sleep mode. Then it can enter either sleep or low-power sleep mode. Note that the I2C clock can be at 16 MHz even in low-power sleep mode allowing support for 1 MHz fast mode plus. The USART and LPUART clocks can also be based on the high-speed internal oscillator. Typical applications are sensor hubs. In sleep mode, the CPU clocks are off. In range 1, the system clock is up to 64 MHz. In range 2, it is up to 16 MHz. By default, the SRAM clock is enabled. It can be gated off during sleep mode by software. All peripherals can be activated in range 1. The sleep mode consumption is 25 microamps per MHz in range 1 at 64 MHz with the flash memory on. In range 2, all peripherals can be activated but the flash memory cannot be programmed or erased. The sleep mode consumption is 25 microamps per MHz in range 2 at 16 MHz with the flash memory on. In low-power sleep mode, the CPU clock is off and the logic is supplied by the low-power regulator. The system clock is up to 2 MHz. Flash memory can be configured in power down and can be gated off. SRAM can be gated off. All peripherals can be active. The low-power sleep mode consumption is 46.5 microamps per MHz at 2 MHz with flash memory disabled. STM32G0 devices features two stop modes, stop 0 and 1 which are the lowest power modes with full retention and only a 2 microsecond wake-up time to run mode at 16 MHz. The contents of SRAM and all peripherals registers are preserved in stop modes. All high-speed clocks are stopped. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake up from stop mode. System clock on wake-up is the internal high-speed oscillator at 16 MHz with only a 2 microsecond wake-up time from SRAM or 5 microseconds from flash. The divider configuration to SIS clock is kept upon wake-up. Stop 1 is similar to stop 0 with the main regulator switched off. The voltage regulator is configured in main regulator mode. All clocks in the V-cordo main are stopped. The PLL, the HSI 16 and the HSE oscillators are disabled. The RTC, clocked by the internal or external low-speed oscillator can remain active. The brown-out reset is always enabled. Most of the peripheral clocks are gated off. Several peripherals can be functional in stop-zero mode. Power voltage detector, digital-to-analog converters, comparators, independent watchdog, low-power timers, I2C, UART and low-power UART. The events from all IOs can wake up from stop-zero mode as well as the interrupt generated by the active peripherals. The I2C and UART HDMI CEC or LP UART can switch the HSI 16 on during the stop mode in order to recognize their wake-up condition and switch off the HSI 16 after receiving the frame if it is not a wake-up frame. In this case, the HSI 16 clock is propagated only to the peripheral requesting it. The stop-zero mode consumption typical at 3 volts is 97 microamps when HSI is disabled, 276 microamps when HSI is enabled. The wake-up time is 2 microseconds and the system clock at wake-up is HSI at 16 megahertz assuming execution in SRAM or in powered flash memory. It is 5.5 microseconds when execution is from the initially non-powered flash. Flash memory as well as HSI 16 are configurable. They can be stopped or kept enabled. Stop-one mode is very similar to stop-zero except that the power figures are much lower as the main regulator is stopped and replaced by the low power regulator. The stop-one mode consumption without RTC is 1.3 microamps typical at 3 volts when flash is not powered and RTC is disabled. The wake-up time is 5 microseconds with the HSI 16 megahertz as system clock at wake-up, regulator in range 1 or 2. Flash memory as well as HSI 16 are configurable. They can be stopped or kept enabled. When comparing stop modes, stop-zero mode consumption is higher than stop-one mode consumption but the wake-up time is shorter and the number of active peripherals is higher. Stop-zero mode keep the main regulator enabled allowing a very short wake-up time of 2 microseconds when restarting from the RAM to the expense of a higher consumption than stop-one. The I2C address recognition is functional in both stop modes and can generate a wake-up event in case of an address match. The UART and LPUART byte reception is functional in both stop modes and can generate a wake-up event in case of start detection or byte reception or address match event when clocked by the internal or external low-speed oscillator or when clocked by an external pin, the low-power timer can wake up the MCU with all its events. The standby mode is the lowest power mode in which 36 kilobytes of SRAM can be retained. The automatic switch from VDD to VBAT is supported and the IOS level can be configured by independent pull-up and pull-down circuitry. By default, the voltage regulators are in power down mode and the SRAM contents and peripherals registers are lost. The 20-byte backup registers are always retained. The ultra-low-power brownout reset called BOR is available in standby mode. The power down reset is always on to ensure a safe reset regardless of the VDD slope. Each IO can be configured with or without a pull-up or pull-down which is applied and released thanks to the APC control bit. This allows to control the input state of external components even during standby mode. Five wake-up pins are available to wake up the device from standby mode. The polarity of each of the five wake-up pins is configurable. The wake-up clock is HSI with a frequency of 16 MHz. In standby mode with SRAM, the main regulator is powered down and the low-power regulator supplies the SRAM to preserve its content. The RTC, clocked by the internal or external low-speed oscillator, may remain active. The brownout reset can be enabled. The independent watchdog can also be enabled in standby mode. Reset, brownout or power down reset, RTC and tamper detection. Independent watchdog and any event on the five wake-up pins can exit the MCU from standby mode. The standby mode with SRAM consumption without the RTC is around 330 nanoamps, typical at 3 volts. The wake-up time is approximately 15 microseconds. In standby mode without SRAM retention, both main and low-power regulators are powered down. Wake-up events and available peripherals, as well as wake-up sources, are the same as in standby mode with SRAM. The shutdown mode is the lowest power mode of the STM32G0 with only 40 nanoamps at 3.0 volts. This mode is similar to standby mode, but without any power monitoring. The power down reset is disabled and the switch to VBAT is not supported in shutdown mode. Hence the product state is not guaranteed in case the power supply is lowered below 1.6 volts. The LSI is not available and consequently the independent watchdog is also not available. A power reset is generated when the device exits shutdown mode. All registers are reset except for those in backup domain and a reset signal is generated on the pad. The 20-byte backup registers are retained in shutdown mode. The wake-up sources are the five wake-up pins and the RTC events including tampers. When exiting shutdown mode, the wake-up clock is HSI at 16 MHz. In shutdown mode, the main regulator and the low-power regulator are powered down. The RTC, clocked by the external low-speed oscillator, can remain active. The brown-out reset is deactivated. Only the external low-speed clock can be enabled. The wake-up events are the RTC and tamper event, the reset and the five wake-up pins. The shutdown consumption without RTC is around 40 nanoamps, typical at 3 volts. The wake-up time is typically 250 microseconds. Here you can see the summary of all the STM32G0 power modes. The minimum output of PLL is 3.09 MHz. Thus, it cannot be used in LP run mode, where the maximum frequency is 2 MHz. From run mode, it's possible to access all low-power modes except low-power sleep mode. In order to enter low-power sleep mode, it's required to move first to low-power run mode and execute a wait-for-interrupt or wait-for-event instruction while the regulator is the low-power regulator. On the other hand, when exiting low-power sleep mode, the STM32G0 is in low-power run mode. When the device is in low-power run mode, it's possible to transition to all low-power modes except sleep and stop-zero modes. Stop-zero mode can only be entered from run mode. If the device enters stop-one mode from low-power run mode, it will exit in low-power run mode. If the device enters stand-by or shut-down, it will exit in run mode. The backup domain allows to keep the RTC functional and to preserve the backup registers in case the VDD supply is down thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low-speed external oscillator at 32.768 kHz. Two tamper pins are functional in VBAT mode and will erase the 20-byte backup registers also included in the VBAT domain in case of intrusion detection. The backup domain also contains the RTC clock control logic. In case VDD drops below a certain threshold, the backup domain power supply automatically switches to VBAT. When VDD is back to normal, the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the backup battery level. When VDD is present, the battery connected to VBAT can be charged from the VDD supply. The battery charging feature allows to charge a supercap connected to VBAT pin through internal resistor when VDD supply is present. The charging is enabled by software and is done either through a 5 kilo ohms or 1.5 kilo ohms resistor, depending on software. Battery charging is automatically disabled in VBAT mode. PWR-CR4-VBE enables battery charging. PWR-CR4-VBRS selects the resistance value. During the startup phase, if VDD is established in less than T-reset tempo and VDD greater than VBAT plus 0.6 volt, the current may be injected into VBAT through an internal diode connected between VDD and the power switch VBAT. If the power supply or battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. In VBAT mode, the main regulator and the low-power regulator are powered down. The RTC and TAMPA, clocked by the external low-speed oscillator, can remain active. Only the external low-speed clock can be enabled. The only powered block is the backup domain that includes RTC and TAMPAs, and the return to normal execution happens once VDD supply is provided. The VBAT consumption with RTC is around 450 nanoamps, typical at 3 volts. Three-bit option bytes to prohibit a given low-power mode. When cleared, a reset is generated instead of entering the related low-power modes. The microcontroller integrates special means to allow the user to debug software in low-power modes. Two bits are available in the debug control register in order to allow debugging in stop, standby and shutdown modes. When the related bit is set, the regulator is kept on in standby and shutdown modes, and the H-clock and F-clock clocks are provided by an internal RC oscillator. This maintains the connection with the debugger during the low-power modes and continues debugging after wake-up. Remember to clear these bits when the microcontroller is not under debug, because the consumption is increased in low-power modes. In addition to this training, you can refer to the reset and clock control interrupts trainings, as well as those for all the peripherals with wake-up from stop capability.