 FET biasing and current sources. As far as FET biasing is concerned if we consider an N channel device the circuit is the same whether it is a JFET or a MOSFET even if it is a MOSFET it could be either depletion type or enhancement type the circuit is the same. So if we consider an FET as having 3 terminals gate, drain and source the symbol is different for different types of FET but we are considering an N channel then we have to have a resistance R sub D and this goes to a source of voltage VDD note the change of symbols the drain instead of the collector so R D and VDD and the current through R D is I sub D and then the gate biasing is done in exactly the same manner as we do the base biasing in a JF in a BJT that is we use 2 resistances R 1 and R 2 and at the source we use another resistance exactly like the meter resistance and to distinguish this from the source resistance signal source resistance okay you know the signal source would be here and this usually we call RS and this is the signal source VS in order to distinguish between RS the source internal resistance and the resistance connected to the source terminal of the FET we denote this by R sigma alright you understand the meaning of the subscript sigma this is just to distinguish between this resistance and this resistance of course the output is taken from the collector not collector the drain and there is a resistance R L across which the signal output is taken okay now unlike alright let me recall the symbols if it is a JFET if it is a JFET then the symbol would have been simply this N channel JFET if it is an MOS FET of the depletion type permit of the depletion type 2 lines and we have a drain this is the connection on the other hand this is the depletion type MOS FET I bring this here de MOS FET on the other hand if this is an enhancement type then you have 3 lines like this this is the drain this is the source and this is the gate okay in either of these 3 in any of these 3 devices the same circuit shall be effective now you notice that the difference between BJT and FET is that the gate is virtually insulated if it is MOS it is DC insulated absolutely metal oxides in the conductivity it is a capacitor basically the gate does not take any current gate does not take any current all that in MOSFET in JFET the gate and source is a reverse biased junction the gate and source is a reverse biased junction therefore that also takes negligible current in other words the gate current I sub G can be taken to be 0 the gate current I sub G can be taken to be 0 so the FET basically and you know the gate controls the current I sub D the gate to source voltage controls the current I sub D so FET basically is a voltage control device all right you also notice that as far as DC is concerned the voltage at the gate is simply V G G equal to V D D R 2 divided by R 1 plus R 2 agreed so this is the equivalent of V BB agreed equivalent of V BB in a BJT all right and the equivalent of the resistance R B would be the parallel combination of R 1 and R 2 all right but it does not go as in a BJT it does not go to a diode it goes to an open circuit all right and I sub D is the I sub D is the drain current let us let us look at the DC equivalent circuit of this we have a battery V G G V G G then we have the resistance R sub G which we have already defined this is the gate terminal and this remains open all right at the at the other terminal we have what do we have a V D B in series with a resistance of R sub D and a what where does R sub D go isn't there a current source there is a current source which is I sub D we are considering the DC equivalent circuit is a current source I sub D then this goes to what is this terminal no the drain terminal is here this is the source terminal and therefore from here we have the current R the resistance R signal to the ground okay this is the equivalent circuit tell me what is the which is the drain just before the current source that is correct this is the drain terminal there will be a resistance of the N channel resistance of the N channel well we will come to this later yes there is a resistance we will come to this later this is that R D which we shall consider for dynamic resistance small R subscript small D that is D I D V D S D I D what is talking of the is this the dynamic resistance this we shall consider the AC equivalent circuit as well DC is concerned we do not have to okay now you notice that here the controlling voltage is V G S V G S that is this voltage this is the controlling voltage and you notice that this is since the gate current is 0 this is equal to V G G minus the source voltage is I sub D R sigma is that clear this is the golden relationship that we shall have to exploit now let us review a little bit about what we learnt about the different kinds of FET let us review the relationship then we shall go to this relation and see how to exploit this you know that the drain current in an FET is given by if it is a junction type is given by I D SS 1 minus V G S divided by V P whole squared provided V D S is greater than V G S minus V P where V P is a pinch of voltage okay for an N channel J FET V P is usually a negative quantity V P typically is let us say minus 3 volts and your V G S the gate to source voltage has to be less negative than 3 volts in order for the transistor to conduct in other words if you remember the characteristics characteristics are exactly similar to V G T characteristics except that there is a slope here there is a slope here and the characteristics are like this okay and this line is given by V D S is equal to V G S minus V P this line okay and before this line the characteristic is like this it is the oblique region it is the oblique region okay and this if this is for V G S equal to 0 alright then this voltage this voltage this is minus V P alright because this line is V G S equal to V G S minus V P alright so the the flat portion of the characteristic is the saturation characteristic the current reaches saturation there and this current for V G S equal to 0 is obviously I D SS the drain current under saturation condition and this is I D that is right that is correct the FET must be operated in the saturation it is there that you can explore the characteristics for a linear amplification and as you go down V G S becomes negative let us say minus may be 1 minus 1.5 this may be minus 2 these are not to scale and what is this line corresponds to V G S equal to not minus V P simply V P so this is the cut off line this is the cut off line and these are the saturation characteristics okay let us make them to scale may be this minus 3 in this case V P is approximately minus 4 volt okay you cannot go beyond this on the other hand if the transistor if the FET is an MOS type MOS depletion type okay if it is MOS depletion then the characteristics are written like some constant K multiplied by V G S minus V T square again V D S must be greater than V G S minus V T otherwise it is 0 otherwise it is the only region okay and V T if it is depletion then V T is indeed a pinch of voltage and V T is a small negative quantity okay it is a small negative quantity on the other hand if it is MOS enhancement type then the same relationship holds that V T is now a threshold voltage threshold voltage and has a slightly positive value V T is greater than 0 for conduction V G S now mind this carefully small V G S in an enhancement type E MOS FET enhancement in MOS FET V G S has to be more positive than V T alright if the two characteristics are drawn on the same graph that is a plot of I C D versus V G S then for the depletion type for the depletion type FET that is D MOS FET or J FET both of N channel the characteristic would be like this this is the transfer characteristic that is a plot of the current I C D versus V G S if you plot this obviously this will be a parabola a square law characteristic and the characteristic when it starts it would start from V P again or V T if it is D MOS and this is a negative voltage so this is somewhere here V P or V T and as the voltage exceeds V P that is when the voltage becomes less negative then V P the current rises and goes like this it is a square law characteristic now what is this current I D S S why because here V G S is equal to 0 okay on the other hand if it is an enhancement type MOS FET then V T is a small positive voltage V T and the characteristic goes like this it is a parabolic characteristic alright you notice also that in the biasing circuit our V we are considering DC alright we can take the voltage there is no problem V G S was equal to V G G minus R sigma I D right this is the condition this is the expression given the gate to source voltage as a function of V G G and I C D drain current and you notice that this line this straight line can be drawn this characteristic I D versus V G S it is exactly the same as the load line and it will start it will start at V G G and this current would be V G G by R sigma is that okay so take these two points and draw the load line this is the load line transfer load line this is not this our load voltage is in current at the same power of terminals okay the voltage is between gate and source and the current is in the drain a third power of third terminal and therefore this is a transfer characteristic this picture is worth 1000 words it takes J FET D MOSFET E MOSFET it shows the load line it shows the operating point where is the operating point now this is the operating point if it is E MOSFET and this is the operating point if it is D MOSFET or J FET alright and therefore the Q point the Q point can be calculated graphically alright or it could also be done analytically let us look at how to do it analytically yes what does the load line physically mean what does it indicate or it is the locus of variation of a current and the voltage in this case the load line is the locus of variation of a drain current and the gate to source that is if the gate to source voltage varies then your characteristic your current variation must lie on this line that is what it is okay now if I want to do it analytically you have seen how to do it graphically if I want to do it analytically let us let us for example consider for specific a specific case then the J FET it will be J FET N channel J FET then I sub D is equal to I DSS V GS minus V P whole square no it is written differently 1 oh let me write it again I DSS 1 minus V GS divided by V P whole square I want to find the DC drain current okay DC drain current and I know then of course I sub D under the DC conditions it is I DSS 1 minus V GS by V P whole square in this you substitute the value of V GS so it becomes I DSS 1 minus what is V GS V GS is V G G minus I sub D R sigma divided by V P whole square and you see that the right hand side contains the unknown the left hand side of course is the unknown and therefore it is what kind of equation it is a simple quadratic equation which can be solved for I sub D quadratic equation has 2 roots by the fundamental theorem of equations one of them would be acceptable the other would not be acceptable. Now what would be the logic for rejecting one of the solution I should be positive suppose both are positive one of them one of them will violate the condition that V DS is greater than V GS minus V P so the one that satisfies this the one that satisfies the relationship V DS greater than V GS minus V P is the solution to be taken and there will be a large number of examples that will work out in the tutorial class and also I will work out some in the Thursday class okay so you can either do it graphically or analytically and it turns out that analytically it is not very difficult so why why turn to a graph and draw a graph and be an equate an object okay. Now with this out of the way let us look at the AC equivalent circuit because the AC mode line requires a knowledge of the AC equivalent circuit let us take the same circuit as far as AC is concerned we shall have the AC S R S the capacitor will become a short and R 1 and R 2 they will combine into a single resistance R G which would be from the gate to ground is that correct R 2 will come in parallel with R 1 because V D B is basically AC short then in the collect in the drain circuit between the drain and the source we shall have a current generator current generator which is the incremental current generator okay incremental current generator which will which will find out that that current generator shall feed an R sigma you cannot wish this away unless R sigma is short circuited alright this capacitor we did not use earlier now we bring in this capacitor C 3 R sigma short circuited and this current generator incremental current generator will feed R D and R L C 3 will be short C 2 will be short so R D in parallel with R L now let us look at this circuit then we will explain further what we have is AC equivalent circuit AC equivalent circuit V S will come in series with R S this is the source resistance then we have R G which is the parallel combination of R 1 and R 2 this is your gate and then you have a current generator we will see what this current generator is in the BJT case is a beta it was beta small i subscript small b okay let us see what this is here we will see in a minute but what this feeds is a parallel combination of this is R L prime where R L prime is R L parallel R sub D the drain resistance and this is the this is the output voltage V 0 now to determine what this current generator is you recall the total drain current is given by I DSS 1 minus V GS divided by V P whole squared okay you recall this now what you have to do is to take the AC part of this AC part of this obviously what we can do is take D I D D V GS okay what would be the what would be the dimension of this it is a conductance it is a conductance it should be denoted by G it is a dynamic conductance it should be denoted by small g and because it relates a current in one terminal to the voltage across another two terminals it is a transfer conductance of a trans conductance and if you differentiate this you can easily see that this is given by minus 2 I DSS divided by V P multiplied by 1 minus V GS divided by V P note that I have shifted to capital V GS why because this is to be evaluated at the Q point at the Q point at the Q point the voltage is V GS now therefore therefore what I have is D I D D V GS I have found out a GM this can be found for MIS FET the expression will be slightly different but notice that D I D is the increment in the total current so D I D can be replaced by small I subscript small D and this is equal to GM times D V GS is the increment in the gate to source voltage so small b small v subscript small g small s therefore the current generator that you see here shall be GM times small v GS this is the AC equivalent circuit okay and you can make simple calculation of the game V 0 by V s very easy right what is V GS where is the source now this is the drain where is the source obviously this terminal is the source why does the source come here because R sigma is grounded R sigma is short circuited for AC how is the source GM this is what I explained here D I D D V GS D I D is the increment in drain current so it is I subscript small d and D V GS is the increment in the gate to source voltage so this is V GS okay so you can calculate the game very easily you can see that small V GS which is the voltage between these two terminals is simply V s R G by R G plus R s and V 0 would be minus GM V GS multiplied by R L prime and therefore it is a very simple matter of calculation to find out what the game is you remember in the case of the BGT we had an alternative circuit in which RE was made equal to 0 alright but there is a feedback from the collector to the base can you do the same with respect to FET let us draw this we have a V s R s capacitance then we have D FET for reasons to be explained in a minute we show an enhancement type FET E MOSFET enhancement type NOS FET okay I will explain this in a minute why I am not drawing any other R s is R sigma is 0 so it goes to ground the drain the drain terminal goes 2 plus V DD okay and the biasing if I take the same type of circuit the biasing would be applied through a resistance what shall I call this resistance R G R capital G in the previous case we had called it R capital B now this is a perfectly good way of biasing your output comes from here C 2 and this is R L this is V 0 this is a perfectly good biasing provided it is an enhancement MOS FET you cannot replace this FET by a J FET or a D MOS FET and the reason is very simple what is the reason for enhancement MOS FET V G S has to be positive on the other hand if it is a depletion mode operation either a J FET or MOS FET your V G S is required to be negative this circuit cannot give you V G S equal to negative unless unless there is a resistance here if there is a resistance here then V G could be less than V S but here V S is 0 identically therefore this is one of the differences between FET and V GT that this circuit is specific to E MOS FET and is a popular circuit never made the mistake of having a biasing circuit for depletion mode with a circuit like this what is the advantage of this kind of a biasing the advantage I already told you it uses one resistance less the if you recall instead of V BB V BB was replaced by V C C and therefore wherever V BE occurs V BE is much less compared to V C C then V BB it is a more stable circuit than the previous one okay and however there is a problem of AC feedback that is AC signal signal current may flow through R G into the into the drain directly for which the solution is that you break R G into 2 parts R G 1 and R G 2 and bypass by means of a third capacitor so you do not really save a resistor okay you do not really save a capacitor also you have to use this you have a 2 more 2 more components you do not really save but this is a good enough circuit there is some reason the source has to be grounded then this is the solution provided the FET is an enhancement mode MOS FET as far as the effect of temperature is concerned IDSS and GN both of them decrease with rise of temperature can anyone explain why it is so with rise of temperature why IDSS and GN decrease because which resistance it is not the resistance okay that is a that is a that is a gross exclamation but what happens is the temperature increase the mobility decreases because they go on colliding with each other they acquire more energy they do not know how to dissipate the energy so they fight each other okay I hope this is not happening it is human beings okay. Is there the same tension but here those increase are from different people. Carriers if you say in channel then therefore you are you should drive the device to its limit as much as it can as the telephone so that is not that is marginal that the energy of the increased thermal energy it causes carriers to fight each other they cannot recombine with anybody so they fight each other they are of the same quality and the mobility is decreased it is also true that VP the pinch of voltage increases with temperature increase pinch of voltage increases but this effect is not very significant it is insignificant increase okay. This takes us to have a look at a completely different type of biasing which is to be used in integrated circuits ICS in integrated circuits the biasing that we have we have discussed so far either BJT or FET cannot be used because in integrated circuits there is a limit on the volume there is a limit on the area of silicon that can be used so in integrated circuits the main guiding principles are in making an integrated circuit or in biasing main guiding principles are that use transistors as many as possible to replace any other function for example a diode you do not make a diode separately use a transistor connect what? Base collector short that is the base diode in fact base collector short and the emitter is the other terminal okay you can make a diode can be made from a transistor in I think 6 different ways of which the best is the one did you know this or you just guessed you know it okay alright so whatever the function is whether it is a diode or a resistance even a resistance use an FET between the drain and the source keep the gate open does not matter use this as a resistance you understand what I mean? So use as use transistors why because resistors are more costly diodes are more costly than transistors I will tell you I will tell you why you see in an integrated circuit every stage of application diffusion oxidation masking every step has to be very precisely controlled and when you make a transistor let us say 2 and 222 or whatever the type is if you want to change it to make a diode it costs a huge lot of money because the whole process has to be stopped reconfigured and then carried out so it costs money in terms of materials in terms of the utility of the equipment alright so one standardizes one process in a particular setup let us say Motorola they only make transistors they will not make anything else unless they are forced to and this transistor you can make millions in one of the one chip okay in one of the waifers you can make a million transistors there is no problem VLSI with appropriate design so use transistors as far as possible as far as possible if resistors are to be fabricated then use the minimum number okay as few as possible use the minimum number of resistors of as small a value as possible of as small a value as possible why is this so the larger the value of the resistance the more is the area of the waifers area of the of silicon current is our choice current is our choice we will make we will reduce the current we will reduce the current you see for amplification the absolute level of current in voltage are not important as long as you put the q point in the appropriate operating point and the dynamism and the dynamics of the whole situation is such that the dynamic range is not exceeded that is you don't going to cut off half power dissipation or saturation or whatever it is then you are perfectly same so current is in our control and in integrated circuit the one of the guiding principles is use as little current as possible so that you don't have to provide for heat dissipation heat is a minutes it can it can cause havoc so current is our choice use the minimum number of hours or as small as small as possible as far as practicable do not use capacitances as far as practicable do not use capacitances because capacitances also are very costly they use they use a large semiconductor area silicon area capacitance is directly proportional to the area not only that if you want to make a large capacitance the thickness the separation between the 2 plates has to be made very small which means the insulation strength of the capacitance will be very small alright so do not use capacitances unless you are first to if you have to use a capacitance use a MOSFET in a MOSFET there is already a capacitance between the gate and the channel so use gate to source or gate to drain as a capacitance instead of a transistor or use a reverse biased junction a reverse biased junction acts as a capacitance alright so this is what I said use transistors as far as possible if you have to make a capacitance of the pure kind a parallel plate well then it is going to be costly you try to avoid it as much as possible if you are forced to then of course there is no choice alright and the 4th guiding principle is inductors forget about them you cannot make inductors in integrated circuits because there is a basic limitation a fundamental limitation the amount of flux that can be contained in a small volume of dimensions microns the amount of flux that can be contained is very very small unless the magnetic permeability or the magnetic field that is causing the flux is of astronomical magnitude naturally you cannot have it in the laboratory and you cannot have inductors unless you go to frequencies greater than 10 megahertz let us say if the frequency is very high very small piece of spiral for example will act as an inductor good inductor you require very small inductors nano Henry order and you can make it by depositing a conducting spiral for example or there are many other many other geometries you can make a loop like this and this is one of the terminals this is the other term okay but this is at extreme high frequencies now therefore if we have to be guided by this in integrated circuits we cannot use that cell bias VJT with 4 resistors or FET with 7 resistors we cannot make them so you have to think of something else and this is done by what are known as current mirrors current mirrors in a current mirror not only you see if you have a if you have a VJT what you have to do is to stabilize I sub C and VCE this is the basic problem okay and if I sub C is stabilized then VCE is also stabilized because VCE is VCC minus the drop in the collector resistance minus the drop in the collector resistance okay so basically our problem is to stabilize I sub C and what is the stabilization I sub C has to be stabilized against variations of beta VBE and ICBO alright one of the simple things in a current mirror the basic principle is that you make I sub C in a particular transistor independent of the parameters of that transistor that is you make a reflected I am using a sexperian term reflected glory what you do is I sub C is controlled by another circuit okay another circuit and therefore I sub C will make independent of the particular transistor in which it is flowing this is why it is called a mirror mirror is what you see here is a reflection as I said reflected glory is a reflection of what happens in another circuit alright let us see how this is performed this is the significance of the term mirror there is nothing else nothing else it is a reflection that means purpose is to stabilize I sub C if I sub C is independent of the parameters of this transistor naturally it is stabilized okay okay that we will see that we will see we will make that transistor under very controlled conditions so one transistor one spot in the circuit will control stable collector currents in many other transistors okay let us see how this is done we recall this circuit for BJT biasing we have an R sub C then the meter goes to ground and there is a base resistance R sub B we recall this biasing in this biasing in this biasing where there is a feedback that R base pleat and all that is a different story that only affects the AC signal part not the DC okay now in this circuit I had told you the delta IC by IC 1 that is the percentage change in the collector current is given by delta beta by beta 1 let us recollect R B divided by R B plus beta 2 instead of R E we shall have R sub C that is the only change R E is changed to R sub C and V B B is changed to V C C then due to V B E change it is delta V B E divided by V C C minus V B E plus delta IC B O do not forget this negative sign delta IC B O R B plus instead of R E it is R C divided by V C C minus V B E all right we also recall in the specific calculation that we have made that this the beta variations accounted for the major change in I sub C it was 9.2 in the particular example that we took this was of the order of 4.6 or something about half and this was of the order of 0.66 percent so major variation occurs due to beta and if I can make that 0 then obviously I will improve matters and making it 0 simply means make R B equal to 0 so if I use this circuit R sub C let us see what happens this goes to ground and instead of a resistance we simply use this okay then what is V C E well this goes to 0 alright and therefore the I sub C is stabilized to a degree greater than when R B was there alright but what happens to V C E now for this transistor isn't it the same as V B E V C E is the same as V B E is it a diode basically it is basically a diode a transistor is being operated as a diode now V B E in the active region as we know is about 0.7 volt is the transistor then in the active region 1 is greater than 0.2 so it is very close to saturation but in the active region we will not require this transistor to amplify what we will do is we will use this current as the reference current we will use this current as the reference current so we shall call this we shall call we shall change the momentum pressure a little bit we shall call this as the reference current and we shall call this resistance as R 1 then you see I ref is simply V C C minus V B E divided by R 1 correct I ref is V C C minus V B E divided by R 1 agreed now this is our reference current how can this change why should this current change the current can change if there is a change in V B E obviously the current can also change if there is a change in I C B E but as you know the changes in V B E and I C B E are much less as compared to the change in beta and therefore if this transistor goes bad and you replace it by another transistor nothing happens because it may be made independent of beta this is the basic point alright now this transistor as a reference is used to control the current collector current of another transistor and the connections are made like this this is plus V C C there is a resistance R 1 then you have you have this connection call this transistor as Q 1 then it goes here this base is then connected to another transistor the current of which has to be controlled or stabilized the operating point of which has to be stabilized let us call this I C 2 let us call it as output current and let us call this voltage as V 0 okay this voltage is V 0 I am sorry that is the V C E of Q 2 this may be connected to a load we are not shown that part of the circuit we are showing only the DC collector current now this goes to the same point the emitters are tied together they collect the bases are tied together okay and this goes to it may go to ground but in integrated circuits usually integrated circuits are operated with a plus minus supply which helps in stabilizing operating point and in getting many other kinds of functions then is possible with only one supply so it goes to minus V E E this goes to a negative supply usual supplies are let us say plus minus 12 V C C may be plus 12 then V E is minus 12 the ground is the middle point of the supply okay right now this is a typical current mirror arrangement why is it called the current mirror because as we shall show I 0 is approximately equal to I R or I reference reference I do not want to write I E of every time I will simply say I R okay now you know that the collector current of a transistor collector current of a transistor is approximately equal to the emitter current actually it is alpha times I E plus I C B O okay alpha times I E plus I C B O I C B O can be ignored and therefore it is alpha times I E and alpha is approximately 1 and therefore the collector current is approximately equal to emitter current and emitter current is a diode current and therefore it is of the form I S particularly when it is forward biased it is I S exponential Q V D E let us use capital divided by K T agreed now therefore the collector current of a transistor depends basically on the base to emitter voltage and since the 2 base to emitter voltages of Q 1 and Q 2 are identical they are identical the collector currents I C 2 and I C 1 should be identical alright so the first thing that you notice is that the output current that you want I 0 is equal to I C 1 alright how is I C 1 related to I R as you say I R equal to I C 1 okay I C 1 then there is a base current here there is a base current here the 2 base current shall be identical because V D E is the same alright and these 2 base currents must come from here therefore this is equal to twice I B 1 plus I B 2 or twice I B which is I C divided by beta so twice I C 1 divided by beta therefore my relationship becomes I C 1 1 plus 2 by beta and if beta is much greater than 2 which is usually the picture if beta is 100 within 1 by 50.02 2 percent change then I R is approximately equal to I C 1 I C 1 is the collector current of the transistor Q 1 I indicated this this is I C 1 collector current of Q 1 which means that the output current I 0 is approximately equal to I sub R the output current is approximately equal to I sub R which for this one okay I will explain this first I R is I C 1 that is the current through the collector plus this current by K C L this current must be equal to the base current of Q 1 plus the base current of Q 2 and these 2 currents must be identical so twice I B and I B is I C over beta is it clear okay and therefore I 0 is equal to I R and what is I R now what is the reference current here it is V C C minus V E E so it will be V C C plus V E E minus V B E divided by R 1 okay so this is V C C plus V E E minus V B E divided by R 1 now V B E strictly should be replaced by K T by Q log of Y because this is a collector current and it is I S e to the power Q V B E by K T so it should be replaced by L M I sub 0 divided by I S is it okay V E because I 0 equal to S e to the power Q V B E by K T therefore V B E should be replaced by this quantity if I do that then what kind of equation do I get I get a transcendental equation and I do not want to solve the transcendental equation so what is the way out way out is engineering common sense common sense it is said is the strongest tool of an engineer and here you see V B E would be a small quantity compared to V C C plus V E E in integrated circuits invariably there is a positive supply and a negative supply therefore this would be of the order of let us say 24 and V B E we want the transistor to be in the active region so active region is approximately 0.7 therefore this is a negligible quantity and instead of solving a transcendental equation I replace this by 0.7 and I get a fairly good fairly good working relationship design relationship for a current mirror therefore the resistance R 1 that I need is V C C plus V E E minus 0.7 divided by whatever current I need okay I C 2 which is approximately equal to I reference alright which is approximately equal to I reference for example if I want let us say 500 micro ampere and V C C and V E E both are 15 volt let us say plus minus 15 then R 1 comes out as 30 minus 0.7 which is 29.3 divided by 500 micro ampere and this comes out as 58.6 K alas this is a large value sir sir in the expression for IR you are ignoring 2 by beta 1 plus 2 by beta if you are supplying many different circuits like you said you are supplying 10 or more then you cannot ignore that case wonderful then we will have to have super bitters if I want to supply 10 of these circuits then obviously if I want to supply 10 transistors from the reference current if I want to supply the base current of 10 transistors from the reference current then obviously these 2 shall be replaced by 11 11 11 11 why 11 because the reference transistor also supplies a base current okay so it will be 11 therefore beta must be much larger compared to 11 and as I said if I want if I use a dilumten that is another thing that is used in ICs invariably instead of 1 transistor you use 2 transistors let me show you this what you do actually is this the collectors are brought together and this is the emitter this is the base this is the collector there is a composite connection so if I supply an ICB here signal current this current is approximately beta IB and this current would be approximately beta squared IB so if I have a beta of 50 I can get a beta of 2500 without any problem your question is quite valid if my current leader has to supply a large number of transistor then the current leader must be made of a dilumten