 In the last lecture, we had looked at the derivation of sub-threshold slope and also understood the importance of sub-threshold slope on controlling the leakage current and we noticed how leakage current has increased over technology generations. So, in this lecture, we will continue the discussion a little bit you know just to understand what are the factors controlling the sub-threshold slope. If you recall, we had this expression for sub-threshold slope which was given by this expression and this is in terms of millivolts per decade. That is essentially the you know voltage required to decrease the current by 1 decade below threshold voltage. So, if you notice a couple of things that become very apparent you know if C d is high then sub-threshold slope becomes worse. Remember that this number should be as small as possible. The best you can achieve is 60 millivolts per decade at room temperature that is when you can ignore C d by C ox compared to unity. Otherwise, it is always more than 60 millivolts per decade at 300 degree Kelvin. So, you know C d in turn depends on the substrate doping in particular you know you may recall that substrate doping. If substrate doping increases C d will essentially depend on substrate doping increase in substrate doping increases C d simply because increase in substrate doping would reduce depletion width as you could imagine and reduce depletion width essentially results in increased depletion capacitance. So, depletion capacitance increases as substrate doping increases. So, you know this is certainly one of the concern increasing the substrate doping is detrimental in getting lower sub-threshold slope. Now, if you look at C ox right in this case increasing C ox is good because increasing C ox will make the sub-threshold slope lower. So, here this is not good for sub-threshold slope and this is good for sub-threshold slope. So, how do you increase C ox you can make use of oxide thickness as the parameter. So, in other words if you decrease oxide thickness as you can well imagine C ox being inversely proportional to the oxide thickness decreasing oxide thickness will help you increase the oxide capacitance which will in turn help you reduce this term and enhance the sub-threshold slope which is also good right. So, the scaling you know as you remember indicates that oxide thickness has to decrease doping concentration has to increase as indicated by constant electric field scaling theory. So, out of the two one is favorable for sub-threshold slope, but the other one is not favorable for sub-threshold slope right. So, this is something you need to remember and in fact as we will see subsequently maybe in the next lecture that is why we do what is called channel engineering in order to make sure that we get the best of both world meaning we certainly get the benefit by having decrease T ox, but even if you are increasing substrate doping we do that intelligently. So, that we do not necessarily suffer very much in terms of sub-threshold slope. Now, so what else you know could you do in order to reduce the sub-threshold slope right. Now, you see C ox if you look at that of course, increasing you know C ox is helpful, but can you make CD 0 right, but obviously not with the conventional bulk so called bulk silicon technology because bulk silicon technology as we have already seen there is going to be certain depletion width which is governed by you know the doping concentration and that will determine your depletion capacitance. But there is you know a variant of a technology which we sometimes call SOI technology we will have a lot of discussion on this SOI technology subsequently in one of the you know future lectures this essentially stands for you know silicon on insulator. In fact, one of the biggest advantage of the SOI technology is that you can really achieve 60 millivolt per decade sub-threshold slope and you can do that by really minimizing CD I mean of course, you can never make it 0, but you know in the limit it tends to very very small value right. The way you do that in silicon on insulator technology is you know essentially you make these junctions remember we have the source and drain junctions in MOS transistor. You have a very thin silicon film and you make the source and drain junction on this silicon film and this silicon film is really sitting on a thick silicon oxide this is very large right. So, the fact that you have done this you know now your depletion width rather the capacitance which is going to be governed by depletion width is really you know this insulator thickness. If you have a very large insulator thickness you can have a very very low capacitance. So, this is what one does in silicon on insulator technology and tries to make sure that CD is brought down as low as possible. This is happening because of this oxide thickness sometimes we call this as a buried oxide thickness just to distinguish this from the gate oxide thickness right. Typically, when we write T ox you know that T ox corresponds to a ultra thin oxide that is up here right in a MOS transistor right. This is this T ox that we are referring to whereas, this T ox is you know something that is sitting underneath the channel and of course, there is also silicon underneath and that is why it is called silicon on insulator. It is as if you have interposed a thick insulator in a silicon substrate and this is one other thing that you could do and in fact, you would have more discussion on this subsequently in one of the future lectures right. So, this is also very good for your decrease in sub threshold slope. Now, there is another way you can minimize CD which of course, just for completeness of discussion. However, it is not always possible and in fact, it may not make sense in most of the application that is using body bias. Remember the transistor is a four terminal device and if you may recall the speed type this is the body correct in a n channel transistor. Typically, you know when we talk of n channel transistor we say that body is at ground potential, but you can intentionally reverse bias this body you see by reverse biasing this body as you may remember from the basic MOS theory your threshold voltage increases when you apply a reverse body voltage. In fact, that is what is called body effect right. Body effect essentially means that your V t you know increases when you have V b which is essentially reverse bias. So, this is what happens as far as threshold voltage is concerned. However, you know first of all as soon as you apply reverse bias this depletion width also increases you see and an increase in depletion width is good for you in terms of decreasing depletion capacitance right. So, as a result of that you may expect that if you operate the transistor at different body biases you will see a variation in sub threshold slope. In particular at 0 body bias if you get a sub threshold slope of 100 millivolt per decade as you start increasing the body bias that 100 starts coming down you see 100 may come down to 95 millivolt per decade 90 millivolt per decade and so on and so forth depending on what is the exact body bias that you have applied. In other words if you were to look at your current voltage characteristics you have the drain current as a function of gate voltage right and as we have already seen if this is in a log scale you know your I d V g curve essentially looks something like this correct and this is your threshold voltage point V t point and this is a sub threshold region and this is governed by the sub threshold slope right this is the sub threshold slope let us say this is at V b is equal to 0. Now, if V b is a reverse bias non-zero voltage then what will happen is that two things will happen one is V t itself will increase as we know from the body bias basic phenomenon right. So, V t will increase so your new V t will be somewhere here you know this is V t prime under a non-zero body bias so that is one effect that you will certainly expect will happen and in addition to that what you will also see is that the sub threshold slope becomes steeper if this is your sub threshold slope under V b equal to 0 and this is V b equal to let us say 1 volt and this sub threshold slope let us say S 2 will be certainly less than S 1 where S 1 corresponds to your you know sub threshold slope in this condition right I mean as you can clearly see because C depletion has gone down that will decrease C d by C ox term and will decrease this sub threshold slope in other words the roll off is much steeper that is what we want however it has come at an expense right it has come at an expense which is increase threshold voltage right. So, the increase threshold voltage is not good for your on current because increase threshold voltage will decrease your on current right. So, although in practice you can decrease a sub threshold slope using this technique but you also suffer in terms of degraded on current right. So, this is not always the preferred technique to follow. One other technique you know again which is very hard to follow but there has been lot of research in what is called low temperature CMOS. Remember I said sub threshold is 60 times 1 plus C d by C ox but it is really 2.3 times K T over Q 1 plus C d by C ox correct and we said that K T over Q at room temperature which is 300 degree Kelvin is at 300 degree Kelvin right K T over Q is approximately 25.8 millivolt and you know multiplied with that bit 2.3 and that is how you get 60 as a number there but you see here this temperature K is constant Q is constant there is nothing you can do but you can decrease this temperature rather than operating the chip at room temperature or the typical commercial chips as you probably have seen from the spec sheet of these commercial chips they operate between minus 40 degree centigrade to 125 degree centigrade that is a typical operating region right and room temperature let us say 27 degrees you know would correspond to 300 degree Kelvin. But what if you operate the chip at liquid nitrogen temperature you know somehow you you know pump in liquid nitrogen and really cool it to 77 degree Kelvin right and you can immediately see that this T goes down from 300 to 77 and you would expect the sub threshold value to go down very dramatically right. So, in other words you know if you have let me go back to the same graph here right if you have you know a characteristic which would look like this at room temperature if this is at room temperature at low temperature you know you may actually see something like this this is low temperature contrast this with what we were doing in you know increasing the body bias. Notice that in fact at low temperature your V t value increases you know because there is an effect of band gap widening and that in turn results in increased V t. However that increased V t does not necessarily degrade your on current your on current may be actually better because you decrease the impurity I mean the lattice scattering because temperature is very low mobility enhancement takes place as a result of that you have very large on current much better on current at the same time because the sub threshold slope is steeper your off current also decreases right. So, this is best of both world you get best on current and best off current. So, if you can figure out a way to operate transistors at low temperature you know you know that is the greatest thing right, but we have not really figured out how to do that it is as if you know you will have to have a cooler with every chip that you build and the cooler itself may be huge right in order to cool the chip to the 77 degree Kelvin right, but that is something you may want to keep in mind that low temperature is certainly something that enhances your sub threshold slope meaning sub threshold performance the slope value decreases right this the slope is steeper, but the way we define sub threshold slope you know you should not get confused with this is inverse of the slope you see how many millivolt per decade change in current right and you know this will have a lower value of s if this s here is 100 millivolt per decade you know s here may be let us say 40 millivolt per decade or even lower in fact you can you know go down this 60 millivolt per decade limit. So, 60 millivolt per decade the so called Boltzmann limit right which essentially comes because of the fact that the carriers have to overcome the barrier to you know conduct current the Boltzmann limit value is different at different temperature because it depends on k t over q at low temperature it is much lower value and you know other than this low temperature of course is very nice, but of course again it is not really practical one of the you know biggest research that is happening in CMOS is really to achieve what are called sub 60 millivolt per decade transistors at room temperature. You see you know that is sort of what is called overcome the Boltzmann limit right ideally if you are building a transistor as usual at room temperature 60 millivolt is the best you can do right I mean that is dictated by Boltzmann statistics right. However you know there are variants of transistors that are being looked at for example you know there is something called tunnel fat t fat which stands for tunnel fat. Here the conduction is not necessarily overcoming the energy barrier whenever you have to overcome an energy barrier to conduct from source into the channel there is always a barrier you see it becomes very clear when we look at the next topic which is drain induced barrier lowering there is always this Boltzmann limit you cannot do anything better than that, but if you are tunneling from source into the channel you can do much better than the Boltzmann limit right. So, there is lot of work that is going on and there is similarly there are you know variants called based on Avalanche mechanism right Avalanche based FETs again these can help you to overcome that 60 millivolt per decade right. In other words you know in ideal transistor as you know should have as low value of sub threshold slope as possible right right ideally you would like to have a characteristics of ideas by VGS as some on current and instantaneously go to very low of current right and this is ideally 0 millivolt per decade if you can right right infinite small small value that you apply below threshold voltage current should drop instantaneously by several orders of magnitude that is the best transistor that you can have. So, these are some of the transistors that are being investigated right right we are nowhere near really you know mastering that technology yet, but this is something for you to keep in mind. So, this is you know just to give you an idea that sub threshold slope is a very important parameter in a transistor design and you have to try and do whatever you can to minimize the sub threshold slope there is different knobs that you can to tune when you are designing a transistor you make use of all that and you know design the best transistors that you can. So, let us look at another very important concept what is called induced barrier lowering this is abbreviated as D I B L double is what we say. So, let us look at this transistor N channel transistor and on a p type substrate you see there is a N plus p junction here and N plus p junction here. Now, if I were to draw the just the conduction band you know I am interested just look at the band diagram energy band diagram right I will focus only on the conduction band diagram let us say initially I have both source and drain at ground potential. So, then what you would expect is the following right this is the source and drain edge right you will have E C which would look like this and there is this is p type there is an energy barrier there right and again it will come down here right this is E C in N type region E C in N plus region and this is E C in P type region ok. These are very heavily doped almost degenerately doped right I mean if you were to sketch the full band diagram the full band diagram would have looked something like this your Fermi level would have been very close to conduction band right this is your E f when both terminals are 0 E f is flat there is no current flowing right your valence bands would have looked like this right correct this is N type Fermi level is very close to E C this is also N type very heavily doped Fermi level is very close to E C and this is P type and hence Fermi level is closer to valence band right of course not as close to E V as this is close to E C because this is not as heavily doped as these regions are right. So Fermi level is little bit away from the valence band right so I am not really interested in the valence band part right I am only interested in the conduction band part because I am interested to find out you know when would these electrons come into the channel and how would they flow into the drain right that essentially what constitutes your drain current the carrier flow electron flow from source to the drain terminal ok. So now let us look at a condition right this is when both source and drain are interchangeable now both are at same potential right it is a symmetric device they are at 0 voltage but now let us say I apply a non-zero voltage to the drain in a N channel transistor and let us see what happens let us consider two cases one where my channel length is long which let us say is 10 micrometer ok and let me see what happens here right this is let us say the source and drain edge just have that picture over there and you know what will happen is this is E c there is this barrier and what you have done at the drain side is you have applied a non-zero drain voltage right so as a result of that there is an extra depletion which is created right and you know accordingly you will have a band diagram which will look something like this ok this is E c on the drain side this is source this is channel and this is drain and you are E c on the drain side and E c on the source sides will be essentially separated by applied voltage you see that is how the two Fermi levels E c get separated because the Fermi level here is here and the Fermi level is out here applying a voltage in a system essentially you know moving the Fermi levels right since I have applied a positive voltage on the drain side I have moved the drain Fermi level below the source Fermi level ok and this is how the you know two Fermi levels will look and accordingly two conduction band will look and the difference between two Fermi levels or two conduction band levels is governed by applied voltage ok and accordingly since you have this applied voltage there is this more band bending because the reverse bias junction has higher junction potential now earlier that junction potential was essentially built in potential that built in potential is not impacted on the source side but that built in potential on the drain side has been augmented by the reverse voltage that you have applied right and hence you have made the barrier on the drain side much larger compared to the barrier on the source side ok. Now the important point to realize is that when I start applying larger and larger drain voltage this is V D increasing all I will be doing essentially for all practical purpose is essentially modulating only the band diagram at the drain side ok this is for V D 2 V D 2 and this is for V D 1 V D 1 and V D 2 both are greater than 0 V D 2 is greater than V D 1 ok V D 2 is greater than V D 1. So, whatever you are doing at the drain side that because the channel length is very long the distance from the drain to the source being very long this effect is not at all felt at the source side I mean source is far away from the drain anyway ok. So, any disturbance that is being caused in the electric field depletion weight everything happens at the drain edge ok nothing happens in the source side in other words this barrier from source to the channel this let me call it at 5 barrier remains unchanged in a long channel transistor irrespective of what drain voltage that you are applying the only way to modulate this barrier is by applying gate voltage when I apply a gate voltage I change the surface potential here and hence the barrier starts coming down you see that is how the conduction take place by applying a positive gate voltage this barrier would come down and there is more injection of electrons into the channel and as I start increasing the gate voltage there is more and more current flowing in. So, that is how you know this things are in a long channel transistor. So, let me just summarize that the source side barrier is unaffected by drain voltage. So, corollary of that is your conduction property of the channel or transistors are independent meaning the barrier here is independent of for what you do at the drain side. Now, let us look at what happens in a short channel transistor in a short channel transistor the source is very close to the drain let us say at 0 bias this is my barrier picture it is of course symmetric the drawing may not look symmetric right this is a source side and this corresponds to v d equal to 0 and v s of course is equal to 0. Now, if I start applying drain voltage which is more than 0 non zero drain voltage positive drain voltage because the channel length is so small the drain electric field can actually penetrate all the way to the source and in the limit as L starts going down further and further this electric field can couple to the source more and more efficiently. So, when I apply a non zero drain voltage you may have a condition where in the resultant barrier could look something like this this is v d non zero let us say v d is equal to 2 volt. So, when apply v d is equal to 2 volt not only of that the barrier at the drain has change, but also because it is effect is felt near the source it also modulates the source barrier you see if this happens you could imagine that there should be more conduction from source into the channel. In other words in a short channel device the drain influences source barrier and hence the source is very close to the drain it is called drain induced barrier lowering at the source. It is the drain voltage that is responsible for this and what does it do it reduces the barrier for conduction at the source side. So, that is what we mean by a drain induced barrier lowering. Typically this effect of drain induced barrier lowering is that your threshold voltage of the transistor would get affected based on what is the drain voltage that you have. In fact, the drain induced barrier lowering its immediate consequence is the following. If you were to plot v t versus l remember I had already told you in one of the earlier class that v t versus length would look something like this and this is what we called short channel effect. When your length starts decreasing your v t would also starts decreasing very significantly and this is flat at the long channel and it starts rolling off only at may be sub micron of course in nanometer regime it goes down very dramatically and this is a v t roll off. Now, when you do the v t measurement the way you do the v t measurement is that you apply a drain voltage and you ramp your gate voltage and you see when the transistor starts conducting. Typically threshold voltage of the transistor is independent of drain voltage. We do not say that v t is measured at this drain voltage or this drain voltage the transistor has 0.5 volt at 1 volt drain voltage you know we do not say that transistor has 1 volt v t that is it. In other words the classical theory again says that the transistor's threshold voltage is independent of drain voltage but that is no longer true in a short channel device. In a short channel device you will have to also specify at what voltage are you measuring threshold voltage are you measuring threshold voltage when v d is very small of the order of 100 milli volt or v d is large of the order of 1 volt or let us say v d is equal to 2 volt. Your threshold voltage value will be quite different and why is that and the reason precisely is because drain induced barrier lowering. Your conduction in the transistor is not only influenced by the gate voltage but it is also influenced by the drain voltage in a very short transistor and more specifically you can expect that if the drain voltage is larger and if you try to measure i d v g characteristics you would expect a lower threshold voltage because this drain has already lowered the barrier and you know you do not need to apply as much gate voltage to turn on the transistor. So, in other words if you were to specify threshold voltage especially at the you know very very short channel regime then depending on whether you have v d s is equal to 2 volt or v d s is equal to 0.1 volt you will see different threshold voltage. Again it does not happen in long channel regime in long channel regime whether you measure the threshold voltage at 100 milli volt or 2 volt it is one and the same you see simply because as we have already discussed in the long channel regime the drain influence is not at all felt at the source side. So, drain does not help you in term terms of turning on the transistor only if you turned on the transistor then the drain can accelerate the carriers at larger velocity and hence you can have larger current but you need to turn on the transistor. But in short channel devices drain can also help you to turn on the transistor. So, as a result of that the Dible this is an immediate consequence of Dible this is due to Dible. So, that is why Dible is defined typically as delta v t per unit voltage. If you change voltage by certain amount the drain voltage delta v t by delta v d let me make it more precise. You change drain voltage by certain amount that changes your threshold voltage what is the change in threshold voltage for a given change in drain voltage. Typically it is referred to as you know something like milli volt per volt this is the unit for Dible that is for example you can say that my Dible is 200 milli volt per volt that is rather than measuring the threshold voltage at 0.1 volt. If I do it at 1.1 volt my threshold voltage would be 200 milli volt lower than what you would get at 0.1 volt. So, that is the meaning of Dible. So, Dible is a very important effect in short channel devices and as a result of that you know you will have a significant impact on your threshold voltage. And there are also what are called surface Dible and bulk Dible. What it means is that you know if you look at the transistor a short channel transistor again remember this is drain voltage which is non zero this can couple to the source right and change the barrier. If this is changing the barrier near the surface then that is called surface Dible. If it is changing the barrier near the surface in the bulk meaning deeper down that is called bulk Dible. So, this barrier can be you know impacted anywhere along this corridor that you have between source and the drain. And because of this you would also obviously expect deeper the source drain junction the worst will be your Dible. Because there is larger area for you know drain to sort of couple to the source and you will have much more Dible occurring. If you have a shallower junction your Dible is not as worse. Another very important point that I want to bring up here is that the surface Dible can be controlled by gate voltage to some extent. Whereas the bulk Dible cannot be controlled by gate voltage because this is so far away from the gate. Your gate voltage is effectively screened by the channel and you would not be able to influence anything deep down. And that is why invariably you know what you do in a transistor design you is you essentially put in what is called punch through stop doping or punch through stop implant. Sometime it is also just called punch through implant. What it essentially first of all what is punch through you know if you recall your bipolar junction transistor theory there is something called base punch through right. If you start increasing the collector voltage you know collector depletion bit will start spreading into the base region and effectively you know you may punch through the base right. And there is an analog here you know you can treat your source as an emitter you can treat your channel as a base and you can treat your drain as a collector right. As you start increasing the collector voltage you know there is this electric field sort of progressing into the channel and that is why this name punch through which is sort of taken from the bipolar junction transistor literature because the effects are similar. In order to stop this punch through what you will have to do is that you have to selectively increase the doping concentration here. If you have higher doping concentration you will not let this electric field come in because you can screen the electric field. Higher doping concentration meaning larger number of the carriers and hence the you know electric field will not penetrate deeper. Ideally for example if you have a metal your electric field can be you know easily screened at the surface of the metal right because metal has large number of carriers. Similarly, highly doped P type region will have large number of carriers which will help you to screen the electric field from the drain and will help you to prevent the dibble right bulk dibble can be very effectively prevented by increased doping concentration. The surface dibble can be prevented because it is so close to the gate by decreasing the oxide thickness you see if you decrease the oxide thickness you are making gate stronger the gate electric field becomes stronger compared to the drain electric field right. So, T ox going down is good for dibble and N A going up as we did in punch bulk punch through again is good for dibble right and the junction depths what we call x j x j going down is again good for dibble meaning dibble will be as small as possible if you have all these conditions. Now, one other interesting point which of course is obvious from our discussion, but just for completeness you know I will depict this graphically. If you have to plot dibble on y axis as a function of channel length what would you expect you see at large channel length your dibble is 0 because the drain electric field has hardly any influence on the source. So, your V T there is no difference whether you do V T at 0.1 volt or at point or 1.1 volt, but as you start decreasing the channel length your dibble starts increasing and as channel length start decreasing dibble becomes larger and larger. Again this is evident because of the discussion that we had earlier the smaller the channel length more stronger is electric field penetration into the channel at the source and more is the barrier lowering and hence much more is the decrease in threshold voltage right and that is what you would expect here. And this dibble interestingly also has an impact on sub threshold slope as a function of channel length. When we looked at the sub threshold slope earlier if you remember I talked about sub threshold slope being dependent on a variety of factors right such as oxide thickness doping concentration, but I really did not talk about whether sub threshold depends on length or not. Now in the context of the discussion that we had on dibble if we were to plot the sub threshold slope as a function of channel length what you will see is the following. And let us say this is your best you can achieve 60 this is in millivolt per decade and this as you know is in millivolt per volt. When you have a long channel you do not quite have 60 millivolt per decade because we already discussed that 1 plus c d by c ops will make it little more than 60 millivolt per decade it may be 80 millivolt 90 millivolt per decade or 100 millivolt per decade depending on how good is your design. And when your channel lengths are large it sort of is constant you know it is really not dependent on the channel length. But as you start decreasing the channel length you know at about the same channel length corresponding to where your dibble starts rising you also see your sub threshold start slope starts becoming worse. In other words you know what I am saying here is that if you have your id versus v g s characteristic you know if for a long channel device if you have an id versus v g s characteristic which looks like this for a short channel device what you may have is you know something like this. This let us say is for 10 micrometer length and this let us say is 100 nanometer. What do you see here first of all v t you see in whenever we plot a sub threshold slope the transition between the exponential behavior and the quadratic behavior is a threshold voltage right. First of all in short channel device 100 nanometer again 100 micrometer or 10 micrometer does not matter your v t has decreased because of short channel effect and that is why this point has shifted to the left that is one aspect and your sub threshold slope has become worse compared to this. On a long channel device you have a steeper roll off whereas in a short channel device you have much worse roll off and hence you know because of both these factors because of the fact that v t has decreased and because of the fact that sub threshold slope is also bad you end up with very large off current. This is your off current right whereas you know the off current here is very small you know it goes down because this is in lock scale right. Why does this happen because your source barrier is not just controlled by the gate it is also controlled by the drain now drain is also influencing your source barrier right as we have discussed earlier through the graphical representation as a result of that you know you suffer in terms of sub threshold slope your gate control is not as good and that is reflected in sub threshold slope as well and that is why as my channel and decreases my sub threshold slope becomes worse. So, the Dible has a very important implication and that also impacts your sub threshold slope. I think we have covered all that we wanted to discuss on Dible. I think we have discussed most of the effects at the short channel regime, but let me just discussed in the remainder of the time for this lecture about the field effect mobility and you know after that we would be in a position from the next lecture to start talking about how would one design a transistor in these highly scale technology right. So, you know the impact on mobility due to various factors that we have in the transistor right let us understand that first of all you know this is what we call field effect mobility as opposed to the mobility that you would have seen in a bulk semiconductor right. For example, in silicon we say that when doping concentration is reasonably small not very high doping concentration, but small doping concentration your electron mobility is of the order of you know 1500 centimeter square per volt second right and your whole mobility is of the order of may be 500 centimeter square per volt second correct. These are the typical mobility values which you have studied in the basic semiconductor devices I said at this is first of all at 300 degree Kelvin and at moderate doping. In other words mobility is a strong function of temperature because of the lattice scattering and mobility is also a strong function of doping concentration. Once you start increasing the doping concentration beyond the limit especially if your doping concentration starts increasing beyond 10 power 15, 10 power 16 you will start mobility degrading right. You know more particularly you may have seen the mobility versus doping curves right N A or N D you know which would essentially look something like this initially it is flat constant may be 1500 for electrons and then it starts decreasing you know it really decreases very significantly higher doping concentration results in higher scattering and that is detrimental for your mobility, but when we talk of FETs we really talk of field effect mobility in other words. The mobility that we are interested in is for the electron which is flowing very close to the surface as opposed to an electron flowing in the deep inside a bulk silicon wafer. Current is not due to electrons flowing like this you see current is due to electrons flowing right out here at the channel and what do we have at the channel at the channel we have two dissimilar materials SiO 2 is sitting on top of silicon this is silicon and this is SiO 2 right. So, there is a non-ideality there is an interface between silicon and silicon oxide and this interface results in lot of defects whereas, the bulk silicon is highly pure defect free almost the surface has lot of defect and as a result of that even though you have the silicon p type region here let us say my p type region has doping of 10 to the 15 per centimeter cube or 10 to the 14 per centimeter cube this 10 to the 14 would have been in this region you would have expected a mobility of 1500 for electrons right, but in turns out if you do a mobility measurement in a transistors you may get something like 500 600 max you may not get more than that for electron mobility at 300 degree Kelvin even though the doping is moderate. So, the effective mobility is much lower you know of the order of 500 600 centimeter square per volt second for moderate doping of course, if you start increasing the doping the mobility will go down further, but first of all the reason why this happens is you know you have these defects at this interface these defects also start acting as a scattering sites. So, when these electron is moving it is not able to move freely it gets scattered because of the charge present at the interface and hence it lowers the mobility right. So, this is essentially a very important effect and not only that if you start applying gate voltage larger and larger gate voltage that also starts degrading the mobility even further you see and that is because this larger and larger gate voltage is setting up an electric field qualitatively speaking in the vertical direction right it is trying to pull these electrons in the vertical direction right and you know because of that you know there is more scattering here right and the is with which the electrons can go along the channel and get collected in the drain goes down it is not so easy to do that right. So, as a result of that mobility also depends on the vertical electric field. So, in other words we can actually write this effective mobility as some mu naught right some theta some fitting parameter v g minus v t where mu naught is of course, a function of you know doping concentration that you have in the channel higher the doping concentration to begin with your mobility is lower. And in addition you know it also depends on temperature, but if you are operating the transistor at 300 degree Kelvin you know that is the mobility that we are interested, but in general it also depends on temperature right. So, having determined that subsequently v g minus v t which is a vertical electric field right once you have created the channel once v g is greater than v t there is this current flowing the vertical electric field will also impact your mobility very significantly. Sometimes you know we also use a slightly different model for this mobility there are lots of models that are available which says you know your mobility is given by E c by E effective to the power some constant C where the C is about 0.3 at 300 degree Kelvin if you are interested in the mobility at 300 degree Kelvin that is at the room temperature and E c is called you know critical field which of course, is a function of doping concentration what is the doping concentration that in turn depends on that in turn governs what is your E c value and E effective is essentially given by this term here 1 plus epsilon silicon times the charge that you have which is can be approximated by this q d is the depletion charge q inversion is a inversion charge as you start increasing your gate voltage your inversion charge also increases remember that your inversion charge q inversion can be written as C ox all the these are in per unit area Coulomb per unit area Farad per centimeter square v g minus v t as you start increasing v g minus v t effectively they are sort of related you see you know here we had v g minus v t in the denominator correct where theta was a fitting parameter the mu was a sort of inversely dependent on v g minus v t and here you have this E effective term and you know E effective in turn is given by this and this q inversion as this v g minus v t term right again you see that there is 1 over v g minus v t dependence is sort of captured right. So, in other words you know we you sometimes see in literature what are called universal mobility curves which essentially plot mu effective as a function of E effective that is the effective electric field and you know that would look something like this as the effective electric field which is defined you know based on the equation that we saw just a minute minute ago this right as that electric field increases which is capturing the vertical electric field doping concentration all that effects are captured right. So, you know the effective mobility starts going down. So, the take home message on terms of mobility is that first of all in transistors field effect transistor the surface mobility the field effect mobility is certainly lower than the bulk mobility you can never approach numbers like 1500 for electrons and 500 for holes right it would always be less than that because of the defects at the interface. And on top of it if you have higher doping concentration that is not good for your mobility if you have higher vertical electric field that is also not good for your mobility right what it means is that if you recall our constant electric field scaling theory or generalized electric field scaling theory which said NA should be increased right which of course is not good for mobility right this in turn immediately degrades your mobility significantly and it also we also discovered that we do not necessarily follow constant electric field scaling theory instead we have let the electric fields rise over the years if the vertical electric fields are increasing right the effective is increasing vertical electric fields are increasing that is also bad for your mobility right. So, trying to restore this mobility is one of the most crucial aspect when you are designing a transistor right as we will see from the next lecture we do lot of things in order to get a very good transistor you know a very good transistor which should have largest on current for a smallest of current right it should have a largest on current for a smallest capacitance that is what is called a DC metric of a transistor and an AC metric of a transistor right and that is how we should be able to design a very good transistor. So, in the next lecture we will look at various concepts related to transistor design more specifically what are called channel engineering source drain engineering and so on and so forth. So, to summarize this lecture we looked at sub threshold slope and dependence of sub threshold slope on various factors and we discovered that there are various knobs that you can tune for example doping concentration needs to be decreased, but that is very difficult scaling theory does not let us do that. So, maybe we can do various other things such as using silicon on insulator devices and you know thinner oxides and things like that we also looked at what is called drain induced barrier lowering which is a very important concept which will impact the way the transistor will behave especially at the short channel regime right and we also looked at the mobility which is a very important parameter you know mobility of course will be degraded because of the vertical electric field because of the defects at the interface and also because of the increased doping concentration right. So, with that we will stop this lecture now.