 It's chiptips, chiptips, I have no music and I can't sing! This is my junk room. I buy stuff, play with it, use it, whatever, and when I'm not using it, I put it up here in my junk room. I don't remember half the stuff that's in here. So that's what I'm going to talk about today. Memory. Really? Do I have to say that? Can't I just... Hello, chip friends. I'm going to be talking about memory, specifically static RAM. I have these chips that I actually want to use in my retro computer and there are essentially two types of RAM. There is static RAM and dynamic RAM. Dynamic RAM is memory that you constantly have to read or refresh in order to keep the bits around. That's why it's called dynamic memory because if you stop refreshing it, it goes away. It's very low power compared to SRAM. SRAM actively keeps each cell alive and active so it takes a little more memory but it's very easy to interface with and you don't need a whole lot of circuitry around it. Let's take a look at the timing for these chips. Okay, so here are the signals that go to the RAM. You've got 15 address lines, A0 through A14 because this is a 32K addressable chip and you've got eight data lines and these are bi-directional data lines so they're both inputs and outputs but only one at a time. You've got a chip-enable signal which is active low. You've also got an output-enable signal and a right-enable signal and those are also active low. The chip-enable signal basically puts the chip to sleep but it keeps its memory around so you can't actually read from it or write to it but it's useful to say power down and keep the memory around. The output-enable basically says to the chip, okay, output data according to the address lines. If you assert output-enable then whatever data comes out is whatever is stored at the address that you're putting in. In order to write to the chip, it's a little more difficult. Obviously, you can't assert output-enable or you wouldn't want to because you want to feed data in and if the chip is feeding data out while you're feeding data in, well your two output buffers are going to fight and one of them is probably going to burn out. That's no good. The way that right-enable works is that it's ordinarily high but then when you bring it low and then bring it back high again, whatever data you're presenting to the chip is going to be stored at whatever address you're giving to the chip. Let's take a look at the timing diagrams now. In the datasheet, this is called read cycle 1. What's happening here is that chip-enable is asserted, that is the negative chip-enable signal is low. Output-enable is also asserted and right-enable is not asserted because we're not writing. The chip is enabled, the outputs are enabled and we're not doing any writing. We present an address to the address lines of the RAM and sometime later the data will appear on the output. What is this time? In the datasheet, that's called T sub A and that is 70 nanoseconds and that makes sense because this is a 70 nanosecond memory. This cycle is called read cycle number two and it's a slightly different way of doing a read. In this case, it's called output-enable controlled because we're not going to simply keep the output enabled and then present the address and wait for the data. Like before, chip-enable is asserted and right-enable is not asserted. Here in this timing diagram, unlike in the datasheet, I'm showing output-enable as a positive signal, that just reduces confusion to me anyway. The idea is that you present the address to the chip before you do anything. Since output-enable is not asserted, you're not going to get any data out. First of all, how long is it between when you assert output-enable and the output buffers turn on? In the datasheet, this is called T sub ENG which I guess stands for time to enable based on, they actually call this the G signal but the G signal is also an output-enable. In the datasheet, this is a minimum of zero nanoseconds. So what does that mean? That means that there is at least zero nanoseconds between the output-enable going high and the data buffers being enabled, which means of course that slightly before you assert output-enable, you want to turn off any circuitry that's talking to the chip because otherwise the chip can turn on its output buffers and then again you're going to get outputs fighting or bus contention. So that's why they say minimum zero nanoseconds because they don't want you to assume that there is actually some sort of a delay over here. And then once that happens, how long is it until the data becomes valid? And in the datasheet, this is called T sub AG and that is a maximum of 35 nanoseconds. So in other words, between the output-enable being asserted and the data coming out according to the address is at most 35 nanoseconds. Now you might be asking, well this is a 70 nanosecond memory, how is it going as fast as 35 nanoseconds? Well the key is over here. You can see that the address has been set up long before you assert output-enable. And in fact, we have to look at read cycle number one to realize that from the address being valid to the data being valid is going to be 70 nanoseconds. So this is valid here for a minimum of 35 nanoseconds because if you add up all the times you will get 70 nanoseconds over here. So that's another way of reading when you don't want the output buffers to be enabled all the time. So let's take a little break here and look at the circuit where I've got a 32k by 8 SRAM hooked up. And I've got a switch connected to a debound circuit which is connected to just one of the address lines. All the other address lines are set to zero. So we're only going to be able to access two memory locations. And I've got an LED hooked up to one of the data lines. All the other signals are disabled so we're not going to write. However, chip-enable is asserted and output-enable is also asserted. So let me power it up and we don't see the light being lit. If I press the button to access a different memory address, I do see the light being lit. Honestly, I'm not sure why because on power-up the states of the memory cells should pretty much be random. However, in this particular case, every time I power up this chip, I find that one of the addresses has a zero written to this data bit and the other address has a one. Well, this is convenient because this is really what I want, and what I want to show is how long does it take between me pushing the button and the data changing so we can see how close it is to that 70 nanosecond value that we saw from the data sheet. Now I have this going at 100 mega-samples per second which means that I can only look at 10 nanosecond samples, so this may be plus or minus around 10 nanoseconds, but in this instance, when the address changed, the data changed 40 nanoseconds later. Let's take a look at one more instance. Here's another one. Well, actually, here's one. And as we zoom in, we can see one, two, three, again, 40 nanoseconds. Let's take a look at the next instance. One, two, three, this time 30 nanoseconds. And the next instance after that, one, two, three, 40 nanoseconds. So you can see that, you know, let's call it 35 nanoseconds, maybe 45 nanoseconds at most is when the data changes after the address. Now should we rely on that? The answer is, of course, no. The data sheet says that the most that this chip will delay is 70 nanoseconds. This is where you get into overclocking. And the idea behind overclocking memory is that, first of all, you're going to not pay attention to the data sheet, and you're going to see how fast the chip actually can go. Because remember, the 70 nanoseconds of the data chip is a guaranteed maximum. So if you really want to extract the most performance from your particular chip, then what you have to do is write data to the entire chip and then read it back as fast as you can and see how reliable the chip is over a long period of time. And you do this on your PC, and you can do this on a RAM chip as well. OK, so for this timing diagram, which is called write cycle number one, this cycle is write-enable controlled because we are going to control when we write using the write-enable signal, which means that the other signals, chip-enable and output-enable, chip-enable is asserted, and also output-enable is asserted. So we're constantly reading from the chip. The output buffers are sending out from the chip. But the problem, of course, is that we want to write to the chip. So here's how you do it. The first thing is you set up the address that you want to write to. Now of course, the moment you do that, because output in it is enabled, the chip is going to start trying to read its data and outputting it through the data port. So the next thing that you do is you enable write. So here's the data coming out. Now at some point in time, after you assert write, the output buffers are going to turn off, and when the chip turns its output buffers off, that gives you the opportunity to send it data. So what is that time? In the datasheet, this is called T sub dis w, which I guess means disable from write, and that is a maximum of 25 nanoseconds. So that's important to know, because if you simultaneously assert the write enable signal and send your data to the chip, well, you're probably going to burn something and release some magic smoke, because you were supposed to wait at least 25 nanoseconds before presenting data to the chip. So the question now becomes, how long do you have to present the data to the chip before you can disable write? In other words, how long does the chip take to write data? And the second question is, how long do you have to keep the data on the data lines after you've disabled write? In other words, how long until the chip notices that it should stop writing to its memory? And this is called the setup and hold times, and you'll see this a lot of time in datasheets, which depend on one signal relative to another. So this is the setup time, t sub s u, and this is the whole time, t sub h. So the setup time and hold times are minimum times. They are the inner bounds inside of which you cannot go. You have to remain outside the bounds. The setup time is how much time at least you have to keep the data around before write enable goes low, and the whole time is how much time at least you have to keep the data around on the data lines after the write enable goes low. And in the datasheet for this memory, the setup time is 30 nanoseconds and the whole time is 0 nanoseconds. And what they're basically saying is that you can simultaneously drop the write enable and the data, and the chip will already have written the data, because presumably the actual writing happens in this interval over here. And once that's over, you don't need the data anymore. So that's why the whole time is 0 nanoseconds. So you have to present the data for at least 30 nanoseconds before dropping the write enable line. And then you might ask, okay, well, after I drop the write enable line, how long is it gonna be before I see data on the output lines again? In other words, when do I have to turn my outputs off to the chip? And the answer, of course, is going to be 0 nanoseconds. But the manufacturers have put in their datasheet, what is the enable time from write? And that is a minimum of 0 nanoseconds. So basically what they're saying is you better turn off anything that's talking to the chip after you drop write enable because the chip can immediately turn on its output buffers at that point and start talking. So that's something very important to keep in mind. So that's the first way of writing to the chip. There is a second way of writing to the chip, predictably called write cycle number two. Okay, so for write cycle two, this is chip enable controlled. The idea is that we're gonna set up our address and data lines and also set write enable to asserted, except that chip enable is now low. So again, the chip is asleep, nothing's happening. So the question is, how long do you have to pulse chip enable in order for the chip to simply wake up, write, and go back to sleep? And this is called TCE write, and this is 65 nanoseconds minimum. So that's the second write cycle, and that's the second way that you can write to the RAM. Okay, so let's go ahead and try to write to this RAM. So I turn the power on and at one address, the data bit is low. And at the other address, the data bit is high. Now let's suppose I wanted to write a low onto this data bit at this address. So the first thing that I would have to do is, if I'm doing write cycle one, I would disable the output buffers. So you can see that nothing is coming out. Now the next thing that I'm gonna do is I'm going to set up the address and I'm going to set up the data by pulling this line low. And now I'm going to pulse write enable. So write enable goes low, write enable goes high. And then now I can release everything. So I'm just gonna release. And now if I enable the output, the data bit is low. I can put the bit back to one by doing the same thing by disabling the output, setting up my address, setting up my data to be high. And then pulsing write enable, done. Now I release the data so I don't burn anything. I can release the address and now I set up output enable and the data bit has been written. So that's really all there is to using a static RAM. It's actually very easy to use, so don't be afraid of it. Diggity-diggity-diggity-diggity-diggity. It's Wich-diggity-diggity-diggity-diggity. I have no music and I can't sing.