 Hello and welcome to this presentation of the Embedded Flash Memory, which is included in all products of the STM32L5 microcontroller family. The STM32L5 microcontrollers embed up to 512 kilobytes of flash memory with dual bank architecture. The flash memory interface manages all memory accesses, read, programming and erasing, as well as memory protection, security and option byte programming. Applications using this flash memory interface benefit from its high performance together with low power access. It supports read while write, has a small erase granularity, a short programming time and allows dual bank booting. It provides various security and protection mechanisms for code and data, read and write accesses. The flash memory size is 512 kilobytes. The number of banks is one or two depending on the debank option bit. Note that read while write capability or RWW is only supported when the dual bank architecture is active. This feature enables the programming or erasing of one bank while executing code from the other bank. The page size which provides the minimum erase granularity is 4 kilobyte with a single bank and 2 kilobyte with dual banks. The number of pages is 128. Regarding protection features, the flash interface offers four write protect areas in single bank mode, two per bank in dual bank mode. Two secure areas can be defined, each of them supporting a secure hide protection area. Access to the hide protection area can be denied by setting a control bit. The flash memory supports page arrays, bank arrays and mass arrays. A page, bank or mass arrays operation requires only 22 milliseconds and the programming time is only 82 microseconds for a double word. An 8-bit ECC code is appended to a programmed double word. When reading, the code is checked to detect and correct single bit errors and detect double bit errors. In the case of a non-correctable error, the flash memory controller asserts the non-masculable interrupt or NMI to the Cortex M33. The following protection mechanisms are supported. Write protection areas used to protect against unwanted write operations. Secure areas only accessible in secure state. Secure hide protection areas that can be programmed as non-accessible after a control bit is set. The main memory contains 128 pages. In single bank mode, the page size is 4 kilobyte, each page consisting of 8 rows of 512 bytes. In dual bank mode, the page size is 2 kilobyte, each page consisting of 8 rows of 256 bytes. In addition to the main flash memory, the STM32L5 supports a system memory of 32 kilobytes containing the ST bootloader that is used to reprogram the flash memory through one of the following interfaces. Usart, USB in DFU mode, I2C or SPI. 10 kilobyte for root secure services, 512 bytes of OTP memory that can be used to store user data that must not be erased or modified. If one bit is zero, the entire double word can no longer be written even with the value zero. 4 kilobytes of option bytes containing default settings to configure IPs in the system on chip. They are automatically loaded after a power reset. The table on the left details the memory organization based on a main flash memory area and two information blocks when dual bank architecture is enabled. The non-secure information block contains the system memory and the OTP area while the secure information block contains the RSS and RSS library. The table on the right details the granularity of the flash memory operations. Programming is done on 8 bytes, arrays is done either globally named mass arrays or with bank or page granularity. The secure memory, write protection and secure hide protection is aligned on pages. The dual bank or debank option is used to select either single bank or dual bank mode. The flash memory can be configured to support two banks with read while write and dual bank boot capability able to boot from either bank one or bank two. The swap bank option in the user option bytes is used to swap bank one and bank two addresses. By enabling the dual bank mode read while write is supported. This feature permits a read operation to be performed on one bank while an arrays or program operation is performed on the other bank. A protection mechanism prevents masters accessing a bank while a program or arrays operation is in progress in that bank. In order to read the flash memory it's required to configure the number of wait states to be inserted in a read access depending on the clock frequency. The number of wait states also depends on the voltage scaling range. In range zero the flash memory can be accessed up to 110 MHz with five wait states. It can be accessed with zero wait states up to 20 MHz. In range one the flash memory can be accessed up to 80 MHz with three wait states. In range two the flash memory can be accessed up to 26 MHz with two wait states. Thanks to the instruction cache the program can be executed with zero wait states independent of the clock frequency. This provides an almost linear performance in relation to the frequency with a benchmark result of 165 dry stone MIPS at 110 MHz. Data in flash memory words are 72 bits wide. Eight bits are added per each double word of 64 bits. The ECC mechanism supports single error detection and correction, double error detection. The programming granularity is 64 bits, really 72 bits including 8 bit ECC and 144 bits when single bank mode is used, two times 72 bits. When one error is detected and corrected the ECCC flag indicating ECCC correction is set in the flash ECCC register named flash ECCR. An interrupt can be generated. When two errors are detected the ECCD flag indicating ECCC detection is set in the flash ECCC register. In this case an NMI is generated. The programming time of a row is equal to 82 microseconds multiplied by 32 double words. The programming time of a page is equal to 82 microseconds multiplied by 256 double words. The mass erase time meaning a 512 kilobyte erase operation takes approximately the same time as a page erase. Each program and erase operation can degrade the flash memory cell. After an accumulation of program and erase cycles memory cells can become non-functional causing memory errors. Endurance is the maximum number of program erase sequences that the flash memory can support without affecting its reliability. Data retention is defined as retaining a given data pattern for a given amount of time. The retention depends on the number of program erase cycles and also on the temperature. The global trust zone system security is activated by setting the TZEN option bit in the flash OPTR register. By default all flash memories secure. When the trust zone is active additional security features are available. Secure watermark based user option spice defining secure hide protection areas. Secure or non-secure block based areas can be configured on the fly after reset. An additional readout protection RDP level 0.5. Arrays or program operation can be performed in secure or non-secure mode with associated configuration bit. When the trust zone is disabled these features are deactivated and all secure registers are read as zero right ignored. When trust zone security is active a part of the flash memory can be protected against non-secure read and write accesses. Up to two different non-volatile secure areas can be defined by option bytes and can only be read or written by a secure access. In single bank mode two areas can be selected with a page granularity. In dual bank mode one area per bank can be selected with a page granularity. Each mode supports a secure hide protection area starting at the same start page offset and ending at a programmable end page offset. The contents of the secure hide protection area is marked as non-accessible after the corresponding HDPA CC disk bit is set to one. The secure HDPA area is part of the flash watermark based secure area. It enables isolation of the secure boot code and data secrets such as authentication and cryptographic keys from the secure application code. The HDPA area is activated by programming the end page offset and setting the HDPA enabled bit. Access to the hide protection area can be denied by setting the HDPA access disabled bit in the flash sec HDPCR register. When this bit is set data reads, writes and instruction fetches on this hide protection area are denied. The HDPA access disabled bit can be only cleared by a system reset. The figure on the right explains the typical usage of the HDPA area. The system boots and executes code in the HDPA area. The HDPA exit function present in the ISS lib is called once the secure boot is completed. This function sets the HDPAx ACC disk bit. The HDPA exit function branches to the secure application. If the secure application attempts to branch to or read data from the HDPA area, the access is denied and an error is signaled. Full write protection areas are supported. Two per bank when debunk equals one and four for full memory when debunk equals zero. Program and erase operations are prohibited in write protection areas. Consequently, a software mass arrays cannot be performed if an area is write protected. Each area is defined by a start page offset and an end page offset relative to the physical flash bank base address. The write protection attribute is orthogonal to secure and HDPA settings. Any page can be programmed on the fly as secure or non-secure using the block based configuration registers. One bit per page enables the secure software to dynamically configure a page as being secure or non-secure. In dual bank mode, FlashSecBB1R124 registers are used to configure the security attribute for pages in bank one and FlashSecBB2R124 registers are used to configure the security attribute for pages in bank two. In single bank mode, the FlashSecBB1RX registers are used to configure the security attributes for pages in the entire flash memory. When the page security attribute is set for a page, the security attribute is the same as the secure watermark based area. A secure page is only accessible by secure access. If the page security bit is set for a page already included in a secure watermark based area, the page keeps the watermark based protection security attributes. To modify a page's block based security attribute, it's recommended to check that there's no ongoing flash operation on that page, add an ISB instruction after modifying the page security attribute. When the access disabled bit is set for HDPArea1 or 2, the HDPA setting can no longer be changed. HDP end page offset and enable bit. The secure area configuration is also locked. Secure start page offset and end page offset. This locking remains active until the next reset. If the user tries to modify one of these option bytes while HDP access disabled bit is set, the option bytes modification is discarded without error flag. The flash is secure when at least one secure area is defined either by watermark based option bytes or block based security registers. This will lead to control the source clock of the flash as secure. It's possible to override the flash security state using the sec-in bit in the flash sec-cr register. The source clock may remain non-secure while the flash interface has a secure attribute. The flash interface is a trust owner where IP containing both secure and non-secure registers. The flash registers can be read and written by privileged and unprivileged accesses depending on priv-bit in the flash priv CFGR register. When the priv-bit is reset, all flash registers can be read and written by both privileged or unprivileged accesses. When the priv-bit is set, all flash registers can be read and written by privileged accesses only. Unprivileged access to a privileged register is read as zero, right ignored. The root secure services or RSS are embedded in a flash memory area called the secure information block programmed during SD production. The RSS enables, for example, the secure firmware installation or SFI thanks to the RSS extension firmware named RSS ESFI. This feature allows customers to protect the confidentiality of the firmware to be provisioned into the STM32 device when the production is subcontracted to a third party. RSS is available on all devices once trust zone has been enabled via the TZEN option bit. It's composed of the RSS boot and the RSS library provided by ST. A pair of public and private keys is provisioned in the RSS area to enable the user image authentication as well as a certificate and a unique ID. The boot loader is also designed by ST but unlike RSS it can be used when trust zone is disabled. Option bytes are used to configure the system on chip before starting the Cortex M33. There are automatically loaded after a power reset or on request by setting the OBL launch bit in the flash CR register. The latter allows a new configuration to be made without resetting the device. This slide and the next two describe the various fields in the option bytes. When TZEN is set trust zone is active. Boot log forces the system to boot from the main flash memory regardless of the other boot options. The setting of secure areas and secure hide protection areas is done through option bytes. The readout protection level enables the readout protection for the entire flash memory. Level 0 no protection. Level 0.5 non-secure debug only. Level 1 read protection. Level 2 no debug. Readout protection is fully described in the presentation related to memory protections. The write protection start page and end page offsets are also programmed in option bytes. The flash memory controller supports many interrupt sources listed in this slide. Two maskable interrupt request signals are used to report a flash event to the NVIC. Flash is for secure events and flash for non-secure events. An interrupt can be asserted upon successful land of operation. An interrupt can be asserted when an error occurs during a program or erase operation. The next slide details the various operation error causes. A single bit error correction is also a non-secure interrupt source. When two bit errors are detected on a flash memory read, the non-maskable interrupt is asserted. This table indicates the sources of operation errors. Two status registers used by software to identify the cause of the operation errors are implemented. Secure and non-secure. A write protection violation occurs when an attempt to write to a write protected area is detected. A size error occurs when the data to be programmed is not word aligned. A programming sequential error occurs when a program operation is attempted without having previously erased a location in flash memory. A programming alignment error occurs when a complete double word is not provided before initiating a standard program operation. An option write error occurs when the option bytes are written with an invalid configuration. The flash memory's consumption can be reduced when the code is not executed from flash. The flash clock can be gated off in run and low power run modes. It can also be configured to be gated off in sleep and low power sleep modes. The flash clock is configured in the reset and clock controller. It's enabled by default. The flash memory can be configured in power down mode during the sleep and low power sleep modes. It can also be configured in power down mode during run and low power run modes when the code is executed from SRAM. Gating the clock and putting the flash memory in power down mode significantly reduces power consumption. The flash memory module supports the following low power capabilities. Clock gating, flash memory power down mode, power gating of the entire module, flash memory and controller. In run, sleep, low power run and low power sleep modes clock gating and power down is supported. It can be used when code is executed from SRAM. In stop 0, stop 1 and stop 2, the clocks are gated and flash memory can enter power down mode. In shutdown mode, the power of the flash memory module is gated for both the flash memory and controller. Gating the clock and putting the flash memory in power down mode significantly reduces power consumption. The flash memory module has relationships with the following other modules. Instruction cache or iCache, system configuration controller or syscfg, reset and clock controller or RCC, power controller or PWR, interrupts or NVIC, memory protections. For more details, please refer to application note AN2606 about the STM microcontroller system memory boot mode and AN5428 about the STM32 microcontroller system memory RSS services.