 So we're right here at the Altera booth. So who are you? I'm Chris Ballo and I'm responsible for the SOC FPGA product marketing in Altera. So you're one of the leading FPGA companies in the world, no? That's right, that's right. Altera is one of the leading companies. So what is this new product? It's our second generation SOC FPGA. So it's the combination of an arm fully dedicated, hardened arm subsystem with advanced FPGA logic monolithically integrated on the same device. So this is a 20 nanometer and you are shipping now, this is a new announcement? That's right. So we just announced, I believe today the announcement went out that we are now shipping our second generation SOC FPGA at 20 nanometers. So the first generation was also Cortex-A9 right? It was a dual core Cortex-A9, that's right, built at 28 nanometers. And now is it still a dual core? This is. In fact, we deliberately replicated the same processor subsystem architecture and the second generation to create a more integrated first to second generation transition option. So all the software is kind of like pin to pin compatible? It is, I wouldn't call it object code compatible, but the structure of it is fundamentally the same. It's the same dual core A9, virtually the same peripheral set. We made some enhancements to security, added a couple of peripherals. So there's a couple of very minor differences, but from an application layer it's essentially identical. So what kind of enhancement security are you doing? We added a strength into the secure boot capabilities. And we also added some ports for Ethernet, and some strength for the Ethernet connectivity. All right. And here you're showing angstrom Linux? That's right. So we're actually showing the device here, because we announced shipping. So we're actually demoing the development kit, and we are actually running Linux right now. And this is the size of it? This is the size of it? This is right here. This is a partner, so they actually are using, this is a partner's development kit. It's the ATERRA Aria 10 SoC development kit. So this SoC right here has ARM? They come in different densities and different packages, so you'll see a different package between these two development kits. So in the SoC there's a little bit of ARM, but there's kind of like a massive FPGA, you know? That's right. It's a combination of the processor and the FPGA. So how much performance is there in the FPGA on this SoC? Well, the FPGA really depends on the design that you're integrating into the FPGA. Because remember, it's really meant to be, essentially, FPGA is kind of an on-demand ASIC. So it's a software-programmed ASIC. And so people can do stuff like this? What is this kind of demo? This is really just a robotics motion control demo. And it's using our first-generation SoC. So the Cyclone 5 SoC. Just showing an example of how you can do robotics, demo, and partition the control algorithm between the FPGA and the processor. All right. Let's walk around here. There's all these boards that you're showing right here. Yeah, we've had just a tremendous amount of interest from partner companies to build out development kits and application-specific reference designs. And so this really shows you just a sampling of those things. All right. Lots of companies working with the Cyclone. Are they all going to work with IREA too? They might. It really depends on the application. Right. And then we have right here... So hello, so who are you? Hi, my name is Graham Baker. I work in the Low Cost Product Marketing Group. So I'm responsible for Max 10 and Cyclone 5 in Europe. So here, Max 10, what is Max 10? Max 10 is our newest Low Cost FPGA. So this is a non-volatile device. So we store up to two configuration images inside the device. And it's selectable to power up which image you've actually run from. So it's an entry-level? It's kind of like an entry-level FPGA arm solution anymore? This is an entry-level FPGA. There's no RIP core as we have in Cyclone and IREA families today. Only FPGA? Yeah. So this is just a pure FPGA. And so how does it work and what can people do? Okay, so some of the key differences about Max 10 are, as I mentioned, it's a monolithic die. So it has onboard flash memory. But we're trying to solve different problems to what we've done before with FPGAs. So we have integrated analog to digital converters, for instance, on the die. We've also done a lot more with packaging. So we now have a range of packaging from four millimetre square chip scale packages right up to 500 IO larger devices and six, seven to two. So when you say entry-level, what does that mean? How entry-level is this? Entry-level, so you can use these devices from very small, simple almost glue-like functions or something like this where we have a motor control demonstration running. So this particular design has a NEOS processor inside it. It's running all of the communications up to the PC. And the actual motor control is controlled by the FPGA array itself. So we've developed a control algorithm using DSP Builder, which runs in the MATLAB Singulink environment. And we can control the motor here. And this particular demonstration, it's a wheel of fortune. We know where the wheel is. In this case, it's pointing at Max 10. And on the screen here, it correlates to the image that comes up. So if you hit the Max 10, you win the board? If you get three the same, you win a prize? Or if it's score over 25?