 We will begin, we will take up from where we had left off for logic design and because different styles of configurable logic make use of different styles of logic, we considered one type of configuration logic which was essentially an offshoot of the CMOS style of logic design because there we had a CMOS kind of logic design and we saw that by changing the connections in that template that we had designed, how can we convert the template to alternately series or parallel combinations as required by CMOS. So, just to summarize on the CMOS style of logic design, one of the advantage of this is that the logic consumes no static power in this style because either the upper switch or the upper switch combination or the lower switch, the lower switch combination is off. So, there is no continuous flow of current from VDD to gram. So, this is a great advantage of CMOS summary. However, notice that every signal which is brought to the input. So, one of the advantages of CMOS design style is that either this switch is off or this switch is off and as we had seen this continues to be true even when we have more complicated logic which is maybe a combination of NAND and NOR because the whole combination is either the upper one upper combination is on or the lower combination is on and the other way round. So, therefore, there is no static flow of current from VDD to ground. We will later see that this is not true in other styles of logic. However, the disadvantage is that every input signal must then be routed to one N channel and one P channel transistor. This wire tends to be rather long because the N channel and P channel transistors cannot be brought very close together. Recall, they have different channels therefore, their substrates are doped differently and this is done by having different wells and these wells are far apart from each other. As a result, these two transistors cannot be placed close to each other and therefore, the wiring capacitance as well as the gate capacitance of these transistors presents a heavier load on the previous output than otherwise. However, still as far as the speed power product goes CMOS is one of the leading methods of implementing logic. There are however cases and in particularly useful for configurable logic that other styles of design are also where other styles are also used. One of these is indeed a modification of the enhancement depletion type of NMOS that we had talked about earlier. However, rather than using an enhancement type NMOS, notice that we have a PMOS here whose gate is returned to ground. Therefore, this transistor is always on. However, this transistor is rather weak. Therefore, when the lower transistor turns on which is stronger, much stronger, the output voltage is pulled down to ground because this is a much stronger transistor compared to that. So, the two do fight, this guy is trying to raise it to VDD, always on and this guy turns on, it pulls V out to ground which tries to turn it off. So, there is a static power flow from VDD to ground while this switch is on. However, if this is made stronger, it will succeed in bringing the output down to 0. On the other hand, when this transistor is off, then the situation is somewhat like CMOS, only the upper transistor is on and the output gets charged to 1. So, this is called the pseudo NMOS design style because the NMOS design style used to have a depletion MOS here which we had discussed during one of the question and answer session. So, we are not going to go through the EDMOS design style, but this is essentially very close. Notice that this ratio, this logic is also called ratioed logic because it does not work unconditionally, it works only when the ratio of strength of the upper and the lower transistor is right, otherwise this will not work. However, the pseudo NMOS design style has some advantages. For example, notice that the input goes only to one transistor and this is the NMOS which is physically smaller than the PMOS for the same amount of conduction. So, as a result, the capacitive load on the input is relatively small and at high frequency, the dynamic power consumption can be smaller than in the case of CMOS. So, as a result, it does have some advantages particularly at high frequencies. However, what concerns us right now is its suitability for its use in programmable logic. So, then let us see how we can use this kind of logic for programmable logic. So, let us see what are the ways of making things other than inverters in this ratioed pseudo NMOS logic. Recall, this is how the inverter was made. The signal went only to the gate of one transistor and its output then appeared here. Now, the same series parallel rule applies in this case as in the case of CMOS. Only we have to apply the rule only to the NMOS transistor. So, it is much easier and exactly the same series parallel rule is applicable here. So, the series parallel rule applies. Now, what this means is that for every plus, there must be a bar on top and for every plus, the NMOS transistors must be in parallel and for every dot NMOS transistors must be in series. So, this rule restricted just to NMOS transistors still applies here. The PMOS there is always just one and the gate is always grounded. So, we do not have to worry about that does not change. Let us take our old friend the long expression that we had implemented in CMOS logic namely this logic and let us implement it in pseudo NMOS logic. There is a bar on top. So, we are fine A dot B that means A and B in series plus means this whole combination in parallel with C dot that means C in series with D plus E that means the parallel combination of D and E and that is all there is to it. The load is just a single PMOS transistor with a grounded gate and this is our A dot B plus C dot D plus E bar in pseudo NMOS logic. Notice whenever the output is 0, there is a path to ground and there is static power consumption. Wherever the output is 1, there is no static power consumption and every input is loaded just by one transistor load. However, there is one complication that we must be careful about. Whenever you put transistors in series, their on resistance adds and it effectively makes the transistor weaker. Therefore, we must for every transistor if we have two transistors in series, we must increase their width by a factor of 2. So, let us say that the on resistance of a transistor is R. If I put two of them in series, their effective resistance will become 2 R and to bring it back to R, I must reduce the resistance of each transistor to R by 2 and that is done by increasing the width to double its value. Therefore, for the same voltage, double the current flows which reduces the resistance by half. Therefore, essentially if you have series connected transistor for the same performance, I must reduce the on resistance of these to R by 2 and R by 2 and now this will be equivalent to a single transistor. In order to reduce this resistance to R by 2, then I must increase its width to 2. What about NOR kind of logic? How do we modify the geometry if I have a NOR and let us consider just a simple NOR. The simple NOR is just a plus b bar. We have a bar, so we are fine and therefore, we must put a and b in parallel. That is about it. Let me just write down the truth table of a NOR gate just so that we can argue about the geometries in this case. So, if you have a and b and the out, in that case if any one of them is 1 or both are 1, then the OR is 1 and therefore, NOR is 0. Only when both are 0 is the output 1. So, this is the truth table. Now, notice that in three cases the output has to be pulled down to 0. Now, actually you have the on resistance here R and the on resistance here R which come in parallel. You might be tempted to say that now I can use 2 R for each, so that in parallel they give me R, but that will not be right because both transistors are not always on. They are both on only in this case. However, in two other cases only one of them is on and therefore, even in that case it must present the resistance R. Therefore, whenever the transistors come in parallel, I must leave their geometry unchanged. Therefore, the answer is for parallel leave the geometry unchanged and for series scale the width by the number of transistors put in series. We saw the example in case of 2. Now, what it means is that if you have to have reconfigurable logic our transistors are fixed. We cannot change their size and that makes it very inconvenient to use those logic configurations in which we need to put transistors in series. Let us now consider the problem of reconfigurable logic with this in mind. As we have seen before any generic logic expression can be written as a sum of products. So, if I have some inputs then first I must form the desired products and then I must take the R of all of these then I can produce any arbitrary logic. So, what I want to do is to keep the hardware unchanged and by some programming make this hardware perform the function of a given logical expression which is expressed as a sum of products. Now, the sum part there is no problem because n MOS transistors are in parallel and therefore, the geometry is unchanged. On the other hand what about creating products? If I was to do it in a simple minded way then to produce a product it is an AND function dot function and therefore, n MOS transistors will be in series and I would need to scale the geometries and this is a problem because when I configure I cannot change the transistor I cannot change its W by L. The transistor has already been made I can only reconnect it in a different way. So, the question is can I not construct a product using NOR kind of logic and fortunately it is possible what we do is the following. Consider this NOR to which rather than giving a and b we give a bar and b bar and let us see what logic function it represents. So, again we form the combinations of a and b then the corresponding values of a bar and b bar are the opposite of course, the OR of these would have been one therefore, the NOR of a bar and b bar is 0. In fact, if either input at this place is 1 that ensures that the output goes to 0 and only in this case the NOR will be 1. Now, forget about this intermediate value and see what function of a and b have we constructed if either of a and b is 0 in these three cases then the output is 0 only when a and b are both 1 that the output is 1 and therefore, we have actually constructed an AND gate or a product. So, therefore, this is equivalent to creating a product of a and b it is an AND notice not an AND. So, we have created a product of a and b by feeding a bar and b bar to a NOR. Why should we want to do this? Because NOR is a kind gate it puts n channel transistors in parallel and that does not require a change in geometry. So, now we have got a an architecture which will allow us to construct arbitrary sums of products without changing geometries of transistor. Let us see how we do it. First of all our inputs are going to be barred. So, what we do is that for every input we create two lines. So, that both a and a bar b and b bar are available. So, every input is available in direct and in complimented form. Let us say that we have a b c d and e like this. So, therefore, I have a here I have a bar here b b bar c c bar d d bar and e with e bar I have all these inputs available. Now for every unique product I add a row to this matrix. So, these lines are just run this is the template in this particular case. So, these lines will just run through. Now I connect unfortunately this does not come through very nicely as I draw. So, these lines are actually continuous and there is no switch there. These are just continuous lines. Now for every product I now put a new row here. So, this line is not connected to any of the vertical lines it is just running independently. And I put the pseudo enmos load which is a p channel transistor with the gate connected to ground here and this is essentially b d d. And let us say that we are trying to generate that same old expression which we have been practicing with. Namely we eventually want to create a dot b plus c dot d plus e which will be c dot d plus c dot e. We might in fact have the option of generating a product of barred quantities also. For example, we could have generated a dot b bar plus c dot e plus c bar dot e. So, any of these things is possible. Now for every product in this I will draw a horizontal line and connect a grounded gate p MOS here. Now at the junction at each junction there are premade enmos transistors. So, these premade enmos transistors are there as a part of the template throughout and I have the choice of connecting that transistor or not connecting that transistor. So, let us take the case that we want to generate a dot b. As you know a dot b is in fact the norm of a bar and b bar. Therefore, the circuit that we want is this with parallel connected transistors with a bar this is not connected a bar and b bar there. That means I must take a bar and from this line put a transistor to ground like here and take b bar here and put a transistor to ground which is available I will just connect it. So, as a result the circuit if I can redraw this will look like this. This is my v d d line and as before we have generated a a bar b b bar and so on. We will draw the rest later you can imagine the rest. So, this is b and b bar and these will run through. So, a a bar b and b bar they will now run through and I have the load pre connected from here which is a p channel transistor with the gate grounded. Now I run a line here and connected to a is a transistor grounded connected to b is a a bar is a transistor grounded and so on. This is all part of the template and my choice is to connect this transistor or not to connect this transistor to this running line. Now consider the case that I connect the a bar transistor here I connected and the b bar transistor here and I connected. Then what is the effective circuit if I just redraw it here in a clear space I have the p channel transistor connected to v d d and then I have two parallel transistors one connected to a bar the other connected to b bar. Therefore, this output is nothing but a dot b. So, this line will now carry a dot b if you recall what we wanted was a dot b plus c dot d plus c dot e. So, this a dot b now we have generated we also need c dot d. So, we put another row here in fact all these rows are pre made we do not put new transistors transistor arrays like this are already there I am just drawing them as and when required. So, now if I have c and c bar as before and d and d bar I can connect the c bar and d bar transistors now and now I will get a get a nor of c bar and d bar which is nothing but c and d. These transistors actually should be in the next row. So, this then gives me c dot d. So, for every product I can utilize one more row. Therefore, I can have as many distinct products as I need as there are rows. So, in reality what happens is that this kind of transistor placement this whole kind of transistor placement is pre made and put on silicon. So, what I have are many rows each with its own p channel transistor and each with the upcoming signal and signal bar lines each one of which at the junction has an uncommitted transistor which may or may not be connected. So, all this stuff is already there and there are transistors all across like that these are just hanging there they are not connected and now whichever term occurs in my product I just connect up that transistor. So, for example, this is a bar and that means a will be there in my product this is b bar and there was a transistor here which I have connected up this one I leave hanging this one I leave hanging. So, only a bar and b bar are connected here and finally, I will get a dot b here and now each distinct term will appear here. It is now just a matter of turning the same thing around because this is actually a nor array which is being used for producing and functions of negative input. These outputs can then be fed to another nor array which is identical to this and now that will produce the sum. So, now one array produces the product the other array produces the sum and I can now implement multiple sums of products using two arrays like this. So, if you look at the bigger picture of this then all the inputs are here and locally their inverts will be generated and the whole thing that I have just explained with the p mask loads here and so on. So, this whole thing is called the product array and then the outputs from this go into a similar array which is the nor array. So, these are positive true inputs and I can pick whichever I want in my sum and place transistors exactly like I did before and now I get as outputs various sums of products. If I produce arrays like this then all I need to do is to connect the appropriate transistors to form the expression that I want. For example, let us say that I simultaneously want a dot b plus c bar dot d I want a bar dot c bar dot d bar plus b and a b c plus d. Now, how many unique product terms I have? I have a b, I have a b c, I have b, I have d, I have c bar d and I have a bar c bar d. So, each one of these will correspond to a row. For example, for a b connect the a bar b bar gated n moths to the output for this a bar and b bar and c bar this only b bar this only d bar this c and d bar. So, it will become c bar dot d and this a c and d. So, it will become a bar dot c bar dot d bar. So, now all these terms will come out from here and I am going to pick a b and c bar dot d terms only for one I will pick a bar dot c bar dot d bar and b for the other and all these sums of products will become available as output of this. So, this thing can now implement multiple sums of products from a given set of input signals. This thing is called a programmable logic array and generalizations of this have become the CPLD or the complex programmable logic devices. So, CPLDs are essentially devices which have multiple units of this. Some of them have the AND matrix pre-programmed and this can be programmed by arrays others have the plus pre-programmed and this can be programmed by the user and you can have many, many such combinations and by using them all you can you can produce complex logic and this is the kind of circuit that you have in fact used in your lab. So, these are the complex programmable logic devices which then lead to the kind of logic you want to implement. No fresh silicon has to be made you just buy this chip and now you can program it once and for all. So, the user can now design an integrated circuit and that is the great advantage of programmable logic. It also has economic advantages because the manufacturer makes the same device irrespective of the logic that people want to use. As a result these devices are made in large numbers which brings economies of scale and now you can make them much cheaper. So, anybody you may want only a thousand pieces which performs one function. Somebody else may require five thousand pieces, but overall summed over all the users millions of such chips will be required and when chips are produced in millions they can be made much cheaper. So, as a result this is the advantage of C P L D or in general configurable logic that you can make personalized logic and yet reap the benefits of economies of scale because the original chip is now manufactured in very large numbers and it services many people. This is like a microprocessor. For example, a microprocessor can be programmed to perform various functions and everybody's function may be different. So, people may use microprocessors in small numbers, but everybody uses the same processor and therefore, the processor part itself is made in very large numbers and that makes them cheap. For example, you can go and buy an 8051 which is quite a complicated chip actually for reasonably low amounts of money fifty to 100 rupees. This is very good value for money and that is possible because of economies of scale. So, therefore, whenever you allow various people to use the same chip and to personalize the application according to their wishes, then you have this advantage of clubbing all their requirements into a signal chip and you can bring down the cost of electronic system using programmable logic array. The next question then is how do we use? How do you program them? Assume you need to have a standardized language which will then program this configurable logic and many such languages have been developed. These are together called hardware description languages or HDLs. Examples of these are VHDL, Verilog and many others. These are the two leading hardware description languages used in the world right now. VHDL and Verilog both of them fall into this category and they permit you precisely this. They permit you to describe hardware and then there are compilers which look at that description and then can map it to instruction which will program a configurable logic block to perform the function that you want. So, we will be seeing VHDL and Verilog as applied to the specific use of structural description. These are very powerful languages and they can be used for many many functions. However, we will not have time to go over all the powerful functions performed by these programming languages, but we will look at them only in the context of describing structural hardware. Structural hardware means you describe a module and its interconnection. So, you just put down modules and their interconnections and that description is then interpreted by some software which will then program your configurable logic. So, as far as the user is concerned you need not worry about the implementation anymore. You can simply describe the logic elements and their interconnections and use one of these languages for it and software is available which will then interpret that description accordingly produce the command files which will configure that logic often called bit file and these bits will then be downloaded to the configurable chip which will then make it perform the function that you wanted to perform. So, we shall take up hardware description languages from tomorrow onwards in a couple of lectures and because the time is quite limited indeed this stuff is actually taught in post graduate courses full courses of 40 lectures. So, obviously we do not have time enough to go in full details of VHDL and Verilog. However, we will use these languages for the limited purpose of structural logic description and that is easy to do and this is what you would be using in your lab demos have already been given to you about this. So, we will then bring the programmable configurable logic to a stop here. There are multiple other ways of implementing programmable configurable logic and we have not had time to describe field programmable field programmable logic which is FPGAs and those are actually generalizations of the same kind of techniques that we have used, but they also have interconnect matrices and pre-programmed on chip components which can be connected together to form very complex circuits typically of complexity of millions of gates. They can all be made on configurable logic using FPGAs. So, those are field programmable that is to say you everybody buys the same chip, but then you program it using hardware description languages and now you can make combinational as well as sequential circuits by just hardware description and that is a fascinating subject by itself. Unfortunately in the course of basic electronics this is all that we can do during the course. I would now like to change over to something which has been discussed very frequently. We are changing gears here somewhat violently. We are now going over to internal design of op-amp. Now I have already uploaded two files for you. One is a bipolar op-amp design, the other is a CMOS based op-amp design and what I would like to do today is to take these up only briefly and develop most of it through a question answer session because often there are lots of questions and we do not have time to tackle them all and many questions remain unanswered. So, what I would like to do today is to leave much more time for question answers. However, I do request you to please restrict your questions to the topic of internal design of op-amp. Other questions we can take up on Moodle or later, but in today's discussion for the extra time that we will make available for the discussion session. Let us discuss two questions about the internal design of op-amp. We are just uploading this file on a view copies of which are already available on Moodle and this describes a 741 from inside. So, this file is now available and I hope you can see this on your screen. This describes the circuit of a 741 and it is quite a handful as you can see. Analyzing this like this will be quite difficult. So, what I have done is essentially simplified this circuit in various operative components and then we can discuss all the components one by one. First of all, this is a three stage op-amp. The first stage is this differential amplifier. So, this part is a differential amplifier as you can see it is symmetric left and right. So, this is a differential amplifier. The output of this then goes to a common emitter amplifier. This common emitter amplifier acts as a phase splitter and drive a push pull output stage. If you look at it, it will look quite similar actually to the totem pole output that I had, but that was NMOS NNPN only. This is complementary. It has NPN as well as PNP and the output is a source follower. Professor Joseph John had described the characteristics required of these three stages and indeed this op-amp follows those stages. This stage is optimized to produce a high input impedance. This stage is optimized to produce a high voltage gain and this stage is optimized to produce a low output impedance. Indeed, these are emitter followers and therefore, provide no voltage gain at all. However, their output impedance is very low and therefore, it meets the requirements of an op-amp of a high input impedance, high gain and low output impedance. These three functions are now separated into three components and each component can be optimized for its particular function. For all of these to work, you need to generate appropriate biases and there is a bias generator circuit which does precisely this. In addition to that, there is short circuit protection in this, so that if you by mistake short circuit the output, the circuit should not blow out. So, that is a safety feature. Let us look at various components of this circuit and look at their functionality. The first part is the bias generator. It is the same circuit, but all the amplifiers have actually been put inside a black box, so that we can concentrate on what we need to look at at one single time. So, the first part is that we are not confused by the complexity of that circuit. So, this is the positive supply v plus and this is the negative supply v minus and first of all, look only at this first column. You have two diode connected transistors here. This q 12 is a p n p transistor, q 11 is an n p n transistor. These are diode connected and this resistor then determines the amount of current which will flow in this part of the circuit. So, essentially the difference of the positive and the negative supply minus twice v b e, one contributed by q 12, the other by q 11, that voltage is dropped across 39 k and that gives you the amount of current which follows, which will flow through this circuit. So, therefore, we call this current I ref. So, you can see that the reference current I ref is the difference of the two supplies v plus and minus v minus. Notice that v minus is negative. So, if this was 15 and this was minus 15, then this will be 30, minus twice v b e, one v b e contributed by this, the other by that. This entire voltage dropped across this 39 k resistor which is r 5. So, therefore, this divided by r 5, that gives you the value of the current. So, with a nominal supply voltage of plus minus 15 volts and v b e taken to be 0.65 volts, notice that the current flowing are quite small and therefore, we take a somewhat smaller voltage than 0.7. So, v b of 0.65 and r 5 equal to 39 kilo ohms, this will give a factor of about three quarters of a milliamp which will flow through this. That means, you have about 736 micro amp flowing through this. This current must then be equal to the current through this plus the drop across this, because the v b e is different. So, if you equate the voltage here, in this path and this path, then the v b e of q 11 is equal to v b e of q 10 plus r times i. So, this is the equation that we have here and as we had derived in one of the discussions, the voltage across a forward bias diode is k T by q which is written as v T here. This is about 26 milli, 26 milli electron volts, 26 milli volts, this is voltage. So, 26 milli volts into natural log of i ref by i s on this side, that is the v b e here and that is equal to the current through this path. So, that is k T by q l n i through this path which I am calling i Widdler divided by i s plus this resistance into the current. So, these two voltages, I am equating voltages at this point. On the left hand side is the voltage derived according to this diode, on the right hand side is the voltage derived by this diode plus the drop across r. So, that is this equation. You can write this in this format in which the Widdler current is given by this expression. Now, notice that this has the Widdler current, Widdler by the way is the designer of the first op amp and the 741 was also designed by him. So, this Widdler current is given by this expression and this i occurs on both sides. Therefore, we cannot get a closed form solution for this. We have to iterate and solve this. So, then when you iterate through this taking some guess value and in this case I have on purpose taken a value which is far away from the solution like 2 micro amps and then put that 2 micro amps here that will give you a value of current. So, you get 30.6, you put 30.6 here and get the next value you will get 16.5, you put 16.5 here and calculate you will get 19.7 and then 18.7 and then 19 and then 18.9. So, these numbers converge pretty quickly and eventually you will get about 19 micro amps of current flowing through this second arm that means this arm has about 19 micro amps of current flowing. This current is then mirrored in various stages and provides. So, for example, this 3 quarters of a milliamp provides the reference for this transistor and the ratio of the emitters allows you to use 0.75 milliamp here, 0.25 milliamp here. So, this whole transistor Q 13 and Q 13 A and Q 13 B they give you two current sources in 3 is to 1 current ratio because these emitters are in 3 is to 1 current ratio. Indeed Q 13, Q 12 and so on have their emitters all common, the base also all common. So, it is all made in one single pocket with different collector. So, that is the bias generator. Now, if you look at the differential stage, we have already discussed the bias generator. So, you need not be worried about this. Notice that Q 1 and Q 2 form emitter followers. The input is to the base, the collector is given a fixed bias. Therefore, it is a common collector amplifier, it is an emitter follower and therefore, it is input impedance is very large which is what you want in case of a differential amplifier. It is output impedance is low and that feeds this common base amplifier. So, Q 3 and Q 4 have their bases fixed by this bias generator and therefore, the base has no signal at all. The input is applied between emitter and base, the output is taken from collector and base. Therefore, these are common base amplifier. So, Q 3 and Q 4 are common base amplifier, their input impedance is low but their voltage gain is the highest possible. So, as a result you get Q 1 and Q 2 are capable of providing a low enough output impedance. Therefore, there is no problem and Q 3 and Q 4 now provide good gain and this stage Q 5 and Q 6 essentially adds up the two differential signals into a single ended output. So, this is the input differential stage. The output of the differential stage then comes to this common emitter amplifier which this is the emitter follower actually which then feeds this common emitter amplifier with a split gain load. So, this output goes there and the inverted output goes to the other side which acts as a phase splitter. So, now you have two signals which are in opposite phase. So, these two signals then feed a push pull stage which is here and these two signals with a base with an appropriate bias here with this will feed this complementary pair. So, these are actually in the same phase not in the opposite phase. This is a common load for this and this is a split load. So, therefore, this is the emitter follower, this is the common emitter amplifier which is used for feedback and the output of which then goes to this phase splitter and the phase splitter has the other collector as the load. There is a diode slightly more than a diode drop provided by Q 18 to properly bias Q 14 and Q 20 in their forward region. So, that this emitter is the output and this voltage is about a diode just under a diode higher and this p n p transistor has its about a diode lower just under a diode lower than the emitter value. So, therefore, both these transistors are now biased in their forward region and together they act as emitter followers and this becomes then the final output of the operational amplifier. And now, we put all the parts together and that gives you the complicated circuit which is 741. About the only mystery in this is this capacitor, this is actually a miller capacitor which is used for stabilizing this multistage amplifier and because we would always be using a negative feedback externally, this multistage amplifier can become unstable unless this capacitor is put. And the theory of this we can discuss during the question and answer session, since it is already 12 20 and we do not have too much time left. What I would like to do is to stop the description of this circuit here and then we can go over to a discussion session.