 we are looking for light issues. Last time I did quickly show you some technology, maybe it is once better way to show you the exact process which makes IC possible. This is taken from Hertz handout from MIT lecture series so you can go on web and check. Basic idea in all the making an integrated circuit or a device is to allow you selective area processing. That means in certain regions I want to do a processing rest should get masked. So the word itself suggest something has to be masked. So the process which allows that particular area which you want to protect from the next process to go through. This can be created on a glass plate like a photo plate. Normally it is a photo emulsion plates. There are other methods, metallization can also be tried which is what hard mask are. But those masks have already pattern on as if like a negative of the photography film. So there will be dark areas and there will be clear areas. So this idea that the dark area can be opened or clear area can be opened decided by something what we call the resistive use. So for example here is a substrate and I have deposited a film in which I had to do some selective processing. So I say okay fine I code this with a photo resist okay. Something like this and then I put a mask which has this area clear and the other areas dark. So if you look at the pattern this is only cross section but if you look at the pattern it is something like this. This is dark area and this is clear areas. There means light can pass. No light can pass. So this is called dark field mask. The inverse can occur. This area may be clear and the windows may be dark. So it will be called clear field mask. So the mask is kept on this coat is right now kept as if it is kept distance. Normally it is touching or very close to it using what we call proximity alignments. And when I shine light, light cannot pass through black areas only it can pass through clear areas. And if say the kind of resist I have been using is called PPR positive photo resist. So what does essentially it means that the positive or photo resist are generally materials of regimes which are long carbon cross linking chains. Whenever that link actually fixes itself it is a huge circular rings and then it is called unachievable bonding is complete. Whenever chain breaks then you say it is achievable. So the PPR positive photo resist has a property that it is initially hard that means it is completely linked. Whenever light shines photons actually received the links break. So whenever link will break that area will become soft. Soft means achievable. The contrast to this could also be having a negative photo resist which says that initially it is open that is it is a soft resist. Whenever light shines on it it will become hard that means cross linked and therefore unachievable. So the same mask with a different resist can do two jobs. Is that clear or is that fine? Just change the resist or using the same resist the complementary of this mask wherever dark area there you become make it clear. How do you make a complementary just take a contact print okay. So you have a complementary mask. So dark will become clear, clear will become dark. So that same resist can be used for either areas to be open or closed. So if I shine light the resist which is below this clear area let us say it was a PPR become soft. So these area PPR become soft. The darker area PPR remains hard means normally achievable in most of the agents which we use. If I do so then I put that refer on the inside what is called the developer. Like a photography we also develop here. So you push this into developer the resist which is soft dissolves. Resist which is hard does not dissolve. Is that clear? So this part was soft when I put into HN that part got dissolved and since these were the dark areas where light did not go through. So that remained hard. So I removed resist from this area. Now if I want to create a window in this deposited film which is the mask area which I have decided then I start etching now that the film etching itself can start with the resist already on the top. Resist is a hard material it does not get etched in the HN for this film. So it protects this mask itself. So these areas resist of film does not attack. Only which is clear area the etching starts for the film and you create a window down and then the rest area is already protected. Is that clear? And then you remove you call strip the resist. They are HNs which finally can remove the resist. They are normally organic materials some other day some other time what are they do? It depends on the film. If it is SiO2 hydrochloric acid is HN for this. If it is any other metal like for example aluminium goes in orthophosphoric acid are HNs and HNs. So you can HNs HNO3 mixtures. So all chemical HNs all chemical HNs. So remember both HNs do not attack resist and therefore H and normally it is believed and which is what is shown here that there is no lateral etching going on but it will in fact the way it is shown it will be lateral but assume that lateral this depth is not too much so the lateral etching is smaller. But in that is called isotropic etching. We can do any isotropic etching where things go vertically down but then we use gases which call plasma etchers. So the ions strike vertically down. They just etch straight way down. So I remember the resist and I have the window of the film. Now I can say I have films at different areas the rest films I could remove. The converse could have been made if I would have just replaced this PPR by an NPR. These area would have been protected the rest area would have gone out okay. So this is a lithography process goes through. When I say a mask I do this processing. Every time let us say AC mask process is 24 mask. 24 times we will see each time this some different mask and you keep etching some areas. Is that clear to you? So this is essentially the crux of all integral circuit manufacture. Now the problem started the wavelength of the light which is used typically in photolithography that is why it is called photolithography is to be order of ultraviolet light which actually allows resist to expose okay. 2,900 to 4,200 Armstrong's light wavelength which we use. However this wavelength itself if you see lambda is very large right now 4,000 Armstrong is a sufficient wavelength. So if you are reducing your feature less than the wavelength itself then the diffraction and diffraction both starts and the pattern cannot be exactly etched out. So that lithography will not be correct. So you will have to reduce the wavelength of the light okay. So from photo you may go to electron beams which can have then higher energy and lower wavelengths. Then the photoresist will be different. There will be other organic material like polymethylacrytholate. Many others materials can be tried. If you want further lower wavelengths you can go to X-rays. If you want further rays you can go to ions. The larger the mass you pick up the heat it will give to the material will be hard and material will become actually non-tystalline. So one cannot use ion lithography very easily because it will actually damage the vapor itself. But no one wants to really do electron beam lithography because even electrons have high energy therefore they are lower wavelengths so they will also actually damage the silicon below. So somehow what we do we create a mass, this mass using electron beam lithograph which is on a normal glass plate okay. And use that corrected mass and use lithography like photolithography. But the problem there then is how good the patterns transfers. So there are different ways of doing it and now what is the wavelength we are using is called extended UV below 193 nanometers. And there is a latest process which probably Intel will start working this year, EUV okay extended UVs. So these are the things which are going on. The other problem which technology people now getting because of 20 nanometer, 30 nanometers or less is they are such a small this when I actually do whatever reaching the pattern which I see and nothing to do with pattern which was on the mask. So for example I may have this mass actually but what I may get is something like this. Now how do I get that area which I W by I was looking for? So now the issues are, so do a lot we do called phase masking. We do some DSP or image processing. We figure out for different patterns if you have this pattern what do you really get? Do a inverse transform and see if I want this what should be the actual pattern. But creation of that is not so trivial then there is called projection mask alignment. There are many techniques which are tried now for going to less than 20 to 30 nanometers. Lithography was very simple till one micron. As we went down scaling, scaling, lithography we were first heard. So major effort therefore went in lithography process. For electron beam can directly write on the wafer. You do not do any mask. You actually wherever you want you put like electron beam can be very sharply focused through ACM. So I can actually write patterns on the wafer itself but each chip will have so many transistors you write and there are hundreds of chip on a wafer and hundreds of wafer to be done this is called direct stepping. Direct write is very costly because you know every wafer has to go through hours of printing before that is very accurate but that is very expensive. So people who have money and who can sell the chip for million dollars can probably do that direct stepping. Otherwise photo lithography then has to be performed for the larger numbers to be created in one go. Some image processing, new techniques, mask projection printing, many tricks are being tried, lower UVs are being tried, extended UVs as they called and this process is very hard. Right now no one knows exactly what is the wavelength Intel is going to use. The machines are made by themselves. The resistives of their own way and they are not right now allowing people to know what exactly this extended UV will be and can they go up to 7 amperes or 7 nanometers. The problem which we see in real life is essentially called the mismatch problem. We have already seen in our analysis that if beta is delta beta plus delta beta plus minus what can occur okay. We have seen all such variations can create what kind of actual problems for you. So now how to elevate some of them. Not that everything can be minimized, everything can be removed but minimization can be tried. One technique is to get into a layout problem which probably can say some of your mismatch problems. So one first look at into mismatch. Factors causing transistor mismatch as I said they may be number of way because of this it can happen. One of course is I yesterday said there will be many many transistors on a chip. Each mask will have different shifts and when you align they have further different shifts at the end of the day each chip will have different everything different. So misalignment then there is something called misalignment when you fix one pattern over the other whatever you say it is not 100% matched and at this goes sideways it goes further different. So there are issues which is mismatch issues. Now first thing you must do how to model that mismatch. If you can model it partly we can take care in design. Then of course can we control it at the process and the device level like threshold can be controlled to a great extent by different way methods. So we try that. Then impact of transistor mismatch you know one of the major worry in DRAM was or SRAM was the sense amplifier design and there the mismatch created a hell of this 1 0 was never guaranteed then and we are looking fast excess. So there is first time people realize that this mismatch can create huge problem in the reliability of a DRAM. Of course one possible technique is to control at the circuit level. So you know how much is offset you have you try to cancel as much as possible if it is a systematic offset what is systematic way in one direction. So here is something which looks trivial the way transistor works you have a diffusion area because there is no color four colors here but maybe blue I call it red black I call it green this is red and this is green. So normally what is done is first poly is printed etched out and then implants have been done at the age of poly. So this become N plus or P plus whichever transistor you are making and this also becomes N plus but below there is an oxide below all polys will be a thin oxide gate. So since this is the area where gate outside below is available. So this is the channel length and this is the channel width. So fixing this diffusion area or source drain area and the poly width decide the W by L of any transistor. So whenever I show you a green line intersecting then there is a transistor below wherever is the common area okay. So it is called G intersection R. So here is that G intersection R shown this is diffusion or N plus and this is poly which also will receive N plus when I am doing this implants. Now you tend to see three are almost identical as far as if you see the pattern that is a but in real life the color shows that somewhere diffusion is larger some is smaller some is shifted left or smaller shifted right that is not visible so much from the pattern itself. But in reality the process down has created the shifts because as I say lithography process is never guaranteed process. Now this three structures after IC processing are not identical to each and therefore these are so close by to each other and still they are not identical. If you are far away unlikely that all will be of same value okay and how much you can tolerate is your design spec. This is called some other process say hello but let us call it. There is a intrinsic factors which is causing the mismatch which is called discrete dopant effect then there is a interface state fluctuations. Extend it because of the process there is a random variation in gate length, gate widths, upside thickness, implant nodes, implant energy, anneal temperature, gate and source day overlap and spacer thickness. Spacer generally comes in the case of pin fets okay. So there are many variations going on okay. These are called process variations. Designers must take care of process variation. These are statistical in nature. So some statistical analysis should be actually attempted. That is what we do sometimes. One of my PhD student work for this process. How to correlate process variation with circuit performance okay. As you reduce the channel let us say the concentration because of the VT which you are adjusting is such that the volume there let us say 10 to the power 15 for sake of numbers. The channel length is less than 10 to the power minus 5 centimeters, 0.1 micron or lower. So what is the volume? 10 to the power minus 15. If it is lower it will be 10 to the power minus 16, 17 per cc or cc. So what is the number of carriers there? Less than 1 okay. So one cannot guarantee say where is the electron, where is the carrier okay. So there is an issue which is called dopant effect okay. Random dopant effect. It will affect the off current. It will affect the on current that is the saturation current. It will affect the thresholds. It will affect the sub threshold slopes and it will affect the transconductance and all are seeds and any other plastics which are area dependent and dopant dependence will also get variations. So if you see a device parameters which worries you most at the circuits because of the process variations all will be moving from one and please remember our worry is on chip variation, chip to chip variation, river to river variation and run to run variation. Run means 201, run next 200, run so run to run variation. So huge problems okay. We do everything fantastic. We say everything is controlled and then we see all variations. So if you look at the impact of process parameters on circuit yeah already I said current capacitance threshold variation in threshold. So they may change speed dynamic power static power and the worst is the yield. It will actually reduce the what is yield. I decide this is the minimum specs I will expect okay. Anything goes beyond that that chip is not up to the mark. So that that chip is wasted. So we say yield. So at then if you find your yield going below 50% the whole process is of no use. This statement is very interesting that it seems as if there is a direct relationship but there is a non-linear relationship because all the expressions are non-linear at the end of the day. So it is very difficult to actually predict which one will hurt you most and when and that is the analysis someone has to do is called statistical analysis. Of course as I say some of them are correlatable some are uncorrelated processes and then it is much difficult to actually predict things okay. I will not go into detail of statistics. This is an area of our students PhD work just to give an idea if social varies and there is a variance which is different for different processes sigma of delta VT. If you see this term and I had taken an example of ADC. ADC is one of the major device in the analog to digital converters which are most mix signal most important chip or circuit. So if you see if I have a 7 bit ADC the sigma allowed to me is around 5 to 6 okay. Anything below let us say 5 yield is okay but if you look at the 10 bit ADC even a half a millivolt shift of sigma the yield may go down 0. So the decision of making even in this was done only for 0.25 microm process if you do as a further down God knows what will happen if 12 bit or 16 bit ADCs are used somewhere. So the precision and mismatch are very very crucial in analog designs as one example I am showing you this is how the sample hold actually changes the equivalence of analog to digital. So 1001 pattern may become 10111 kind of thing and which will not be representing the actual digital data for the analog okay. So there are issues which essentially process people know that at the end nothing will come and therefore layouts become extremely this is all just to tell you all that why layouts are so crucial at the end of the day and layouts are the only thing which as a designer we create the W by L sizing and then when you lay it out things may work may not work if you have not taken enough precautions on that okay. As I said basic layout design techniques should be taught by Professor Mother Desai's course that's the issue where digital designers should learn more about that this course has no such area left in my course where we say layout design. Other layout editors is a part of any design process okay. So is that point clear why I am worried about mismatch so much because money economics is worrying 10 bit no yield then what do we do we made so many of them and there is none working well. So that is the issue which companies like nationality everyone is worried about who sell ADC chips or analog is that okay the issue is clear to you why mismatch is real worrying. So there are issues in layout one is called we will come one by one whatever is now following I have been figures I have been taken from Razavi there is a chapter on this mismatch word itself is mismatch there so look for that chapter and I will show you what is the worry there the issues of orientation of layout symmetry adding dummy layers unit cell reputations and the last but not the least the last but one is most important called common centroids and avoiding interconnect resistance these are the issues which as a layout designers you must be by the way design when you design a chip till you make the before the metal mass comes the process is called front end that is designers W buyers have gone in okay this is called front end the rest of the process to make interconnects back end whatever and this all issues related to this these are called back end processes these are torturous boring but they are paid higher than front end engineers okay because there is testing is the last part which they come to it and there is where they start looking things worse happening okay so here is something typical this is shown to you there are two devices shown here one can see from here this is the poly that is this is the gate which is shown here okay this is a P plus implant this is an N plus implant okay and one can see right now it is only one trans shown the other part I have not shown this contact is essentially called metal one there are more than one metal possible each metal is separated by oxide on the top so what we did is for this a P plus implant for shows we did here what we now did that opened the contact to the gate to the source and to the drain okay so this is essentially called active regions and this may and the any so the method is any metal one normally runs vertical any metal to runs horizontal normally they are not running in the same direction or no angles they all should never be at 45 degree or 30 degree parallel cord this normal XY system is always use these lines are called Manhattan lines why okay some of you might have visited USA New York Manhattan has avenues and streets exactly Santa Cruz if you go some way in Mumbai avenues and streets actually copied from there so Manhattan has all roads like this and all streets like this so this is called Manhattan lines so the way right now you can see there are different directions I am taking metal out okay and that is not acceptable to me okay because if I do this process for n number of times it will show you much more variations on this unless I am symmetric to something so I show you what symmetry is show so this kind of interconnects are not treated well where you will pick up connection anywhere anytime and run anywhere anytime it is not a good way of putting your layouts okay this is given in other book specifically written so you do not draw it you can look into figure there the another issue which which is called antenna effect and one can see this is a normal transistor these are two devices shown here for example polyps please remember these are two transistor in series do you see them source drain source so drain of the two are same but it is only a matter of decision to say because they are symmetric this also become source drain so you say connect source and drain in between or call drain of both together whichever way you feel like as long as the devices are symmetric there are other devices called asymmetric those devices like LDDs and others they do not have source same as drains do not connect like that now what we do is though they look to be in series essentially what does two transistor in series means equivalently of a one transistor what does they show two transistors okay before we go to there maybe a simple figure can explain you this is one possibility same connection second is this equivalent of what and this equivalent of what in this case the lengths are doubled widths are same or whatever you said in this case widths are doubled and lengths are same so transistor sizing whichever you come normally do not put huge size transistors break into either series or parallel combinations so that the uniformity of each probably is much more maintainable there is a word which we use in layer which is called aspect ratio what is word aspect ratio let us say this is the line length this is small much smaller compared to this so whenever I do etching I cannot guarantee etching here to here same because I am going through a huge length okay so the length here may not be same as length here this is called aspect ratio issue so don't run two long issue lengths break into as many as you want either using if you want W to be higher or length to be higher use either of the methods to actually break into smaller number of device large number of devices to equivalently putting for a digital people those who are doing digital course this also has an advantage this is called gate stacking this is one of the most important technique of reducing power in a digital circuit okay so now what we did this is a similar transistor shown here so one method was that okay you connect common gate together and put one bit metal there is a suggestion that if you have a single metal layer connecting to the contacts here and you run it longer as we did here it gives like a some kind of a resonator circuit on a oxide in any insulator if you run a metal line it acts like an antenna okay so radiating system this is what we do in MIC instead of there in alumina substrate or other substrate your silicon silicon dioxide substrates so it runs like an antenna so radiates power so much of the if you calculate the pointing vector here the huge power loss is at the same so to derive this okay the metal one where the contact is coming which is a dissimilar discontinuity as we say you make it that small and run another metal on the top to oxide through a window to that which will actually take care of those contacts away from the actual this so that the radiating patterns will be restricted only here which has a smaller power loss this is called antenna effect so yeah designers if you learn like this yeah in some frequency it may still work but higher the frequency you go this will be one which will say there is the radiation is much more than the power delivered to you okay so these are issues another issue which I just show random this connection so one method is for example this is called surrounding you can see here what did I do there I have a couple gates so here also have a two gates finger these are called fingers common point here and the drain contact is taken in between this is rain and this is source is that clear source on the outside and center is the drain so I have to drain here source outside and connected them also okay this is still a single transfer please remember sources are common drains are also connected so what is it means it is parallel transistors to are connected here is that clear to you this is essentially how is called folding or finger structures you can do larger numbers if you have large number of W bars to be connected put equivalently this sources on the top drains on the opposite call source are same so whichever is source which are his name and in between run colleges this exact okay so you can make can you now see these structures are more symmetric you take symmetry across this or you take symmetry across this so there is a symmetric structures can be created by actually folding them okay fold properly as much as you can and then see to it that symmetry is some way attained okay this called multi-finger transistors okay the same statement which I made if you are very large size transistor wide you can have two sets of them and in between connect multi-fingers and then connect okay so there are larger the size tricks to be again you can see from here it is trying to get into more symmetric systems our ultimate image getting symmetric systems why I am looking for symmetry anyone because whatever processing I do if all sides is similar then they are likely to duplicate everywhere the same aspect ratio issue will never come into picture okay so larger the fingers I create more likely I will get symmetric structures and more symmetry means much more uniformity of etching if lithography is possible okay please do not draw because it takes a hell of time and these figures are available just to explain you what is going on maybe I will put it on the web if you wish the differential pair which is the most common circuit you will use you can see from here one method is you have one device here you have another device here now you can see I have one poly that is one input gate is like this but the other is I made like this now it is not symmetric the source I made common one drain is going but the other drain is away from each other like this this length are different than this length for the contacts okay so what should I do then I should either do this or I should do this now you can see identical drains identical source so if you take symmetry across this defam have a symmetry that is what we have been all the time ceiling defam has a symmetry requirement so if you lay it out only then the defam symmetry is easily accessible to you in this you can break more devices if you wish but fold it now this is called folded symmetry do like this and again to the but again it is symmetric symmetry is all that I am looking for any lithography process okay and therefore any layout I made has much more worry in symmetry points is that okay there is another very which analog people gets problems into here another problem which we observe is called like when I was making your internal device I have this oxide and gate delineate at first and then implant source drain but it is the way implantation process goes many of you might not be aware those who are doing technology course in our other they might have seen already implants there is a columnar tube may be of any size of 8 inch or 12 inch through which electron beams are sorry ion beams of particular dopant or water implant you are doing is actually getting focused by electromagnetic fields okay when it comes to the focus beam the wafer is orthogonal to it okay but the distance when the focusing is done by lengths electromagnetic lenses the wafer is does not have exact angle of 90 degree you have to keep it at least 3 to 5 degree of some other day it is a part of requirement for good implants now if I am younger this will get lesser this will get higher because focusing here will not be there this is going to happen so I will treat the beam anyway 3 degree beam at least I will shift maybe 5 so I will not actually have 90 degree orthogonal beams further I have to scan them when I scan them it is like a normally normally rasters are came but some way some people do vector also so when I flashback there is a residual implant comes so when you come back to original position there is a residual system so on the left and the right you do not get identical implants the reason is you can now see this n plus and this n plus hour look at say here it is very internally very small here internally it is larger larger the inside part essentially means capacitance is increasing it is called drain capacitance what is the problem in drain capacitance increase your pole actually will move it may become dominant which wasn't there so what we do now in this this is two possible structures which are there so we do something very interesting you have these two transistors to make you actually put another two transistors okay so now this transistor on its left sees another transistor this transistor already sees another transistor this also sees another transistor if I take it away this side is different from this side in between so what I say is to create a symmetry I actually create dummy transistors on the left side or right side okay so the it is called bias so whatever bias I see on the one side I see exactly identical on the other side these are called dummy transistor at least if not put transistors at least put polylines this poly to this poly because there where the implant age comes so the minimum requirement in analog age every transistors if they are not together they must be surrounded by parallel polylines to create symmetry for implants is that correct yes you can see from here if I have a large beam coming if I I don't have this there is a energy going other side if I have back here I have energy only equivalently on both sides okay so to keep energy distribution of the implant same all source drain side I must have also the both sides okay these are essentially walls for that dummies as they and they are not doing connected anywhere these are dummies if you put transistor your area put trans itself if you don't have area at least put polylines everywhere to protect your internal parts is that clear so these if you see analog this is what is needed in digital why we are not interested so much because noise margins are sufficiently high any such things goes there it will probably take care at the end of the day there is no margin here anything goes wrong amplified so that is very even analog this word symmetry you can see from here there are two transistors and I am connecting a metal something like this but no connection on this side okay so don't do this you do metal one and metal two and if you feel this is not needed don't connect it anywhere is that clear if m2 are not needed don't run it anywhere but mere transistors so any time you do on the left useful even if it is not required put same thing on the right to be have symmetry structures now I must tell you what is my worry with this is the next one which I will do as a circuit this maybe you will get this figure this is also one matching problem if one is vertical poly here is horizontal but never do the same run always same direction if you have this all of them should go horizontal or all of them should be vertical of course preferably do everywhere the same but other cell you may do change also if you need connections the other side so but in the small area whichever cell area you are creating symmetry has to be 100% maintained this is called orientation effect there is something which results but then I will give some mass behind what we say from left to right there is some variation called gradient of the sizing for example okay because of the process whatever I do actually there is a gradient in the process now what it can create here is an example which I will show you assuming right now linear gradient linear gradient means it is much easier in real life it may not be even linear gradient let us say the size of a pattern is this is equal to you know slightly equal to twice the size of B and let us say there is a gradient on the left to right linear gradient so when actually I will print this this will not remain double that of B is that correct this is essentially worrying us because then we decided to areas to be double one or double out of this but in gradient this will not allow this to happen so what we did is some interesting feature of course there are many other transistor should have a area should have been shown but I just chose for one let us say the gradient is y is equal to mx plus c linear gradient okay for even let us say a is broken into two areas a1 and a2 so I write a1 is mx1 this is for a1 mx1 plus b b is the intercept a2 is mx2 plus b and b is mx3 for this plus b now if I write a1 plus a2 by b I get mx1 plus x2 plus to be by this however this does not become twice unless this becomes 2 this can only become 2 and the x3 is equal to x1 plus x2 by 2 okay now this is an issue this is an issue x3 plus x1 plus x2 must be average that must be equal to x3 now this problem which we see if x3 is not x1 plus x2 by 2 a1 plus a2 by b2 is not equal to 2 either so what we now do we say okay put x1 minus x2 and x2 minus x3 same or essentially saying x2 should be x1 plus x3 by 2 if I do this x1 plus x3 by 2 and put b here okay a1 a2 is across this similarly a2 should come on the other side and a again so this is called common centroid okay this is called common centroid so if you have a circuit broken into a path I do not know where I have a figure but I will show you what it shows there may be blocks here along this axis sorry along this axis along this axis along this axis it is identical okay so let us say variation from this is even be for example variation here opposite will appear here if I connect them then variation in the two is getting cancelled is that clear so I do always common centroid breaking into blocks so that the effectiveness of variation can be cancelled or at least minimize so all analog designers should make their layout common centroid so 4 by w by lk so those okay so that so in defam also you have two transistors m1 m2 m1 by 2 m2 by 2 m2 by 2 m1 by 2 now you can see it is common to all four sides and therefore it will show minimum gradient effect this is an issue which is called layout issue which if you do not take care then the problem will be the sizes of what you actually were creating are not getting transferred is that clear so one difference from digital hardware analog is every layout in analog is common centroid okay that gives the maximum symmetry at least if not that do some symmetry at least preferably use common centroid but at least symmetry you create minimum that is what is expected here is something very interesting data which is given by not data calculations given by the same thing can be explained from here you have four transistors m1 m2 m3 m4 let us say due to the gradient it has a oxide capacitance of C ox it is C ox plus delta C ox C ox 2 delta C ox this is C ox plus 3 delta C ox so one possible technique is you connect these two and you connect these two so what is the capacitance you are going to get ox 1 plus there is no 3 so 2 C ox plus 3 C ox delta C ox here 2 C ox plus 3 you do this way you connect this and this and you connect this and this then C ox 2 C ox plus today 2 C ox plus this so essay of course this become 4 so depending on how much symmetry you are gradient you are expecting you must decide which transistor should get gate connections which transistor should not we should be closer by so don't put connection at least this this is the worst connection this is 2 C 2 C ox plus 1 this is 5 delta C ox it will come so either try this or try at least this so that you get symmetry as close as possible which is created due to gradient in the process is that clear so now all that I am trying to show you that why in analog layouts it is different from so what you say which is the famous layout editor in the case of cadence if you see analog designer there is a separate shell in which you work if you are digital designer you work in a different shell the reason is this layout both I virtue so but they are different virtues okay so it is actually designed quite analog the other is designed only for digital hardware okay so please use it don't use magic because magic is it has no connection with anything neither analog nor digital it is only a graphic editor okay so there you can do anything you like physically by forcing it in real life we are not allowed to force ourselves system will actually tell you you are going wrong but you are always possible to overruling this is allowed okay and but if you do that you are taking a big risk on yourself okay the circuit which I showed you earlier I should have showed now this is called common centroid is it clear half M1 half M2 half M1 you can even flip this okay even better So this is called common centroid okay yes centroid is ka okay the last part of this we are missing transistor so far in analog what else you need resistors and of course we also need inductors but this course we may not talk about them this you can draw this is not a very big circuit you can see from here this RS and RD are not the transistor resistors I put these are essentially the resistors which is source drain area resistors actually I should also put RG in case if you need okay so how do I do this if I n well device area there I yesterday said you start with a piece of thread and create a deep area which is called n well well means 5 micron down or 3 micron down that is why called well please remember in circuit only first half a micron or even lower is the actual surface area you will use surface depth you will use all devices are within 5000 Armstrong's okay then you do not need further then why do you need so much thickness of silicon because extremely fragile and to handle it at least you should have some stability so far 12 inch paper you can now understand why it should be very relatively much thicker because 12 inch paper will huge mask and it may just break jokingly bashing okay so you must actually put some this so that it works so typically one and half millimeter to 2 millimeter thickness wafers are used for 12 inch for 3 inch wafers 250 microns are sufficient thickness but the device is going to be within less than a micron but the wells are normally slightly below this that kind of device has to have substrate kind of effect for source and drain so the wells are typically 2 to 3 microns all the time it will be used to make it 5 microns so if in a n well if I make n plus contacts n well would have some sheet resistance or rho by T so RS is known this is my length there is a width in the inside this so L by W into RS is the resistor value so adjusting this and adjusting the second parameter width of that I can decide how much is the resistance I want this since it is a P substrate this is a NP junction so there is a depletion layer going on is that clear this depletion layer should not connect okay this is called punch through the 2 register will get connected okay so there is a rule up to which 2 registers could be brought together okay normally registers are created due to the implant area available to you so which are the areas available substrate n plus implant P plus implant the odd wells so they are 4 RS is available to you depending on the substrate of the highest lowest concentration highest resistivity so if you just take on a substrate to a gardening you create and put a contact there you can create large registers okay but normally not used whenever you need large register which turn which way you use you actually create transistors in saturation region and you have large amount of R can be created the last part of this circuit is capacitances you can see from here a capacitance okay I just told you last time maybe before I go there are number of maybe we should use a fresh sheet let us say this is my first layer I am making an internal device I open a contact there is a gate here there is a poly here these are all oxides these are contacts this is the first metal I took for source drain and gate of course is in the vertically outside so I put another oxide on the top okay then if I want to contact with this I open a window in this oxide and run the metal from the top which then we will get contact to the low range if I want to contact with this metal I put another oxide on that and open a window here sorry open a window here where this next metal actually gets connected to the next metal at no time this can directly be connected to the lower down you must connect to the next nearest metal layer okay the catch is whenever you open a window here there should not be another window below okay because the processes will then maybe inter merging somewhere so if you open a contact here open somewhere here the next contact in the next layer all contact should never match each other they should be at separated positions okay but you still go down and connect these are called metal 1 metal 2 metal 3 metal 4 metal 5 metal 6 metal 7 and we are now going up to metal 9 okay why we need large numbers because many of the processors are DSP in particular you need huge interconnect lines going from one place to the other so our metal lines are similar we can go as many metals of course there is an issue why not beyond 9 why not 100 oh so the problem starts at the total resistance for the length of interconnect you go through this so high that the voltage will drop there itself nothing will go down okay so there is a length minimum you can you have to restrict to so in capacitors normally between two metal layers there is an insulator so there is a capacitor wherever you make two contact there will be a capacitance associated but the way we actually do the capacitance is in our base is the following you have this process of transistor but let us say in the top first poly line has been created for the gate poly 1 of course all poly will be protected below by oxides then sorry this poly I should use this then there is another oxide layer on this poly I created and I put another poly here this is called poly 2 is called double poly process not all processes are double poly all flash processes flash ROMs or they all are double poly but not all CMOS processors double poly but analog CMOS processors are always double poly so extra money for that so this is M I am sorry poly oxide poly that is the most common capacitor used in analog designs created in analogs if you do not have one there is another way of doing the same thing which I will show you instead of quality is poly this is called metal 1 and this is metal 2 or 3 or 4 to restrict the area of metal so you have a capacitor down which is called MIM capacitors which are called MIM capacitors please remember once I use this line I must break it somewhere because otherwise there will be one line everywhere so the area for each has to be restricted to make a standard area of capacitance is that clear so restricted area will make standard epsilon A by D kind of thing so either MIM capacitors are used or poly if you have to poly process poly 2 to poly 1 is what is used often in our processes most people have poly 2 if they do not have then you use only MIM digital process will have MIM because there are 7 layers available 9 layers available now there also it is decided that the capacitor should be closest to the point where the node capacitance is to be created otherwise for us parasitic capacitance will actually shift our volts or zeros so in analog the position of capacitance to choose has to be which node you are actually looking at so closest to that you actually bring your capacitors instead of having a large capacitors you can actually create small capacitors of C 1 C 2 or C 1 and then connect in a fashion but we see this capacitance is not connected to anywhere these are connected 6 6 2 so 8 capacitors are connected to give 8 let us say this has a capacitance of 1 or C this is 8 C is that clear this is C and this all are in parallel made so they are 8 C very things such things are needed in a switch cap circuits you actually will use 2 such capacitances this will be 8 times this okay so if you want to do this circuit use this kind you make around now all that I have not shown and even the why I have not shown you need dummy everywhere all areas must be put dummies all around so 8 of them and for the 8 of them around just to keep them identical to each other is that clear to you so this is something not shown but please remember every this has side should have equal and dummy top bottom side everywhere so this is late but then you should have here here at least poly as I said here here everywhere okay this is essentially is called 8 to 1 capacitance ratio this circuit is creating 8 to 1 capacitance ratio 8 from this one from here okay change this combination and you can create any other ratio as well the last slide for the day as well as for this layout part is this interconnect routing now this is an issue which is available it is it is equally troublesome in digital but shown only for analog here let us say you have a current layer which is mirroring so many of them like you have the m6 m6 m5 m so much even in open okay now whatever way I use this line which is called the ground line okay or VSS line one can see from here between here to here there has to be some metal line running and it does not have 0 resistivity okay it has a finite resistivity so equally saying from here to here there is a resistor from here to here there is a resistor and if this is taken little longer so this potential will be different from this potential when the current is sinking through is that correct these are things so when all of them are sinking because of the mirrors this sink will be different from this sink is that correct because the available current to you is not the voltage drop is actually created across okay this is called ground based resistance problem in the case of digital even if there is no mirror because of this we see what we call ground bounds the actual 0 shift to a higher potential so your noise margin on 0 become worse sometime even not there okay so it is called ground bounds similarly it comes from the power supply sites called power group it comes down and your upper noise margin also can go okay so these are issues which layout people so what should I do for R to be minimized increase the area so thickness of this metal analog grounds are therefore at least eight times that of digital grounds thickness wise at least eight times if you see analog ground huge plates kind of grounds are provided so that the arms are as small as possible is that clear that is the trick we are but what is the penalty area you lose but at least survive otherwise you do not survive okay so that is the issue in the case of layouts also now I will say you do not use single references okay even if it does not matter if you run through as far as circuits things but run another circuit ahead another mirror and run ahead okay so break into number of references in case you feel too many such things you are learning from one point so do not run from one point this is also done keep referring are actually putting VDD lines on four places if you see a normal there will be at least four VDD contact and four VSS contact okay they will need only one VDD and one VSS but the distance from each of them may be different so at least four commerce you create four VDDs same a four VSS this is done even in so jit now you think you can tolerate keep as many then repeat again that is extra area but saving your life for that okay so these are you now clear to you that why I spend time in analog layout is the issue is that things can fail at the end just because you are not aware or you are lax in layouts okay things will finally you may show you 0 okay so all analog designers must spend their 50% time after so-called simulation results have come in actually getting the best layout okay try any number of times I started and put it every verse values for them and see where it still works for you okay increase the ICMR decrease the ICMR swing the power supply 5% to 10% where you keep seeing that everywhere circuit is all bounds it actually will increase temperature from minus 25 degree centigrade to 125 degree centigrade run whether all corners it works then keep modifying your layouts till you find most of the corners are met so that requires hell of an effort okay most of our student copy from the last year thesis because he must have seen some and no one has seen in the first so the worst things are going on last 10 years okay focus of this finishes much of the issues on love there are many more things I can tell but forget this we will start with next Wednesday the last topic of this which is called oscillators we are done lot of amplifiers at least see oscillators actually oscillators are not not just the VCO which we are interested in we must do something called PLLs phase loop phase loop blocks but I think in next 3 hours 4 hours I do not think I will be able to catch up with PLLs but I will at least tell you how PLL works on Friday so on Wednesday I may show you VCOs on Friday I may show you how PLL picks up why PLLs are essential with VCOs okay.