 Hi, my name is Augusto and today I'm presenting about the NCFMC Carrier General Purpose FPG Card for Fast Data Acquisition. So to start I will talk about a little bit of history. The development started in 2011 and was inspired by the CERN OpenHard initiative, so we decided we would try to release our designs as open source hardware back then. It was intended to be used on the bin position monitoring and fast orbit feedback systems for the forthcoming new Brazilian synchronized source, CERIOS, and it was developed initially under contract with the Warsaw University of Technology and last year we released version 4 of the hardware in a partnership with the Warsaw University of Technology and Creotech. So our goals were to promote a common hardware platform for fast data acquisition, real time processing and that is flexible enough that you can use in a wide range of applications. So for example we use the NCFMC Carrier for our bin monitoring position system and fast orbit feedback but I know that folks at the Warsaw University of Technology are using it for quantum computing applications. By virtue of it being open source hardware, you can avoid vendor locking. So if you want to produce, manufacture the board for a different vendor, you can. You can make modifications to suit your needs and this is good because it also alleviates some of the problems we are experiencing right now with supply chain problems. You don't depend on a single vendor for this hardware and from the start we decided that would be a good idea to follow open standards whenever possible so we didn't want to invent our own platform and try to stick with is already industry standard. So what is micro DCA? Micro DCA is short for Micro Tagalic Communications Computing Architecture is a descendant from the advanced DCA standard. It is an open standard and it's like the standards we use in desktop computers but for high availability systems. It offers a remote management via IPMI and it has a very flexible architecture. So in a typical micro DCA system you will have a crate that is this metal case on the right. A crate can come in different configurations, different number of slots and you can buy it from different manufacturers and inside the crate you will have a MCH that is card here on the left and is responsible for managing all the hardware inside the micro DCA crate. It manages the power, the clock routing and checks the temperature sensors, the voltage sensors and allows you to control the crate remotely. It's kind of like BMC if you are familiar with. An MC stands for Advanced Measuring Card. The board we are talking today, the MCFMC card is an MC. I will call it from now as AFC to make it short and the MC is connected in the front slots and it connects directly to the backplane. And then there is the RTM that is a board that you will fit in the back of the crate and it connects directly to the MC. So just to give a quick harder overview, the AFC comes with Xilinx Arctic 7 FPGA. This FPGA has 16 high speed transceivers for which we are using for PCI Express. The order 12 you can use for any application you need, you can use for Ethernet, you can use it for some special custom made serial protocol. It has 500 IO pins so you can connect plenty of hardware to this FPGA and it has 215,000 logic elements. It's not a huge FPGA but it's quite powerful. It comes with 2 GB of DDR3 memory so mainly in some applications that you deal with digital signal processing you may need a large memory or when you need to do fast bursts of data acquisition it's very useful. It has two general purpose FMC slots. These slots are standardized, you find it typically on FPGA development kits and these slots you can design your own hardware to fit there or you can buy some off the shelf hardware also. You can find one rear transition model or RTMs slots that you can fit another board if you need more space for your hardware. It comes with Cortex M3 microcontroller that is dedicated for housekeeping so it reads the temperature sensors, the voltage, current sensors. It also allows configuring the clock switch so this board has a clock crossbar that you can route clock signals to and from the FPGA. It comes with logitor clock oscillators and it's wide-rebed capable. Wide-rebed is a timing network protocol that was developed by CERN and it's useful for synchronizing devices with sub nanosecond precision. We don't use it but I know that some people are very interested so the AFC is capable of doing that. So the AFC V4, the last release, had a lot of hard bugs fixed. It has automatic JTAG configuration so what this means is each FMC card and the RTM card can have the JTAG chain routed to it but if you disconnect each card, the FMC, the JTAG chain will automatically bypass the disconnector so you won't be left with a broken JTAG chain. It has a simpler clock crossbar configuration and the FMC microcontroller was upgraded to microcontroller from the same family but with more flash and RAM. So the design files are available in the open hardware repository. From now we didn't merge the version 4 to the master brand so if you want to look at the latest release, please check the CTIFC for a branch. It's licensed under the CERN open hardware license version 1.1. We might update this license to the version 2 that it has a better wording and it's more clear what you can, what you cannot do with the hardware. So openMC is the firmware that runs on the MMC microcontroller is responsible for providing an IPM interface to the IFC so the MCH will talk to this microcontroller, request a sensor data request if you want to do a hot swap or something like that and it manages power for the FPGA, the FMCs, the RTMs and also configures the clock crossbar as said previously. So here is the repository we are right now doing a huge refactor to make it more modular so it can be more easily ported to different hardware. So the board support package is a basic project design. It defines the pin mapping, it supports PCI Express and the DR memory. It uses the HDL MAKE build tool for synthesis and simulations, it's very interesting too because you don't need to do directly with the Vivado IDE, you can just write some Python files to describe your project where your sources are and how to build them and the HDL MAKE tool will generate a MAKE file that automates all this synthesis and bit string generation process and with that I conclude my presentation. If you have any questions please reach me and thank you.