 Hello, Myself Ravindra Chavan, Assistant Professor, Department of Electronics Engineering, Vulture Institute of Technology, SolarPort. So, in this session, we will discuss how to interface the data memory, especially it is of RAM type with the 8051 microcontroller. So, at the end of this session, the students will be able to apply the concept of data memory interfacing in controller-based system design. The outline of the session will be like this. First, we will go through the memory organization. Then, the pins provided for the memory chip interfacing of data memory, especially the data RAM with microcontroller 8051. And then, we will see how to read and write the data to or from the external memory. So, the first, we will see the memory organization. So, in the memory, the number of bits that a memory chip can store is called the size of memory or memory capacity. Memory chips are organized into a number of locations. Each location can store 1 bit, 4 bit, 8 bits or even 16 bits depending on how it is designed internally. But today, whatever most of the memory chips we are having, all these memory chips are capable to store the 8 bit in one location at one address. So, memory chip contains 2 raised to M locations where M is the number of address pins. Each location contains N bits where N is the number of data pins on the chip. So, the entire chip will contain 2 raised to M into N bits. Means the number of address pins and the number of data pins are depends on the size of the memory chip. So, depending upon the number of locations, the M will be coming out. And if each location contains or if each address contains the 8 bit, then the data pins required will be 8. Now, suppose for example, given memory chip has 14 address pins. So, memory is having the 14 address pins and data pins. So, what will be its organization and what is the capacity? So, the memory chip has 16384 locations. Why? How this figure comes out? 16384. It comes out because of the 14 address pins. Means M is equal to 14 and 2 raised to 14 is equal to 16384. And each location can hold 8 bits of data. Each location can hold 8 bits of data. This we have concluded because it is mentioned that this chip is having 8 data pins. So, this gives an organization of 16384 by 8 bits. Which is also represented as 16k by 8. Or sometime we can also say that 16k byte. The size of this memory is the 16k byte. Then the pins provided for the data RAM. So, the address pins are there, data pins are there and the control pins are there. Now here as an example the address pins are shown like A0 to AM. Now this M is depends upon the number of locations. Then D0 to DN. N is depends upon the number of bits per location. If each location is capable to store the 8 bit then N must be equal to 8. Means there should be the 8 data pins. So, read control signal is required for read operations. Now what do you mean by read operation? Read operation means the data will come out from the memory. And it will be transferred or it will be taken by the processor. Then the write control signal is there. Which is for the write operation where the data will come from the processor. And will go into the memory chip. And this CS bar which is called the chip select signal. So, this signal must be active all the times. If this CS is disabled or if it is at the logic one. Then this entire chip will be disabled. Now the required pins of the 8051. Required for what? Required to interface with the data memory. So, the port 2 is required because this port 2 is here. The port 2 is having the alternate function as A8 to A15. Means this port 2 is providing the higher 8 bits of the address while accessing the external memory. Similarly, the port 0 is having the alternate function as AD0 to AD7. Means port 0 is providing the lower 8 bits of the address as well as the data. As well as the data while accessing the external memory. So, the port 2 and port 0 are required. Then the signal called ALE address latch enable. This signal is generated by the 8051 microcontroller. So, this is the active high pulse type signal. The ALE signal is high when the microcontroller is putting the address on the address pin. And when ALE is 0 it indicates that now the data is available on AD0 to AD7. Then the two control signals read bar and write bar which are multiplexed with the port pin P3.7 and P3.6. So, these two are also required for the interfacing for read and write operation. Then how to interface a data memory chip to the microcontroller? So, as far as the physical connection or the physical interfacing is concerned, it's very simple. The data pins of the microcontroller should directly connect to the data pins of the memory chip. Control signals RD and write from the microcontroller should connect to the RD and write pin of the memory chip. And while connecting the address pins, the lower bits of the address from the microcontroller go directly to the memory chip address pins. And the remaining upper one should be used to enable or should be used to activate the CS pin of the memory chip so that the memory chip will be enabled. Now, how to select or enable the memory chip? The easiest way of designing the decoding circuitry to select the particular memory chip is the use of NAND gate. So, the CS pin is active low and the output of NAND gate is also active low. So, while using the NAND gate, you connect the lower address bits directly to the address pins of the memory chip. And connect the remaining upper address bits to the input of NAND gate with high address bits directly and low address bits through NAND gate. And connect output of NAND gate to the CS pin of the memory chip. Now, here the one example is shown the address pins are 12. So, A0 to A11 pins will be there and data pins will be 8. So, D0 to D7. So, here the D0 to D7 this is the data bus. Now, as this memory is of size 4k. Now, to address the 4k, how many address bits will be required 12 because 2 raised to 12 is equal to 4k. So, that's why this memory chip is having the pin A0 to A11. So, whatever the A0 to A11 from the 8051 will directly go to the address pin of this memory chip. Then remaining higher address bits that is A12, A13, A14 and A15 will have to use to select the memory chip. Now, to select the memory chip this is the decoding circuitry used where the simple NAND gate is used. Now, here the starting address we have assumed 7000. So, this 7 means A12 is 1, A13 is 1, A14 is 1 and A15 is 0. So, high bits are directly connected to the NAND gate. Low bits are inverted and connected to the NAND gate. So, when A12, A13, A14 are 1 and A15 is 0, then NAND gate output will be 0 and then the chip will be enabled. Otherwise, chip will be disabled. Now, we have seen that for port 0 the alternate functions are AD0 to AD7 means port 0 can be used for address as well as data on time shared basis. So, during the initial portion of the operation address will be available on AD0 to AD7 and in the later portion of the operation the data will be available on the AD0 to AD7. So, these address and data lines need to be separate to maintain the address on the address bus throughout the operation. So, for that we can make the use of ALE this signal. So, this ALE is high when the address is available on this AD0 to AD7. And now here the latch is used. So, this latch is enabled when this G signal is high. So, when ALE is high the latch will be enabled the address on this AD0 to AD7 will latch here AD0 to AD7. And when ALE is 0 the data is available on AD0 to AD7. So, that will we can take out here as a separate bus. Now, we are having the separate bus for address as well as for data. So, this is the overall interfacing schematic. So, here the example of 8K memory is shown. So, RAM is of 8K. So, for 8K how many address lines are required the 13. So, it should be A0 to A7 used here and A8 to A12 are used here. The remaining lines A13, A14 and A15 are used for decoding logic. So, decoding logic will be depends on your the address range. And read bar is connected to read bar. Write bar is connected to the write bar of the memory G. Now, one thing you have to note here the data transfer happens only between accumulator and the external memory. So, to write the data in the external memory first it is required to take that value into the accumulator. And from external memory the data will come into accumulator only. So, you just think and write an instruction to read a byte from external data RAM from address 0100 and to store at an external address 0200. So, you just recall the data transfer instructions and you write the instructions for this. So, first our source byte is at address 100. So, you load this 100 into the DPTR register. Then move XA at the rate DPTR means the byte pointed by the DPTR register means stored at address 100 will transferred into the accumulator. And then from accumulator you transfer to the address 200 in external memory. So, again load the DPTR with 200 and transfer it. So, directly memory to memory data transfer is not possible. So, from external memory you read into the accumulator and from accumulator you write into the external memory. So, references used are Majidi's book and the Ajay Deshmukh book. Thank you.