 Hello everyone, myself Prithviraj Pithambe working as an assistant professor in department of Electronics Engineering at Vulture Institute of Technology. So let us learn today one of the favorite LPC1768 micro-motor architecture and its features. At the end of this session students will be able to illustrate the architecture of LPC1768. Also they can list the available on-chip peripherals on this micro-motor. So this is the outline of this presentation introduction then architectural overview of LPC1768 and the features of this micro-motor. So LPC1768 is a very very popular micro-motor available in the market which is based on Cortex M3 processor which is 32 bit micro-motor. This processor core is based on ARM version 7 M which is micro-motor profile hardware architecture. So ARM provide three very popular profiles A profile, R profile and M profile, A stands for application profile, R stands for real-time profile and M stands for micro-motor profile. So this Cortex M3 processor core is based on ARM version 7 micro-controller profile hardware architecture. So hardware architecture means code and data buses are separate. It also supports necessary vector interrupt controller, backup interrupt controller, memory protection unit, three AHB light buses, then instrumental and embedded trace microsels for trace, JTAG and serial wires for debugging. So this all resides near to this CPU. This micro-motor also operates at max 100 MHz and it communicates with the on-chip peripherals using two buses, advanced high-performance bus which is AHB bus and two advanced peripheral buses. So two buses for code and data and one buses for system. So these three are AHB light buses which core uses for communicating with multi-layer AHB matrix. So core communicates with these high-speed controllers, DMA controller, Ethernet controller, USB controller using this multi-layer AHB bus matrix. Also this core uses the same matrix for communicating with the flash and SRAM and ROM. For the remaining on-chip peripherals core communicates with AHB to APB bridge. So this also comes with clock generation logic. So this clock generation logic you can program this micro-motor to run at max 100 MHz. These are the on-chip peripherals. Some serial interfaces are available, external interrupts are prepared, RTC real-time clock is general purpose, IOS are available, timer counters and on-chip peripherals are available for the user to design any embedded system. So let us learn these features one by one. So this LPC1768 is a 30-bit micro-controller. So meaning is it is having 32-bit data path, 32-bit register bank, 32-bit memory addresses and 32-bit ALU unit. So let us calculate the maximum memory space this micro-controller can access using this 32-bit wide memory addresses. This micro-controller can access maximum 4GB memory space. So the formula is very, very common 2H to 32. 32 is the size of program counter or the memory address. So the on-chip peripherals available are 64KB static RAM for storing data, 512KB flash program memory for storing code, 8KB ROM for boot. So this controller is hardware-based architecture. Meaning is the separate instruction bus and data bus are available to access the same memory space which is unified memory system. So which allows instruction and data accesses to the memory at the same time. So this increases the efficiency without affecting the instruction pipeline. There are 17 general purpose input outputs, having configurable pull-up pull-down registers, open drain mode and repeater modes. All GPIOs are located on the AHB bus for the fast access. So if you go back to the architecture, you will see that all the GPIOs are directly connected to the AHB matrix. So which are very, very near to the core for the fast access. There is one 8-channel 12-bit successive approximation resistor analog to digital converter. So you can have maximum 12-bit output with a conversion rate of 200 kHz. There is one 10-bit DACs also available, digital to analog converter for generating analog signals for various applications. There are four general purpose, 32-bit timers, counters available. Having 8 capture inputs and 10 compare outputs. There is one more new feature, one motor control PWM with three channels. So you can design a three-phase motor control system with this special interface. So each contents separates timer counter, match capture limit and daytime resistor. There is one more standard PWM model available on this microcontroller, real-time clock RTC. So this is one of the on-chip peripheral. This RTC uses 1Hz clock output generated from 32-bit ultra-low power oscillator which is also on-chip. So this clock is used by this RTC to generate calendars, alarms like applications. So separate 20 bytes of battery power, backup resistors are available and this RTC can be powered by externally using three-fold lithium button cell. So even the power down mode or even if your controller is in off state, your RTC never loses its data and you can generate the applications like calendars, alarms. There is one more feature, system tick timer which generates fixed 10 millisecond interrupt. So this feature is used by real-time operating systems like RTOS, Fritos. There is a watchdog timer available to wake up your microcontroller from deadlocks. There is one more new peripheral available, quadrature encoder interface which converts angular displacement into two pulse signals and can be used to track positions, directions of rotations and velocity. There is a channel purpose DMI controller used for memory to peripheral to memory transactions. There are two PLLs, programmable phase lock loop, PLL 0 generates CPU clock, PLL 1 generates USB clock. There are four external interrupts, one wake up interrupt controller which detects an interrupt and wake up the processor from deep sleep powered on or deep powered on mode. There are two features ISP and IAP. So ISP allows microcontroller to be programmed while mounted in the end product but application needs to be stopped during the reprogramming process. IAP in application programming allows the microcontroller to be programmed under the firmware controller but application did not to be stopped. There is one Ethernet Mac having full feature 10 Mbps or 100 Mbps Ethernet Mac, USB controller, USB 2.0 full speed support, communication between host and up to 127 peripherals. There is one more USB OTG controller on the go which allows the microcontroller to be act as both master as well as slave rules. There is one more CAN control area network 2.0 B controller with two channels. So you can design automobile based applications using this on-chip peripheral. Four UARTs, UARTs 0, 1, 2 and 3. Having fractional board rate generation feature, it has its own separate internal transmit and receive fee pose, DMA and IRDA mode support. Out of these four UART 0, 2, 3 are identical and UART 1 has an extra feature of modem control and RH485 support. SPI full to flex serial interface, serial peripheral interface used to interface external memories like SD card. Then there are two SSP compatible with SPI, four wire SSI and microwave bus protocols. Three I2C bus controllers, bidirectional inter IC control using only two wires SCL and SDA supports master or slave mode. Then there is one more inter IC sound bus controller which allows the communication interface for diesel audio applications, support master and slave mode. So you can design audio applications also. These are the references, thank you.