 Welcome to the session on modulus counter. At the end of this session, students will be able to design a synchronous mod counter. Let us see what is mod counter. Modulus counter are defined based on the number of states that the counter will sequence through before returning back to its original value. For example, two-bit counter that counts from 0 0 to 1 1 in binary that is 0 to 3 in decimal has a modulus value of 4. Hence, here the states are 0 0 0 1 1 0 1 1 n written back to 0 0. Note that it has taken 4 clock pulses to get from 0 0 to 1 1. As in this simple example, there are only two bits that are the maximum number of possible output states for the counter is 2 to the power 2. Therefore, a mod n counter will require n number of flip-flops connected together to count single data bit while providing 2 to the power n different output states and n is always a whole integer value. Here, we can visually see the operation of these two-bit or synchronous counter using a truth table. We can see from the truth table of the counter of q 1 and q 2 when q 1 equals to 0 and q 2 equals to 0, the count is 0 0. After applying the clock pulse, the value becomes q 1 1 and q 2 is 0 giving the count value 0 1 and after the next clock pulse the value becomes 1 0 and finally, the value becomes q 1 q 2 equals to 1 1 giving a count of 1 1. The application of the next clock pulse causes the count to written back to 0 0. Therefore, it counts continuously up in a binary sequence of 0 0 0 1 1 0 1 1 and next 0 0. Here, if a single flip-flop on its own could be thought of as a mod 2 counter as it has single output resulting in a count of 2 either 0 or 1. But, if a single output flip-flop on its own produces a limited counting sequence, so by connecting together more flip-flops to form a chain and we can increase the counting capacity and construct a mod counter of any value. If a single flip-flop can be considered as a mod 2, then adding a second flip-flop would give us a mod 4 counter. Allowing it to count in 4 discrete steps, then we have seen that a mod 2 counter consists of single flip-flop and a mod 4 counter requires 2 flip-flop allowing it to count in 4 discrete steps. Here, the q 1 q 2 n clock in timing diagram are shown to be simultaneous even though it is connecting or the connection represents an asynchronous counter. The output q 1 is least significant flip-flop changes for every clock pulses and the output of q 2 makes transition whenever q 1 changes from 1 to 0. Here a question how many natural states will there be in a 4-bit ripple counter? Your options are 4, 8, 16, 32. Take a pause of this video and write your answer. Your answer is C. In an n-bit counter, the total number of states are 2 to the power n. Therefore, in a 4-bit counter the total number of states are 2 to the power 4 is nothing but 16 states. A synchronous mod 6 counter, suppose we want to design a mod 6 counter, how could we do that? First we know that m equals to 6 that is mod number equals to 6. So 2 to the power n must be greater than 6 as 2 to the power 1 equals to 2, 2 to the power equals to 2 equals to 4 and 2 to the power 3 equals to 8 and 8 is greater than our 6. Then we need a counter with 3 flip-flops giving us a natural count of 0, 0, 0 to 1, 1, 1 in a binary. Then we can use a combinational logic circuit around a basic counter either synchronous or asynchronous to produce any type of mod counter. We require as each of the counter unique output states can be coded to reset the counter at the desired count. The 2 table is as we are constructing a mod 6 counter, we want the counter to reset back to the 0 after a count of decimal number 5. However, we can see from the attached 2 table here that the count of 6 gives us the output condition q1 equals to 0, q2 equals to 1 and q3 equals to 1. Here in this diagram, here we use 2 input NAND gate to code the 110 state but the first time that q2 and q3 are both at logic 1 as when the count reaches 6. So 2 input NAND gate connected to q2 and q3 could be used and we can code these output states of 110 to give us a single signal to clear the counter back to 0 with the help of 2 input NAND gate. In binary code the output sequence count will look like 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1 but when it reaches the state of 110 the combinational logic circuit will detect this 110 state and produce an output at logic level 0 and we can then use the resulting low output from the NAND gate to reset the counter back to 0 after its output of 0 to 5 decimal count. And giving us the required mode 6 counter. When the output from the combinational circuit is low it has no effect on the counting sequence. Here the q1, q2, q3 and clock in timing diagram are shown. The output q1 is least significant flip lock changes for every clock pulses and the output of q2 makes transition whenever q1 changes from 1 to 0. Similarly, q3 makes transition whenever q2 changes from 1 to 0 and this can be achieved by connecting q to the clock input of the MSB bit. Here asynchronous mod 10 counter if we take the modulo 16 asynchronous counter and modified with the additional logic gates it can be made to give a decade counter. For use in standard decimal counting and arithmetic circuits such counters are generally referred to as decade counter. A decade counter requires resetting to 0 when the output count reaches to the decimal value of 10 that is 1010. The decade counter has 4 output producing a 4 bit binary number and by using external NAND gate we can detect the occurrences of the 9th counting state and after that it reset the counter back to 0. As with other mod counter it receives the input clock pulse 1 by 1 and it counts up from 0 to 9 repeatedly. Once it reaches the counter 9 the counter goes back to 000 instead of counting 1010. The basic socket of decade counter can be made from gk flip lock that switches state on the negative trailing edge of the clock signal. Here the output q1 is least significant flip lock changes for every clock pulses and the output q2 makes transition whenever q2 changes from 1 to 0. Similarly, q3 makes transition whenever q2 changes from 1 to 0 and q4 makes transition whenever q3 changes from 1 to 0 and this can be achieved by connecting q to the clock input of the MSB bit. So modulus counter are defined based on the number of states that the counter will sequence through before returning back to its original value. In general an n beta synchronous counter is called mod n counter where mod number equals to 23 power n. In this case of modulo m counter they do not count to all the possible states m is the number smaller than 2 to the power n. These are my references. Thank you.