 Welcome to class 26 on topics in power electronics and distributed generation. So, we have been looking at the currents in current components in a single phase inverter and especially the single phase inverter with a capacitor center tap configuration. And we looked at started off with a DC specification of the voltage which is linked to the AC terminal voltage specification with some additional inverter parameters. So, the other things that we need to consider is so the DC voltage rating was considered. So, we have to consider the effect of low frequency harmonics on the voltage rating. In the last class we looked at took a close look at the current rating and we saw that the current rating has thermal implications and it has implications on power loss and cooling and the temperature of the capacitor core which has a reliability implications. There are other factors such as hold up time of the capacitor which can be important in DG application. From the reliability perspective we looked at a simplified model of the component the capacitor component as a bathtub curve which is a commonly used model for reliability and we came up with a estimate for end of life. So, if you look at the model that we had for the capacitor. So, if you have the manufacturer specified L naught as the life at the at a test measurement point from the manufacturer T C naught. And if you have data at the actual core temperature of T C A then the life at the actual temperature is approximately given by L naught and we are considering a doubling of life for a 10 degree reduction in temperature of the core T C O minus T C actual by 10. You could also have a voltage multiplier effect. So, one factor is that effect on the of the temperature which is actually a very significant effect. So, you could also have a voltage multiplier effect. So, if you are operating in close to V norm is equal to V rated then this has a value of 1 and it is great greater than 1 for V norm nominal operation of the capacitor to be less than V rated and rapidly degrading the capacitor if the actual operation of the capacitor is above its rated voltage ok. So, many times you can have a 400 volt electrolytic capacitor for a short duration for a few seconds you might be able to take it up by a few tens of volts above 400 volt, but if you hold it at that level for a long time it will actually get damaged in a matter of seconds and, but for a short duration you can actually take it above the rated voltage it is not recommended for continuous operation or design. So, in the last class for our design of the capacitor one of the design points that we had chosen was we considered a capacitor C dc of 4 parallel 150 micro farad 450 volt capacitor to obtain a load life of about 4.6 years and power loss in the capacitor bank of 15 volts. So, essentially what we had done was we calculated the current components then we looked at what the thermal impedance from core to ambienters and we looked at the ESR the values of ESR at different frequencies and calculated the temperature. So, we got 4.6 years and the loss in the capacitor in the ESR because of these various current components totaled in both the top bank plus the bottom bank each bank consisting of 4 parallel capacitors to be 15 watts. And so, now we are left with to look at what is the final voltage ripple that happens on this capacitor banks because of the different frequencies. So, one frequency is a 50 hertz which goes through the center tap and the frequency is the 100 hertz which comes on the DC bus and then you have the switching frequency effects because you have the output low frequency which is getting chopped by the action of the inverter. So, you have the high frequency effects. So, to look at these individual components we have our CDC is 4 into micro farad is 600 micro farads. So, if you look at the 50 hertz voltage ripple your voltage ripple at 50. So, this is we had 4.3 amps flowing per capacitor bank at 50 hertz times root 2 for the peak and the impedance of the capacitor to be 2 pi 50 into 600 into 10 to the power of minus 6. So, this is about 33 volts. So, we also can observe that this 50 hertz applies plus say for example, if the current is positive it will charge up the bottom bank and discharge the top bank. So, you might have plus 33 volts may be at one instant, but the top bank will have minus 33. So, the total voltage across the entire bank would be not affected by this 50 hertz or in another instant bottom might be minus 33 and the top may be the other polarity, but their polarities cancel. But on a individual bank basis this is a important factor to consider however on a total bank basis it may not be observed it is not observed. So, it is not seen on V dc. If you look at the 100 hertz effect. So, this is we had 1.8 amps flowing through the capacitor times root 2 to get the peak. So, the impedance is 2 pi into 100 into 600 micro farads. So, it is 6.6 volts per capacitor bank. So, it is because this voltage is actually getting this current is flowing as a differential mode current through the bank. So, you have plus 6.6 on top plus 6.6 at the bottom. So, it adds up. So, seen as it is seen as a 13.2 volt ripple on V dc. If you look at the switching frequency effects and the switching frequency we have considered is 10 kilo hertz. We have 3.1 amp of ripple again we are approximating it to be a sinusoidal component at a single frequency. So, 3.1 into root 2 and if you look at the capacitive voltage drop this is 2 pi into 10 to the power of 4 into 600 micro farads. So, you have about 0.1 volts. So, hardly any ripple at the switching frequency. If you look at. So, this is because of the capacitive effect. If you look at the ripple because of the ESR in the capacitor with a similar switching frequency current flowing through. So, this is now the ESR of the capacitor was 0.41 ohms at the 10 kilo hertz. There are 4 capacitors in parallel. So, you have about 0.4 volt due to the ESR of the capacitor 0.1 volt because of the actual capacitance. So, at the switching frequency you could almost consider only the ESR effect the capacitive is a capacitor is behaving starting to behave more like a resistor rather than as a capacitor even at the switching frequency ok. So, if you so the ESR effect dominates. So, if you look at what is the maximum voltage the maximum voltage seen by the individual capacitors and just assuming a worst case scenario we would have 400 volts nominal for the individual capacitors DC value. You have 33 volts because of your 50 hertz effect you have about 6.6 volts because of your 100 hertz effect. So, you have about 440 volts on seen as the voltage on your individual capacitor bank. So, you have actually a very tight margin of just 10 volts. So, your control has to be very effective. So, that you do not have large overshoots etcetera when you are actually dynamically controlling the DC bus. Whereas, if you look at the overall total capacitor bank voltage. So, this is now twice your 400 volts which is 800 volts which was our DC value plus 13.3 which is twice 16.6. So, about 813 volts is your total voltage seen by the whole top and bottom capacitor bank. So, if you look at the ripple voltage above your nominal voltage. So, the ripple voltage is about 2 percent ripple overall which might seem reasonable it is a tight design, but it is actually doable. So, you might have to be cautious about your control design. So, that you do not have large overshoots on the DC bus capacitor. So, you have to precharge it slowly etcetera ok. So, if you look at then the overall design of the DC bus capacitor bank. We saw that the first thing that you decide is the type of capacitor you want to use. So, in a voltage DC bus of voltage source inverter electrolytic capacitor is common. In fact, people have started looking at very high reliability inverters where you might actually eliminate electrolytic capacitors in the DC bus. You might actually use poly properly in type of capacitors, but its value is quite small. And if you want a large value of capacitance to hold a DC bus constant you will need a large bank ok. So, the capacitor type is important. The voltage rating from both DC and ripple perspective is important. The current ripple has implications on life and efficiency. If we feel that you are tight on these two factors one might consider say considering more capacitors in parallel. However, you also have mechanical considerations which you need to consider from the cooling perspective also. If you put more capacitors in parallel you have more surface area for your capacitor bank. So, you effectively help reduce your thermal capacitance as long as you keep your packaging space between capacitors constant. But you also have mechanical constraint of volume and size etcetera which means that you cannot go on increasing the number of devices that you could add in parallel. You end up now taking a lot of space. So, from your packaging constraint you might have mechanical constraints you might have sizing requirements which might prevent you from adding more capacitors. You also have factors like if you add more and more capacitors in parallel in the system you are considering components that are increasing and we know from our reliability studies that if you put more and more components into a physical system the chances of failure especially at connections, terminations, breakage of some problems at the connections can increase. So, putting very large number of components in parallel is also not realistic solution from the perspective of component reliability ok. So, people have looked at what is a reasonable tradeoff in terms of the voltage ripple current ripple perspective, but at the same time not having too many components overly large number of components also from a cost perspective if you put too many in parallel your cost might actually go up quite sharply. So, now we will actually look at the one of the analysis that we did for evaluating the current in the capacitor and the life of the capacitor was actually the switching models what are the waveforms in the capacitor due to the operation of the single phase inverter. So, we will now take a closer look at the switching model of the power converter ok. So, if you look at the leg of the power converter we have we looked at it earlier the leg of the power converter is modeled as a single pole double throw switch and if you look at the overall inverter structure you have the duty cycle coming in into your PWM block where you are doing a comparison between your duty cycle and a triangular carrier. So, we were considering duty cycles in the range between 0 and 1 and the triangle carrier again being going as in a symmetric manner from 0 to 1 and back down to 0 and the output of the comparison is the command to the top switch of your inverter which is S plus. And we also know that this is a model where we are considering exchange of power between two sources essentially the exchange of power is between your AC and DC side and the variables that we consider as input to the input to the switching model is the are the two variables that are essentially varying slowly in such a model and the one variable which is varying slowly is the DC bus voltage it does not change rapidly because of the fact that we have a large capacitor typically connected to the DC bus. Another slowly varying quantity is your AC current again the reason why we consider the AC current to be slowly varying is because we have a output filter which is typically a inductive filter and the inductor prevents sudden changes in currents. So, we consider the AC quantity to be also slowly varying. So, the inputs to this particular inverter model is your DC bus voltage and your AC current or your V in and your I out I AC we have labeled in some of our diagrams I AC as I out. And the output of the switching model is actually the quantities that are varying quite rapidly which is your output AC voltage which is VON we have labeled it as VON in many of our diagrams this output voltage with respect to the neutral or it can be the output voltage with respect to the negative bus also something that can vary the output of the switching model is your DC bus currents which can be your positive bus current negative bus current etcetera ok. If you look at the switching model of such a power converter the question you could ask is when would such a model be required when would it be useful to us and definitely it is going to be useful to us if the item of interest is actually close to the switching frequency or it may be something even which is higher than the switching frequency because of the rapid transitions that can occur because of the switching action of the inverter ok. So, if you look at the items of interest. So, your input the variables are V DC and comma I AC which we consider to be smooth and continuous your outputs are V O which can be VON or IDC which can be on your positive or negative DC bus which are discontinuous. So, if you need the switching model if you are considering say for example, the switching action of the devices or the diode operation for example, if you have dv dt spikes di dt spikes you might have stress on the inverter stress on the components on the transistors etcetera you definitely need to look at the switching action. You may also be looking at the switching loss. So, if you consider it EON, E off etcetera these are a switching characteristics related. So, if you are looking at it on a detail waveform basis that definitely would need a switching model. You may also need to consider ripple effects for example, ripple in the filter for filter design. So, you might consider delta I in I AC. We consider I AC to be continuous, but it might have some underlying ripple because of the switching action of the inverter and you want to decide how big inductor you want to put in the circuit. We also saw that we could calculate ripple IRMS current in CDC. So, factors such as that such factors can be calculated from the switching model of the inverter. You might also be interested in say the PWM spectrum calculation. So, if you look at the exact expressions for the PWM spectrum of say sine triangle PWM you get Bessel functions etcetera you have components not just at the switching frequency, but also at the side bands. So, more sophisticated PWM modulation methods if you want to study it close closely you want to definitely look at the switching functions the switching model of the inverter ok. Another aspect which when you study closely it becomes an important aspect of all power converter design is how to handle electromagnetic interference. These interference effects are actually closely tied to the switching effects the D I D T D V D T in the power converter and also another part of the aspect of the inverter itself which is the parasitic components in the circuit ok. So, a parasitic component that we recently studied is the ESR of the capacitor what we wanted to purchase was just a capacitor, but we got a resistor along with the capacitor which is causing problems. Similarly, when you go to purchase a transistor you do not just get a switch you have lead inductances, you have capacitance not just from your collector to emitter of your transistor switch, but you can have capacitance between your your silicon chip to your heat sink and these capacitances can actually carry currents and those currents can actually lead to significant EMI concerns in your power converter. And these components preliminarily you might assume to be ideal in the sense that you would assume that those parasitics are not there, but in the actual realization of the power converter if these effects are ignored then EMI becomes a problem which addressing at a later stage becomes issue it is always good to look at what parasitic components are there in your circuits you have stray capacitance between your magnetic windings and your body frame of your inductors, transformers etc. So, these parasitic components if it can be included up front can actually be included with the switching model of the power converter to see what would be a DI DT now coming with a inductive parasitic what would be the induced voltage or a DV DT now with a parasitic capacitance what would be the surge spiky currents that go into such a capacitor. So, these these analysis this type of switching model analysis can give you a feel for what is the worst component in your layout which gives you the maximum headache from a EMI perspective ok. But there are actually drawbacks of the switching model too and one of the drawback of the switching model is related to the fact that the output of the model is discontinuous. So, whenever you have discontinuous functions you need more data points to actually describe it which and more data points means you have longer computation time you need more memory requirement. So, you would always like to actually see where you could get get away with something simpler and the something simpler is the average model ok. So, one can look at the average model and the the main benefits of the average model is when we are looking at longer timeframes and one important area where you would look at a longer time frame of the operation of a inverter is when you are actually looking at how to control the inverter. So, whenever you are looking at it from a control design perspective you might say I want to look at how do how does a MPPT act over minutes duration rather than over microseconds duration where the switching frequency effects occur. So, if you are now wanting to do long longer term simulations or multiple fundamental cycles maybe when you are looking at much longer duration like mission cyclic mission lifetimes days of simulation where you are looking at temperature effects which cabinet temperatures can actually take hours to settle. So, you might want to look at then a model which can be require lesser number of computations which can actually be solved in a shorter time frame and in a simplified manner, but can capture most of the effects of what the switching model can do. So, another aspect that can be covered by the the the average model is ability to understand underlying PWM amplifier. For example, you might have low frequency spectrum of your PWM amplifier in many advanced PWM modulation methods like space vector discontinuous modulation etcetera. One might consider adding a third harmonic. So, you want to look at the path for the third harmonics in the overall system through the filters etcetera you also have low frequency non-idealities like distortions, dead bands etcetera and you may want to look at the model of your inverter from a low frequency perspective to study these effects in a closer manner. If you look at the time steps that are used for computation of the inverter. So, if you consider say a switching frequency of 10 kilohertz you are considering a switching period of 100 microseconds. So, you are talking about your time step to be much lesser than your TSW your switching period. So, if you are talking about for 10 kilohertz FSW you are talking about time step TSW of 100 microsecond you might take a T step of maybe 1 microsecond if the you are looking at something on a fine grain basis you might even take it lower if you are looking at d i d t is d v d t is during switching action etcetera. But you can see that you have a constraint of your computation time to your switching frequency whereas, if you now look at on an average basis you might actually just do one computation per switching period. So, you are talking about benefits advantages of 100 to 1000 times increase speed in your computation. So, something which might take hours on a switching model can be done maybe in a few minutes or maybe just a minute in your average model. So, to look at the average model we will start off with again the switching model of the power converter and we are familiar with the switching model which is the single pole double throw switch. So, we consider a switch in parallel with the diode this is transistor Q p and Q n and the switching is S plus for say if you consider this as leg A and this is I A is a current flowing out p and n and our PWM action is generated by a sine triangle comparison. So, we have a triangle going between 0 and 1 and we can consider it with respect to a reference say some reference R. So, we have V AR if this is V A. So, in the top of the midpoint topology that we considered on a single phase basis we had considered the neutral to be the center point which was the reference. So, we have S plus for our switching function of leg A is 1 if D A is greater than your triangle of your PWM and 0 otherwise. We also know how to relate the duty cycle back is 1 by TSW integral 0 to TSW S plus A DT and the switching of the bottom switch is SA minus is 1 minus SA plus. So, we can actually write an expression for V AR the voltage at A with respect to R is S plus V of p with respect to R plus SA minus V N with respect to R and we can make use of SA minus is 1 minus SA plus. So, we get this is to be is equal to SA plus V P N or V P N is our V DC plus V NR. So, we have a simplified model for our DC output voltage. So, you have consider this as 1. So, this is the switching function description of our leg A and if we then average this particular expression over 1 switching period we will put a bar to indicate it is average V AR. So, if you now consider the average of SA plus V DC we will make an additional assumption that V DC does not change significantly over 1 switching period. So, you get the average of SA plus V DC and this is the V DC average plus V NR average and we know that the SA plus average is our DA and the V DC is not changing significantly. So, we have V AR is DA V DC plus V NR. So, this is the one is the switching function model and the two represents essentially the average model and you can actually drop these bars without large change any significant ambiguity in what type of model you are writing because you know that the switching function represents a discontinuous function whereas, DA represents something that is smooth smooth function which is continuous. So, similarly one can actually write the switching function relation between your DC bus positive current I DC P is SA plus times I A which is the switching model of the current and if you then take the average here taking the average of SA plus I A we are again going to make the assumption that I A does not change significantly over 1 switching period this might be a looser assumption compared to assuming that the DC bus voltage is staying constant it does have implications for example, this type of model you may not be able to average when your I A output frequency is getting very close to your switching frequency. But for sufficiently large difference between your fundamental frequency and switching frequency we could go ahead and take the average and we have I DC average is equal to DA times I A. Similarly, you could take the model for the negative DC bus current I DC for the negative bus is SA minus I A which is 1 minus SA plus. So, you will get 1 minus DA times I A to be your negative DC bus current. So, if you now draw the model of the average model you have essentially your positive bus negative bus your DC bus capacitor bank supporting your V DC you have DA I A coming in from your positive DC bus you have 1 minus DA I A respect to N P if you look at your output voltage you have DA times V DC generating your output voltage VA which is going out through your filter. So, it is your continuous current which is your I out or I AC if you look at the voltage DA it is actually with respect to N and here you what you end up with in this model is that this particular point is also linked to the same reference. So, the bottom part of this model you have a current source which is going into a short circuit. So, you find that this particular path is redundant you can actually simplify it and you can make the model to be something simpler you have essentially DA I A. So, this current is now automatically DA I A and because this current is I A this current that is going through the negative DC bus is actually 1 minus DA I A. So, it satisfies the same constraint as your as what is there shown over here and the inputs to this particular model are essentially your duty cycle your I A and your V DC and typically in control applications you will have measurement of your DC bus voltage you have your AC current measurements your controller is actually outputting your duty cycle and then you could actually incorporate a model such as this for the one leg of the power converter. So, instead of using the average value now the value of VA with respect to a reference is now continuous quantity rather than a discontinuous quantity and similarly the currents that are coming in are now continuous quantities rather than discontinuous quantities. Also the assumption that we have made in this model is that the duty cycle belongs to the range 0 comma 1. If you if your duty cycle goes out of the range you might find that your your energy conservation equations may not be satisfied your amplifier cannot generate more voltage than what is available. So, you need to ensure that you are respecting your duty cycle constraints you also have other non idealities that you have ignored in this model you have ignored non idealities such as dead time switch voltage drops etcetera which might effectively reduce the actual voltage that would be obtained at the output of this average model. So, you can ask a question now in this this average model can we can we take this particular inverter to be a amplifier gain. So, if you consider this particular amplifier as having a very stiff DC voltage you can see that the relationship between your duty cycle input and your output voltage V a is essentially just da V dc. So, if we consider V dc to be constant. So, essentially you have a gain times your input to be your output. So, many times we might further simplify from your output voltage perspective your inverter to be considered a ideal amplifier ok. So, you can but if you look at it from the reverse perspective where you are looking at the currents that are coming into your DC bus you have your duty cycle might be a sinusoidal quantity your input current would be a sinusoidal quantity. So, you might you may not be able to take a simple gain model as the relationship between your currents at the input and output one current may be 50 hertz and then your ripple now on your DC bus is now starting to occur at 100 hertz etcetera. However, between your duty cycle and your output voltage you have the same frequency effects. So, you could consider it to be just a linear amplifier with simplifying assumptions regarding the DC bus. Another factor to be considered when you are modeling a inverter especially considering the when you are looking at one leg is in this particular case if you had this is for one leg of the power converter if you have two legs you could consider two such models in parallel if you have polyphase you could consider multiple such legs in parallel. So, this particular average model can be generalized ok. So, another factor to consider when you when you are modeling the converter is the effect of PWM delay. So, this is especially important when you are considering the bandwidth of the converter to be close to the switching frequency in engineering often when we consider something to be close or far we consider numbers such as factor of 10. So, if your switching frequency is 10 kilohertz and if you are considering control bandwidths below 1 kilohertz then you might say you could maybe ignore the delay effects. But for designs where you want to actually consider switching frequencies which are much closer to your bandwidth. So, you may want to have a bandwidth close to 1 kilohertz, but your switching frequency may be just 2.5 kilohertz. And the reason why you do not want to take your switching frequency high is you know that your switching losses would go up with frequency. So, you do not want to take it to be much higher than what is really just required ok. Then you will have to maybe now look at what are the delay effects that are there because of the PWM. Also many times in modern power converters the PWM delay gets added on to the computational delay in your digital controller and so, the overall delay becomes important factor ok. So, if you consider the PWM operation the duty cycle coming down. So, if in a digital controller your actual point at which you are updating your duty cycle may be at some regularly sample points. If you are having a analog type of implementation you might be able to have the exact intersection of your sine wave and your duty cycle wave and your triangle. People have looked at the difference between regularly sampled and naturally sampled PWM and the performance is actually quite similar ok. There are some pulse position changes because of the sampling, but people have found that you get similar performance in the two methods ok. But you can see that in case when your duty cycle is close to 1 update over here will give you a fast response for the operation your output voltage goes up to a high value very close to when your actual computation is updated. Whereas say if you look at the point 3 you are updating over here and now you have a delay between when your actual switching action is taking place and when the computation is being provided from your controller. And this depends on what is the value of the pulse that you are trying to get etcetera and it is a varying effect, but it is modeled as a equivalent delay model of TSW by 2 ok. So, another way of looking at whether one can justify such a model for the delay one can look at the expression for the average output voltage and the volt second match at the output of the inverter ok. So, if you look at the average output voltage say V a with respect to say the neutral in our inverter model is V dc into d minus half. So, this was the average model over TSW. So, if you look at the volt second on a a to n basis you can describe it as integral with respect to time time t s plus V dc by 2 minus 1 minus s plus V dc by 2 d tau where tau is the time with respect to which you are doing your volt second integration ok. So, at t is equal to TSW we have volt second a n divided by TSW by definition this is what your averages V a n average ok. So, if you look at what this means if you look at your PWM switching cycle you might have the output of the inverter going between 0 plus V dc and minus V dc by 2 and you might have an average value and by definition the average cancels out the positive and negative volt second error. And if you look at then the volt second error that you are building up again assuming that your error is 0 to start with. So, volt second error you are starting off with 0 you are having some negative volt second error then your volt second error is going to the other side and coming back. So, if this was instant one at which you are updating your PWM operation the point at which your error comes back to 0 is at TSW by 2 and at TSW and subsequent points. So, if you look at a control action the time to take for the error to go back to 0 is TSW by 2 and many times the delay between when you give a command and the output to go back to 0 and all the subsequent ripple would be such that the positive and the negative volt seconds balance out. So, one could model the delay effect of the PWM leg to be TSW by 2 from also from a volt second perspective volt second error perspective. So, this often in a power converter is used along with the model of your output filter people when they model the inverter for digital control might model the inverter as a zero order hold. So, if you look at the phase delay of a zero order hold where the zero order hold is being updated at a rate of TSW is actually the delay is TSW by 2. So, many times people use a zero order hold model for the inverter with the subsequent analog filter etcetera. In case there is sufficient separation between your switching frequency and your control frequency then it people might be even justified in ignoring such delay effects. Thank you.