 Hello and welcome to this presentation of the STM32MP1 series system configuration controller. The STM32MP1 microprocessors feature a set of configuration registers. The system configuration controller gives access to the following features. Selection of the data path for AXI Masters to the DDR controller. Selection of the Ethernet-PHY interface. Management of the I-O compensation. Configuration of the 20 mA high drive I-Os used for I2C fast mode plus. And configuration of the high speed 1.8 volt I-Os used for SPI, SDMMC, Ethernet, QWAD SPI, and trace. The system configuration controller enables the control of the balance of the bandwidth between masters. Examples are low latency masters or processor versus high bandwidth masters. For example, graphic processor or USB host to get the best usage of the DDR memory bandwidth. Both DDR ports are using the same physical mapping address, so there is no need to update the software and any change can be done during execution to dynamically adapt to different use cases. The system configuration controller allows static configuration of the external Ethernet physical interface used. Supported gigabit physical interfaces are GMII or RGMII with or without 125 MHz from external physical interface. 10 or 100 Mbps MII and RMII physical interfaces are also supported. ETHCLK from RCC could be used to feed the external physical interface reference clock, usually 25 MHz, thus saving a crystal. The values on the boot pins are latched during the boot phase. It is up to the user to set the boot pins to select the required boot mode before reset. The boot pins are also resampled when the device exits standby mode. Consequently, they must be kept in the required boot mode configuration when the device is in standby mode. During stop or run mode, the embedded pull-down on boot pins can be disabled to save power. The pull-downs are automatically disabled during standby mode and enabled again on standby mode exit. Refer to the application note AN5031 getting started with STM32 MP1 series hardware development and the reference manual for details on the boot pins. In order to have the best electrical characteristics, whatever the conditions, the IO compensation automatically tunes the characteristics of the IOs when the voltage or temperature changes. Required only for VDDIO frequencies above 50 MHz. The control timer break register contains the control bits related to safety and robustness. Two control bits steer certain error detection events to the timer's break inputs. This allows timer outputs to be placed in a known state during an application crash. Once programmed, the connection is locked until the next system reset. These internal events are the power voltage detector event and the Cortex-M4 lockup state. The system configuration controller manages the I2C IOs fast mode plus 20 mA drive-enable control bits. This mode is only enabled on pads selected for I2C and AF MUX. There are also controls to improve ADC performance when analog supply is below 2.7 volts. The system configuration controller also manages specific high-speed IOs control when the voltage is below 2.5 volts. This control is available for SPI, SDMMC, ETH, QUAD SPI interfaces and for trace pins. The mode is only effective on pads selected in AF MUX. Warning! Using this feature when the voltage is above 2.7 volts could damage the chip. To avoid unwanted programming, a global enable fuse is provided as OTP and must be set only for a platform expected to use an IO voltage below 2.5 volts. The on-chip bootloader allows the user to program the flash memory or set OTP fuses through a serial communication peripheral. The supported protocols are USART and USB. USB is recommended for a large amount of external memory. Note, the USB boot works with specific values of the external quartz oscillator on HSE with 24 MHz as default. 25 and 26 MHz are also possible with dedicated OTP fuse settings. The OTP setting for HSE auto-detection allows 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40 and 48 MHz for USB boot. The USART UART uses the internal HSI oscillator with automatic baud rate detection. There's no restriction on the HSE frequency between 8 and 48 MHz if the USB port is not used during the boot phase. It could be used by an application with any HSE frequency. In addition to this training, you can refer to the reset and clock control, power controller, timers, Ethernet and I2C trainings.