 Hello and welcome to this presentation of the STM32U5 Analog-to-Digital Converters or ADCs and Digital-to-Analog Converter or DAC. It will cover the main features of ADC-1,2 and ADC-4, which are used to convert analog voltages such as sensor outputs to digital values for further processing in the digital domain. The DAC is used to convert digital signals to analog voltages which can interface with the external world and also with on-chip peripherals such as comparators and operational amplifiers. First, let's describe the feature of the ADC. STM32U5 products integrate three ADCs, the 14-bit ADC-1, ADC-2 and the 12-bit ADC-4. ADC-1 and ADC-2 are high-performance converters belonging to the CPU domain while ADC-4 is a low-power converter belonging to the smart-run domain. The table in this slide highlights the differences between these two ADCs. First, the resolution of ADC-1 and ADC-2 is 14-bits and the converted data are stored into 32-bit registers while the resolution of ADC-4 is 12-bits and the converted data are stored into 16-bit registers. The maximum sampling rate is the same for both ADCs, 2.5 mega-sample per second. The ADC-1 and ADC-2 support a hardware linearity calibration, which is required for a 14-bit resolution. The ADC-4 only converts analog voltage provided by single-ended inputs while the ADC-1 and ADC-2 also supports differential analog inputs. For ADC-1 and ADC-2 conversions are organized in two groups, the regular group and the injected group. The injected group can preempt the execution of the regular group sampling sequence. The ADC-4 only supports the regular group. The ADC-4 supports a low-power background autonomous mode, LP-BAM, that allows it to be functional and autonomous in stop-0, stop-1 and stop-2 modes without any software running. When ADC-4 is used simultaneously with ADC-1 or ADC-2, ADC-1, ADC-2 operation might generate noise on Vref plus voltage. Since Vref plus is also the ADC-4 reference voltage, this might cause conversion errors. To prevent this issue from happening, the ADC-4 implements a control bit that activates the concurrent mode protection. Each channel of ADC-4 can choose one out of two sampling times, while each channel of ADC-1, ADC-2 can be sampled with a different sampling time. Raw samples acquired by ADC-1, ADC-2 may be processed by the oversampler, gain and offset compensation units before being provided to the software. Maximum oversampling ratio is 1024. Raw samples acquired by ADC-4 may be processed by the oversampler before being provided to the software. Maximum oversampling ratio is 256. Both ADCs feature a dual clock domain architecture, which means that the ADC kernel clock is independent from the AHB bus clock that is used to access ADC registers. ADC-1, ADC-2 and ADC-4 use the same kernel clock source from RCC. This synchronizes the ADC-1, ADC-2 and ADC-4 activity and helps to manage the interference with each other. Compared to previous generation, there is no option to select the AHB clock, HCLK, as the sampling and conversion clock source. However, it is still possible to choose the kernel clock from CIS-CLK or HCLK in the RCC. The ADC-1, ADC-2 has the following analog input channels, 17 external channels and 3 internal dedicated channels, 1 channel for the internal reference voltage, VREF-INT, 1 channel for the internal temperature sensor, Vsense and 1 channel for VBAT monitoring, VBAT-4. The ADC-4 has the following analog input channels, 19 external channels and 4 internal dedicated channels, 1 channel for the internal reference voltage, VREF-INT, 1 channel for the internal temperature sensor, Vsense, 1 channel for VBAT monitoring, VBAT-4, and 1 channel for the internal digital core voltage, V-Core. ADC-4 also has an internal connection to DAC output channels. The resistance of the analog switch inside the input output increases when the analog switch supply decreases. So for cases where VDDA and VDD are low, a voltage booster may be enabled to supply the analog switch and guarantee low resistance. VDDA is the supply recommended for the analog switch. But when VDDA is below 2.4 volts and VDD is above 2.4 volts, the power supply can be switched to VDD. If both VDDA and VDD are below 2.4 volts, the voltage booster should be enabled. This slide describes sampling time control applicable to ADC-1, ADC-2. The first step of a conversion consists in loading the sample and hold capacitor with the voltage to be measured. Longer sampling times ensure that signals with a higher impedance are correctly converted. The sampling times available listed in this slide in ADC clock cycles range from 5 to 814 cycles. The sampling time can be programmed individually for each input channel of the ADC-1, ADC-2. The ADC-1, ADC-2 implements two mechanisms that were introduced from STM32G4 series. The first one is Bob mode, which only works in discontinuous mode. In Bob mode, sampling starts immediately after the last conversion without going into idle state. This will provide less latency from the trigger signal to the start of conversion. The very first ADC conversion after the ADC is enabled is performed with the sampling time programmed in SMP bits. Bob mode is effective as from the second conversion. The second mechanism is the sampling mode based on trigger signal. Rising edge starts sampling, falling edge stops sampling and conversion begins. Both ADCs provide an automatic calibration procedure which controls the entire calibration sequence, including ADC power on and off. The ADC-1, ADC-2 integrates a hardware linear calibration mechanism. More than 14-bit ADCs generally require calibration to compensate capacitor array mismatch. So as with the SMT32H7 series, linear calibration is introduced in the STM32U5. Since calibration takes 25,502 clock cycles to be completed, it may be useful to store the calibration value to flash memory to accelerate ADC boot time. Linear calibration does not have voltage or temperature dependency, so it can be run once during the final production test. ADC-1, ADC-2 and ADC-4 all support a hardware offset calibration mechanism. Since offset can be dependent on voltage or temperature, it may be necessary to recalibrate in case of significant voltage or temperature change. These figures indicate the ADC-1, ADC-2's linear calibration effect. ADC-1 is converting a 100 Hz sinusoidal wave signal. Without calibration, THD indicates minus 71 dBFS, with calibration, THD is improved to minus 78 dBFS. This slide describes the ADC-1, ADC-2 gain compensation feature. A gain factor can be applied to the raw samples to improve the dynamic range. The gain factor is applied after oversampling. It is programmable in the range of 0 to almost 4 and can be adjusted by 0.025% steps. Each ADC has three integrated analog watchdogs with high and low threshold settings. The ADC conversion value is compared to this window threshold. If the result exceeds the threshold, an interrupt or timer trigger signal can be asserted without CPU intervention. Regarding ADC-1, ADC-2, the analog watchdog 1 also has filtering capability. If data is out of range for more than the number of times specified in AWD-FILT in the ADC-XHTR-1 register, the AWD-X flag is set and the corresponding interrupt is issued. This figure details the various stages of the ADC-1, ADC-2 data path from raw sample to data register update. Raw data is first passed to the oversampling block and the resulting value can be left or right shifted in the OVSS stage. The oversampling unit pre-processes the data to offload the main processor. It can handle multiple conversions and average them into a single data item with an increased data width up to 24 bits. The data then enters the gain stage followed by the offset stage. The internal multiplier width is 32 bits and the input data width for gain compensation must be less than 18 bits since 18 plus 14 equals 32 bits. Note that the output of the offset stage is assigned 25 bit value. Before this data is passed along to the analog watchdogs, saturation control is performed. The offset correction may result in the data width being wider than the original data. To limit the original width, data saturation can be enabled. Then finally, the data is passed to the left shift logic block and stored in the data register. The OVSS and L-shift bit fields in the ADC-CFGR2 register select the alignment of the data stored after conversion. By default, data are right aligned. The ADC-4 implements a mechanism to support concurrent operation mode. When ADC-1, ADC-2 starts sampling, it creates noise on the Vref plus reference voltage. If ADC-4 is running at that time, the ADC-4 conversion result is disturbed. To avoid such noise, ADC-1, ADC-2 uses an internal signal to notify ADC-4 that sampling is in progress, so that ADC-4 will suspend its operation for one clock cycle. As soon as the ADC-1, ADC-2 sampling phase begins, ADC-4 is put on hold for one ADC-4 clock cycle, extending ADC-4 conversion time by one clock cycle. In addition, ADC-1, ADC-2 may have two sampling phases during ADC-4 conversion. This is due to the injected conversion function of ADC-1, ADC-2. By setting Vref SEC SMP to 1 in the ADC-PWR register, ADC-4 operation can be put on hold twice during the conversion phase. When the Vref SEC SMP bit is set, ADC-4 conversion time is two clock cycles longer. This timing diagram clarifies the Vref protection mechanism effective when ADC-1, ADC-2 and ADC-4 are used concurrently. First, ADC-4 samples an analog channel. This generates noise on Vref Plus, then ADC-1, ADC-2 also starts a sampling. Since Vref protection is enabled, this stalls ADC-4 for one clock cycle thanks to the clock mask internal signal. During this clock cycle, ADC-1, ADC-2 generates noise on Vref Plus. When clock cycle later, conversion resumes in ADC-4. By this means, noise generated by ADC-1, ADC-2 will not affect ADC-4 conversion. As explained in the previous slide, concurrent sampling on ADC-1, ADC-2 and ADC-4 can cause errors. However, enabling the Vref protection function is not sufficient. As second condition is required, both ADCs need to use the same clock, same frequency and same phase. The pre-scaler used to generate the sampling and conversion clock must be initialized with value 1. ADC-4 supports the autonomous mode to further reduce system power consumption. In this mode, the ADC defaults to power off state. When a hardware trigger is detected, the ADC powers up and then issues a clock request. The ADC-4 start sequence is managed by a state machine. Once the sequence is completed, the ADC conversion is performed. ADC result data can be used by analog watchdog or transferred to memory by the LPDMA. Once all planned conversions are finished, the clock is stopped and ADC returns to power off state. During this sequence, the Cortex-M33 is not involved. This table compares the characteristics of the STM32U5, ADC-1, ADC-2 and ADC-4. VDDA voltage range is the same. ADC-4 supports a Vref plus range from 1V to VDDA. The effective number of bits, ENOB, is a measure of the dynamic range of the ADC. In differential mode, the ENOB of STM32U5, ADC-1, ADC-2 reaches 12.8 bits. The ADC-4 of STM32U5 does not support differential inputs. Note that the minimum sampling time for STM32U5's ADC-4 is only 1.5 clock cycle. The higher the resolution, the longer the conversion time. The 14-bit ADC-4 also consumes more than 12-bit ADC's due. For low acquisition frequency, the ADC-4 of the STM32U5 consumes less than due ADC's of STM32U5, which is convenient when periodic voltage monitoring is performed in LP-BAM. Let's now describe the features of the DAC. The STM32U5 series integrates one DAC module with two analog outputs. The basic functionality is very similar to that of the STM32L5 DAC. The DAC output can be routed to internal resources without using the GPIO. The DAC OutX can use an internal pin connection to on-chip peripherals such as comparators and operational amplifiers. The STM32U5 DAC supports the low-power background autonomous mode, LP-BAM, in stop-0, stop-1, and stop-2 modes. By using the LP-DMA and a hardware trigger, the DAC output can be updated even when the system clock is stopped. In this mode, the DAC only supports sample and hold mode using the LSI-LSC clock source for static conversion. Unlike the STM32L5, the DAC is connected to the AHB bus, which offers a larger bandwidth than the APB does. To minimize disturbances on VRF+, the kernel clock is the same on ADC1 and ADC4. This table shows the characteristics of the STM32U5 DAC. The STM32U5 DAC can operate between 1.6 and 3.6 volts, whatever the buffer state, on or off. 12-bit monotonicity is guaranteed. By using sample and hold mode, the current consumption can be drastically reduced. The STM32U5 DAC, buffered output, has a settling time of 2.5 microsec, whatever the capacitive load, up to 50 picofarad. The DAC can handle a sampling rate of 1 mega-sample per second. Several application notes dedicated to analog-to-digital converters are available. To learn more about ADCs, you can visit a wide range of webpages discussing successive approximation analog-to-digital converters. In addition to this presentation, you can refer to the following presentations. Reset and clock control and power management.