 So, welcome to this lecture on Programmable Logic Devices in the course digital system design with PLDs and FPGAs. We have completed our advanced digital design part, I have covered almost everything, DERAWAT design, controller design, issues in the controller design then some essential topics on synchronization, top down design everything is completed, VHDL we have as far as synthesis is concerned, we have completed everything pretty much. What is remaining is maybe the test pen just we have to cover to write the test pen for simulation, we will do that and two topics are left. One is Programmable Logic Devices and Field Programmable Gate Arrays and we will next few lectures we will complete try to complete the Programmable Logic Devices or PLDs and I must tell you that there are two types of devices in this PLDs, one is SPLDs and CPLDs, one is Simple Programmable Logic Devices and the second one is Complex Programmable Logic Devices, SPLDs are very rarely used but it is better for an academic interest to go through that part so that when it comes to the CPLD it is very easy to understand and also maybe that gives you a little bit of how these devices are evolved, maybe it is useful I mean I am not very sure about it but CPLDs have some use at least, it is not as useful as FPGAs because nowadays the designs are very complex and people try to build lot of things into a single chip to that extent CPLDs are not much used but they have do have a place in the case of low and medium complexity design and they have some advantages, some disadvantages which we will see. So let us start with the Programmable Logic Devices, so let us look at the slides. So we are going to hold together the Programmable Logic Devices which are called PLDs and as I said there are two part, one is SPLD and CPLD, basic idea is now when you look at the evolution this is started this idea of the Programmable Logic Devices has started quite sometime back maybe 25 to 30 years back and there were I mean the VLSI circuit density was not much. People needed some kind of Programmable Logic and earlier designers used to work with discrete gates and discrete functions like multiplexers, demultiplexers, encoder, decoder. So when you had normally a logic design it was a printer circuit board full of small integrated circuits okay which was not very complex you know you will have some gates you will have some multiplexers, encoders, decoders as we have the design was pretty much same what we have seen but it was implemented not in a single chip plenty of chips it was huge number of chips okay. So you should when we talk about the evolution you should think of that scenario not today's scenario. So there was some need of Programmable Logic the first thing comes to mind is the chip select decoding in a microprocessor based design that means in a microprocessor you have lot of memory and peripherals. Again those days it was not a single chip there will be multiple memory chips to cover the memory space multiple peripherals all these need some kind of you know the memory map you know everything is mapped to the memory map of the processor. And that is done by the chip select decoding by the higher address bits and that some kind of flexibility was required in kind of mapping these devices into appropriate places depending on the need okay. So there was at least for a chip select decoding there was some kind of programmability was required. So I think that was the kind of starting point of this Programmable Logic. So the only Programmable element then available was memories okay what is called Programmable read only memories. So that is a context so basically the idea coming back to the slide the idea is how to use memory as some programmable logic you know like you have standard memory how to use it as a programmable logic that was a basic idea. So let us clear that part so that you are kind of not lost in all the old technology because if I show a picture of one of the prom a kind of architecture then you will be wondering what is going on. So let us treat this idea suppose we take a two you know variables x and y and you want to implement this Boolean function of x and y which is nothing but x, x or y okay. So do not confuse with this these two x's this is the variable this is the function and this is y okay. Now idea is how to use a memory to implement this x, x or y that is a basic idea and we take a two line two address line memory that means four locations it has and that means we take a four into one memory and you know that there are four locations and when address line is 0, 0 the 0th location is selected address line is 0, 1 first, 1, 0, 2nd and 1, 1, 3rd location okay. So internally there is an address decoder depending on the value you put here appropriate location is selected okay for writing or reading now assume the truth table of x, x or y is programmed in this four locations okay. So basically x, x or y is the function is either of the input is 1 then the output is 1. So if both inputs are 0 that value is 0, 0, 1 that means this is x bar y is 1, x, y bar is 1, x, y is 0 okay. So what we are doing is that we are programming that the truth table into these four locations because these are two address lines are connected to these variables okay and this is some more program okay we just write that truth table into these locations. Now you check what happens suppose we give 0, 0 as the input value now that writing is kind of part of the programming this memory with the truth table and when you want to kind of use it as a logic what you do is that you put this memory in the read mode. So I am not showing that I have assumed that it is written and this is already in the read mode okay. So the logic box when the memory is in the read mode, when the memory is in the write mode we write the truth table okay and I am not showing the writing part which is understood. So if you give 0, 0 to x and y then this 0th location, 0, 0 location is accessed and you get a 0 here and if it is 0, 1 it access this location and then 1 comes on the data line. So the data line is the output, address line is the input and again you give 1, 0 the 1 comes here, 1, 1, 0 comes here. So basically you take a memory of the required capacity that means suppose you want to implement a 5 variable function then you take a memory with 5 address line or 32 locations into 1 bit 1 data line we require. Connect all the variables to the address line, 5 variables to 5 address line in whichever order it does not matter but then you have to appropriately program the truth table okay. So you program the truth table then use the data line as the Boolean function, the output of that logic you know that is what is required. So that is how we use the memory as a kind of programmable logic, address lines are the inputs, data line as the output this is while working as logic, truth table is the content of course when you write the truth table into this memory then this data line is definitely the input okay is not the output okay. But in operation when the logic is in operation address line is the input, data line is the output. Now if you use a kind of static RAM which is kind of volatile each time you power up the locations are not defined okay, we do not know what is the content of the location it could be 0 or 1 because these are kind of you know the latches inside SRAM cells are nothing but kind of cross couple latches which will come up with some random values. So you have to write, so you cannot use SRAM as a programmable logic you can use but you have to write it each time but so if you again once again go back to the old scenario that was not kind of possible and so some kind of non-volatileity was required that means you program it once for all maybe but then it should retain this truth table inside okay. So such a device was available then that is called programmable read only memories or called prom okay. So the architecture of the prom was like this and we are showing now exactly similar one that means four locations to address line instead of one data bit I am showing two data bits that is the only difference. So this was the architecture of the prom or programmable read only memory okay, so that is called programmable read only memory that means you can once you program it you can only read it you cannot write it. So you can say it is a write once and read many time memory or something like that. So you have here a four location memory with two bits output and if you see there are two address line a1 and a0, a1 and this is a compliment of that a0 compliment of that and this part is the address decoder. So this line when both are 00 a1 bar a0 bar this AND gate is 1, this is a1 bar and a0 this is 1. So it chooses these are the min terms and a1 sorry a1 a0 bar a1 a0. So these four AND gates are the four locations okay. Now take one data line and there are connections okay like there is a diode and a fuse and this is a normal fuse which can be blown by passing a larger current okay. So there are four connections through diode and we will see why the diode is required. I mean this is we are discussing the old architecture and this data line is pulled down to the ground with through a resistance and this is the output okay if you need a buffer you can imagine a buffer here and similarly any number of output can be there which allows you to implement multiple outputs okay. Now assume you want to program your XOR function that means 0, 1, 1, 0 okay. Now what you do is that you blow the fuse we will see how to blow the fuse you just blow this fuse retain this connection retain this connection and blow the fuse okay. So it is equal unto programming 0, 1, 1, 0 exactly like here 0, 1, 1, 0 because we are trying to implement the XOR of the input okay. So here we have two inputs you can assume it is X and Y. Now like if you program 0, 1, 1, 0 you see what happens you give 0, 0 here then this AND gate is 1 and rest all is 0 okay. So the moment it is 0 these diodes won't contact okay and this is 1 but you see that this fuse is blown okay. So this there is no conduction here and it is pulled down you get a 0. So but if it is kind of 0, 1 then this AND gate output is 1 rest are 0. So since this is 1 and this is pulled low this diode will conduct the fuse is retained so you get a 1. Similarly when you have 1, 0 this diode will conduct the fuse is intact and you get a 1 and when it is 1, 1 this is active rest all are 0 but this fuse is blown. So it won't conduct it is pulled low and then you get this okay. So you can say that this is acting like a programmable OR okay. So we are programming the OR function you can imagine this as an AND and an OR okay. So this is a fixed AND you have 2 inputs so you have 2 raised to 2 min terms a1 bar a0 bar a1 bar a0 a1 a0 bar and a1 a0 all the min terms are there. So suppose you have n inputs then you can imagine there will be 2n vertical lines n inputs and there are complements and there will be 2 raised to n AND gates here each AND gate will have n inputs okay because you need to choose an input or its complement. So for an n input case there will be 2n vertical lines representing n inputs and its complement and there will be 2 raised to n AND gates representing all the min terms and there are each AND gate there will be n inputs selecting the appropriate min term okay. Now you program the truth table by blowing the fuse okay. Now the next before we see how to blow the fuse what is the purpose of this diode okay you might be wondering why a diode is required because it is definitely not to do anything do the 0 because when you want to program a 0 you blow the fuse there is no connection at all. So it is something to do with the connections you are retaining. So in the case of XOR gate we have program 0, 1, 1 and 0 that means these 2 fuses are blown they are not there these 2 are retained okay. Assume the input is 1, 0 okay when the input is 1, 0 the AND gate this AND gate is high 1 and this AND gate is low 0. Suppose there is no diode there is a direct connection then you can imagine that what happens then there is a direct connection through the fuse one output is 1 other output is 0. So there will be a short circuit directly from the VCC to ground the VCC of this through the PMOS or then maybe earlier it was kind of BJTs used but it does not matter but then there will be a from the VCC it is coming through that and it goes to the ground through the transistor pulling loads there is a short circuit. So this diode you know kind of block that 0s so that there is no direct connection between the VCC and the ground. So if this is kind of 1, 0 then this is 1 and this since it is pulled over this diode will conduct the 1 reaches here but since this is a reverse bias you know this diode is 1 is here and the 1 is here it is reverse bias you need to have at least 0.7 volt difference being identical gates that cannot happen and so this will not conduct this will not create short circuit that is the idea of the diode. So as I said the programmable read only memory is a kind of fixed and a programmable or okay. Now how to blow the fuse it is enough if you know like if the current rating is say 20 mA you draw larger current maybe the 30 mA or 40 mA then this fuse is blown it is a one time business what is done is that at this point okay. Suppose you want to blow this fuse and naturally this has to source that current there will be some mechanism to source a larger current wherever you are connecting that output is there there will be large current sourcing. So say you want to blow the fuse what is done is that you give 00 here now what you do is that take this point and apply a negative voltage maybe say this is grounded so you give kind of minus 5 volt and the supply is 5 volt earlier the potential difference was you know somewhere around 5 volt little less than 5 volt. Now it will be near around 9 volt because it is a double with some drops you know removed or near to the 10 volt. So the current you know flowing through the fuse is double that of the normal current and it blows the fuse and it just for a short duration a negative pulse is applied. And if you care to see the old time devices there is a pin called VPP that is called the programming voltage V is the voltage P is the programming so there you apply a negative voltage and then you can appropriately choosing the minterm you can blow the fuse rust will be retained. But as I said it is a kind of non-volatile once you program you cannot reprogram it then you get it ok. So that was the basic idea of the programmable read only memory you can implement a combinational circuit essentially you program the truth table and we have seen that it is a fixed band and it is programmable over ok. The AND is fixed by this 2 raise to an AND gates in the case of N inputs by blowing or retaining the fuses we are programming 0 or 1. So you are able to program the truth table and also like when in the case of multiple outputs multiple like in this case 2 output a same minterm can be chosen ok. You can share a minterm between 2 outputs and it is possible that the first output may not use that minterm the second output may use or both may use but in any case it is possible that a single minterm can be shared between 2 outputs that is possible ok. So that is the idea but basically there is a problem as you go increase the number of inputs say assume that in a chip select decoding maybe you have to kind of use say decode 10 address line ok. Suppose there was a 16 bit microprocessor then only say a 15 to a 9 need to be or a 6 need to be decoded that means 10 address line need to be decoded then you will have 10 address line and 2 raise to 10 1024 locations I mean 1024 AND gates ok. Now it is really funny if you look at the particular application of chip select decoding you are mapping the device to a particular location and many a times it requires only 1 AND gate ok like say all the higher address bits are 1 1 or some pattern ok. Many a times you require only 1 AND gate but you have 1024 AND gates. So these AND gates for many like you know that even if in a 5 variable normal Boolean function you are not going to use 2 raise to 5 minterms ok. If you use all the minterms then the output is 1 always so this is an overkill this number of AND gates are overkill. So the question we are asking is that can we reduce the number of AND gates ok. So that was a natural question people ask. So it all started with designers using the PROM as a programmable logic which was not kind of intended function of the PROM though it is obvious for us. Now that time it was a kind of invention or a creative use of the PROM. So people felt that actually there is lot of wastage of the AND gate in this kind of architecture. So why not why do not we use less number of AND gates. The moment you use less number of AND gates then you should realize that those AND gates we cannot fix the minterms ok. Suppose we say that let us remove these 2 AND gates. Then what happens is that you have only minterms a1 bar a0 bar and a1 bar a0 is available. Then we would not be able to program the XOR function ok. So the moment you try to reduce the number of AND gates then you should make sure that these AND gates are programmable. That means these minterms should be programmable. That means you should be instead of 2 fixed connection with an AND gate with 2 input you should have an AND gate with 4 input and with maybe fuses connected at the input some kind of programmable mechanism. We will see what is that mechanism, how it is really implemented. This is just a kind of logic schematic not the actual implementation and we will see how this is implemented using transistors. We will see that but essentially it require AND gates with 4 inputs 4 programmable inputs. Then we can reduce we can have only using some statistics ok. Like you study the Boolean function of different variables, 5 variables, 6 variables from practical cases and say in 90% of 80% of the time for a 5 input scenario you do not require more than say 14 minterms or something like that. Then you can usually 14 AND gates ok. Now the moment you introduce the programmability in the AND gate it is even possible there is another advantage that you do not need to kind of stick on with the minterms now you can stick on with the product terms. So, earlier suppose we had used a1 bar a0 bar and a1 bar a0 ok. So, both minterms were there but we know that a1 bar a0 over a1 bar sorry a1 bar a0 bar over a1 bar a0 is nothing but a1 bar only. So, it is possible that in such a scenario you can minimize your Boolean equation ok. And the product term now if you have 2 minterms in the output then what you do is that you only implement a1 bar here that means you there are 4 connections you retain the a1 bar connection and blow all the other connections ok. So, the moment you have less a memory we decide we can use lesser number of AND gates we would definitely make these AND gates programmable and at that point we do not need anymore we are not working with the minterms we will work with the product terms which will even reduce the requirement of number of AND gates ok. So, that was the next step ok people started building these devices ok from idea taken from this prom that this is too much of an overkill for most application does not require these number of AND gates for chip select decoding is very few 1 AND gate or 2 AND gates and even in normal Boolean function the number of AND gates required are less. So, people reduce the number of AND gates but made AND gates programmable and the moment it is programmable the requirement of minterms has vanished and we have come to the product term. So, essentially you kind of minimize your equation and start implementing it is that. So, that is what we said we can reduce the AND gate but the AND gates be programmable the minterms become the product terms and such a device was called PLA ok the programmable logic array it was called it is called programmable logic array ok I am sorry that I have not written that in the previous slide. So, the programmable logic array now somewhere in the lecture I have told do not worry too much about these terminologies again do not ask me why it is called programmable logic array I mean just the name it may have some kind of you know justification by the those who invented it. But we need not worry you know too much about these terminologies because all the more we go to the next step it will be kind of confusing. So, this was the architecture of programmable logic array again we are taking the case of 2 input case where there are 2 inputs and it is complement now instead of 2 raised to AND gates we have only 2 AND gates. And each AND gate has you know the 4 inputs to connect to the 2 inputs and it is complement with a programmability with a fuse you know with some kind of programmability like you know the simplest case you can imagine a fuse and you want to program say a1 bar then you retain this fuse blow all other fuse or you want a1 bar a0 then you retain these 2 fuse and remove this fuse. And naturally you can do the programmable over ok now this become pretty much complicated because if you have multiple outputs what to program how to program this how to program this because now when you have multiple output it is possible that a single product term can be shared between the output. Now we have talked a little bit about the multi output minimization when we have done an overview of at the beginning of the course. And when you have a multi output minimization you have to find basically the common sub-expression in the equation and try to implement that ok that is what need to be done here. What is common the largest common sub-expression should be implemented and that can be shared between these 2. But you see that this is a little bit of an overkill because there is lot of programmability now ok. Now like you have like you have programmable and and programmable over ok. So summarizing you have a the PLA was a programmable and and a programmable over. The prom was fixed and because all the min terms were there and the programmable over when it comes to programmable logic array you have the programmable and and programmable over. We have less than 2 raise to n product terms and you can share the product terms by output and there is tremendous programming overhead because you have to kind of you know program these fuses at the input of the AND gate and the output of the AND gate and so on. Lot of programming overhead was there but much more than that much more than that suppose you assume a single output do not worry about multiple output scenario you take just take a single output you are able to program whatever the product term you require. The moment you do that there is a less requirement less need for a programmable R or a kind of thing ok. Because suppose you are trying to program you know x x or y ok or a x or b like a is connected here b is connected here then we will program a bar b here a b bar here there is no need to kind of program this ok. So assume there are 4 AND gates ok and if somehow you can disable these 2 AND gates then there is no need to kind of you know somehow you make the output of the AND gate 0. Then there is no need for this programmable OR section we can fix you know make the connection fix and that will make all the programming overhead reduce. So that is the that was the next evolution for a single output you do not need a programmable OR because if you have multiple AND gates suppose in this case we are put 3 AND gates and you need only 2 product terms somehow make the AND gate output 0 we will see that how to do that. Then there is no need to have a programmable OR section at the output that was a basic idea and such a device is called programmable array logic ok. Now this was programmable logic array and this was programmable array logic and there is as I said do not worry too much about the name ok one is called PLA and another is called PAL I know it is it is kind of programmable logic but since earlier was one was called PLA this was called PAL. And now I will kind of use a shorthand for representing the AND gate so let us come to PLA now onwards it is very difficult like when we are going to see some practical devices which has lot of inputs. Now in a picture if there are say 10 inputs then we will have 20 vertical lines and it is very difficult to show AND gate with all the 20 connections. So now what we are going to the next slide onwards when we have a 4 input AND gate will only show a single line going like that assume that there is programmability at the cross point ok. So we are going to show so like this you have an AND gate a single line assume that there is programmability I mean assume that this is a 4 input AND gate ok that is the best way to do that we will see how it is implemented as I said. So we have a shorthand representation of a 4 input AND gate with programmability at all these inputs ok. So this is the kind of architecture of programmable aerologic where in you have some fixed number of programmable AND gates in this case there are 3 AND gates which is permanently connected to an OR gate ok. So when you take this output you can program you can implement a Boolean function of 2 variables up to 3 product terms ok up to like you have only one product term that will be programmed in the first AND gate and somehow you make sure that this AND gates and this AND gates are disabled ok. We will see that how to do that very simple and elegant way. So this is the architecture of programmable aerologic where in the AND gates are programmable but the number of AND gates are fixed. The OR gate is fixed that means if we have 3 AND gates which is connected to an OR gate permanently and you get an output and maybe like in a real device there could be variation like it is not that all the outputs are kind of consist of 3 product terms maybe there are some output which consist of only 2 product terms and things like that ok. So that is how and this is the basic architecture of a PLD or programmable logic devices ok. The PAL is the real architecture of a programmable logic devices and we were talking about the evolution and the real kind of logical reasoning behind how this has evolved ok. So though we are not using any of those very much definitely we are not using the prom and the PLAs and PALs are used but then it is a worthwhile academic exercise how this has evolved and why such an evolution happened ok to understand that will help in some other logic design I hope. So the PAL is programmable AND and fixed OR. So we started with a programmable fixed AND and a programmable OR we have come to both programmable then we have kind of inverted it was from a fixed AND programmable OR we have ended up with a programmable AND fixed OR for all the reason we have stated. So here you have for an N input you have 2 raise to less than 2 raise to N product terms each AND gate of the product term as 2 N inputs to be able to program any minterm or a product term you have dedicated product term for output and for a particular output the product terms of fixed ok that is architecture of the PAL. So this is the evolution we have started with the prom which is programmable read only memory which had basically a real memory where the address decoder acts as a minterms of the Boolean function fixed AND. So N input you have 2 raise to N AND gates each AND gate has fixed connection to the N lines. Then a programmable OR basically it works as programming the location with truth table and in a prom that is implemented that programmability is implemented through the fuses which we blow by blowing you know flowing a large current and diodes are kind of in series not kind of a cross drive from the VCC to the ground. The next one was that this AND was an overkill because in a chip select decoding very few AND gates are used only one AND gate is used even in real Boolean function the number of the product term minterms are less. So we reduce the number of AND gates but then it necessitated to make it programmable that means increasing the number of inputs to 2N and which is programmable and that enable not only the minterms the product terms which was much more kind of use it allowed to reduce the number of the AND gates. So the moment you talk about the product term you are talking about minimized implementation the Boolean equation is minimized to get the product term that is implemented and the programmable OR a lot of overhead because of programmable OR. Again for a single output we said that this programmable OR does not make sense because we program whatever the product terms we require and disable AND gates that automatically implement the programmable OR. So it was possible to kind of fixed OR and by playing with the AND gate disabling the AND gate we could get that programmability in the kind of in the present day language we can say we can get a virtual programmable OR or something like that. So at that prompted this particular architecture the PAL which has a programmable AND section and a fixed OR section okay. Now so that is what we have is about the idea of this PAL has come from using memory as a programmable logic because of non-volatility the PROM was used and which was a fixed AND programmable OR number of AND gates used were less. So we may reduce the number of AND gates making it programmable which enable to program the product terms and that was called PLA and for a single output again the moment the AND gates were programmable OR was not very much necessary. So that was prompted the architecture of the PAL which is nothing but programmable AND and fixed OR. So let us turn now to some real devices the first device okay again the bit of a history because nobody use nobody makes this PAL 16L8 anymore but if I remember if I can recollect this was one of the devices which came into the existence or people designed 16L8 and then the AMD used to make this particular device Texas instrument this particular architect diagram is from the Texas instruments old data sheet okay. So that shows the internal of the device I mean do not be kind of alarm by the number of lines it is very simple. So I hope you can kind of it is visible. So take this input you know this was a 20 pin dual inline package, dip package which in today's standard was very huge but early implemented very low density logic function okay. So take this input this was an input you see this is this one is coming is going through directly through a buffer and through an inverter that shows a buffer and inverter together and two lines. So instead of showing it here to save space it is shown on the side. So this line number 3 like 2 and 3 are the complement and the particular line of 1, 1 and 1 bar is these two. So you have another input 2 so this that line 2 and the input is here. So these lines are nothing but the inputs are its complement and so you have a dedicated input 1, 2, 3, 4, 5, 6, 7, 8, 9 and this particular one. So there are 10 dedicated inputs so you can up to 20 say 0 to 19 up to here is 10 inputs and its complement okay. Maybe that some connection maybe kind of the you can see these two connections are here but I am just telling the number of lines 20 lines are for 10 dedicated inputs and its complement and these AND gates now you take one of the AND gate here this has connection to all the inputs which is programmable with some kind of programmability at this junction okay. So now if you see there are 0 to 31 so there are 32 vertical lines that kind of tells us that there are 16 inputs and its complement okay. Now we have located the 10 inputs so where does that additional 6 input come. So look at this maybe look at this structure we will come to 6 additional input. So here you see there are 1, 2, 3, 4, 5, 6, 7 AND gates permanently connected to an OR gate which is going through a tri-state inverter and it is available as an output okay and the tri-state inverters enabled is controlled by another AND gate. We can call it say control AND gate okay that means if this AND gate output is high this output is available if it is low it is tri-state okay. But so this is a dedicated output which can be enabled or cut off similarly come that is pin 19 and pin 12 is also a dedicated output. So there are if you see 1, 2, 3, 4, 5, 6, 7, 8 outputs so that is what is shown here 8 output. But and the top 1 and the bottom 1 are kind of dedicated outputs and look at this section 1, 2, 3, 4, 5, 6 you see that it is when you enable this tri-state gate it act as an output but if you cut it off then this act as an input okay. So along with 10 dedicated inputs we have 6 IOs okay which can be used as output or input. So this now allows this IO pin to be used as input also okay. So in addition to 10 dedicated inputs you have 6 IOs which can be used as input. So there are maximum possible number of input is 10 plus 6. So you have 16 inputs and it is complement so there are 32 vertical lines that is how the 32 lines come. So now you imagine this each AND gate as 32 inputs with programmability. So you can choose any of the 16 inputs or it is complement to form a product term or a min-term or whatever you call okay. So AND in one section you can have up to 7 product terms okay up to 7 suppose you can use 3 of them or you can leave the 4 unused okay. We will quickly see how it is kind of to be able I mean how can you disable AND gates okay. We will see that we will in a moment I will tell you. So now you look at this output kind of this dedicated output there is hardly any reason for a tri-state gate. So most of the time this need to be permanently enabled unless you connect to some kind of a data bus where it is tri-stated or you know shared bus or something like that. Now how to permanently enable it so the idea is that basically this is you cannot like you have studied the gate and it is bit ridiculous to think of a kind of 16 input 32 input AND gates okay. So definitely this is a wired AND gate okay it is a single line and I hope you have studied wired AND or wired NOR we will see that you know we will I will show you how it is really implemented but do not worry this is not like a conventional kind of TTL circuit with 32 input or not even a conventional CMOS AND gate with 32 input it is a wired AND or wired OR we will see that okay. So now assume that this is a wired gate with a single line with a resistance pulled up to the VDD or VCC okay. Now what you do is that to permanently make the output of the AND gate 1 you blow all the connections you do not you know remove all the connections then this input is pulled up and since the input all the inputs are 1 the output will be 1 it is permanently enabled okay. So that is how the AND gate is permanently enabled okay. But there is a need suppose we have 7 product terms here in a particular for a particular Boolean function we need only kind of 6 product terms and we need to kind of disable this AND gate okay. Now how to do that is very simple okay you know that A and A bar is 0 the same principle is applied here what you do is that do not do any programming on this input retain all the connections okay all 32 connections are retained. Now assume there has to be for some function at least one input has to be there. So even if there is one input say A is connected here, B is connected here. So for a particular this AND gate A and A bar is connected to an input so irrespective of the input is 0 or 1 this AND gate output will be 0 always and that is disabled okay. So you want usually 3 AND gates no problem rest of the 4 AND gates you retain all the connections do not do any programming. Then those output are disabled automatically we are doing the programming of the OR okay. By programming the AND gate 0 output 0 we are implementing the programmable OR functionality. So that is a basic idea of how to manage if the number of product terms are less okay that is how it is managed. So now what we do is that to understand it a little more better okay. So essentially it was you know it was a kind of general purpose programmable device where you connect various input it really does not matter where you connect and that was the first time you know something of this was happening like you could connect the input lines anywhere. So depending on your PCB design you could say it was not convenient to bring A here maybe it was convenient to bring A here it does not matter you connected there because you could program it appropriately. So you could connect the various inputs here various output and depending on your need you program the number of AND gates and the product terms okay that was what the basic idea it works as a combinational circuit and we will see how this is used as a the devices which was meant for sequential circuit data path. And though we cannot kind of seriously use these kind of simple PLDs for great you know the data path and things like that that was not possible but still you know compared to earlier at that time the discrete gates this was a major leap major programmability to that extent the studying this is a very good idea. So now let us come back to the slide let us take this kind of say a part of it maybe we will take this first three section little bit magnified to understand it better okay. So that is what is shown the inputs like 1, 2, 3, 4 inputs okay and three output section okay and now this is a dedicated output okay and which we can use it was only as an output definitely this can be kind of cut off if it was a connected to a shared bus it was possible to cut off by this control AND gate that can you can permanently cut it off or you can a product term can control it okay. So that was a possibility here but take this section which is much more interesting as I said say this is an output and mind you there is a this is a tri-state inverter okay and this was an active low kind of circuit and that is how this L comes in the picture say PAL16L8 okay you might wonder suppose you have a Boolean function y is you know some of some product term then you implement if you directly implement that product term here then what happens is that you will get the y bar instead of y okay that was an issue but it is very easy suppose you have y to be implemented then you apply demorgan theorem you say y bar then you apply the demorgan theorem convert that into to equivalent y bar product terms and you implement it then you will you are implementing y bar at this AND or gate. So which is inverted by this inverter then you get the y you know that is how this was used okay. So this inverter itself is not a problem because the complement of that was taken and was implemented by the tools and maybe we are this structure though it is like this kind of output combined with the input though it is a very you know it is a very kind of very simple looking structure but it has many use you know it is really really kind of very elegant design though it looks very simple it has lot of advantages this particular connection this one connection we will soon see maybe we are coming to the end of this lecture. So I will kind of wind up here because we do not have time to kind of go through that. So in the next lecture we will go through it but what we have seen is a kind of commercial device then used now it is not available which is called PAL16L8 with 16 kind of 10 dedicated input 6 Ios. So the maximum number of inputs was 16 so there are 32 lines vertical lines or 32 input 16 inputs and it is complement and there are 2 dedicated outputs each OR gate has 7 programmable AND gates each AND gate has you know 32 inputs which is which can be connected to 16 inputs or it is complement then there is a tri-state gate at the output of the OR gate tri-state inverter the enable is controlled by another gate and we also have seen how to permanently enable that and there was 7 product terms going to an AND gate and we have seen suppose you need only 3 AND gates 3 product terms out to disable for product terms by retaining all the connections which bring in the programmable OR facility in the other programmable AND itself. And we will see little more in detail that Ios section of the 16L8 which is very elegant and then we will move on to some kind of devices with flip flop which allows you to implement data path and sequential circuit then pretty much we can move to the at least one device which is probably available even now which can be used in simple PLDs then we will move on to the complex PLD. So as I said though it is not useful directly this will enable us to understand the CPLDs which have some use today we will be able to understand the architecture of it very nicely if you understand this. So, please revise what we have done today and I wish you all the best.