 Hello friends, welcome you to all to the sessions 15 of home based development . So, in this class we will be covering basically ABARs and two special instructions SWI that is software interrupt and undefined instruction that is the instruction which is not understandable by the processor. So, what is the reaction to that by the processor? So, basically these are all part of the exception cases. So, this is little involved I want you guys to pay you know closer attention to what I am saying today. So, we will touch upon ABARs in general what what we mean by ABARs ok and then P fetch apart ABARs and data ABARs . So, by now you should know what these two ABARs correspond to when they are generated but still you know in this class we will cover the background of this and then these things happen and in response to these ABARs what what does the processor do. Then we will talk about the special instruction called SWI which you might have seen in the simulator code where you might be using one of few of them. There are whole lot oflegger functions provided with the simulator using this instruction with a specific parameter. So, once you understand how to use it may be you can try out all the library functions that are provided with the simulator, but this class is not about how to use them it is only about understanding what is a software interrupt ok and then when does the undefined instruction exception happen in a processor ok. So, this is going to be our focus for today ok let us see what is what do we mean by ABAR and ABAR indicates that the current memory access either code or data cannot be completed. So, let me give you the background what we mean by a memory access that cannot be completed. So, this is the processor ok. So, it is connected to the memory. Now, you know that processor reads both code and data from the memory. Now, what are the possible reasons why any of these access say the code access or a data access cannot be completed ok. So, first of all let us understand when does the code access happen code access happens during the prefetch stage. You know that in a pipeline already the instructions are prefetched right two instruction down the line. So, if there are some instruction ok 1 2 3 a different instructions will be in a different stages of the pipeline. So, once this goes up then this moves in this moves in and then the next instruction for this prefetched here right. So, code get access only during the prefetch we understand that during the prefetch only code gets accessed. That means, all the code is getting fetched aside of their execution ok. So, at least two cycles you know before it gets executed the code is fetched. Now, I will give you an example where a prefetcher what could happen ok. For this I need to just give you some you know physical memory virtual memory, but just understand that these things will be covered later, but only for you to understand the cons you know background on how these supports could happen and giving you this. So, basically you might have heard about virtual address and physical address ok. So, what I mean by physical address and physical address virtual address is something which the programmer thinks or the program thinks that it has got access to a whole lot of big memory ok. Let us assume a typical ARM processor can you know 32 bit wide. So, you can have larger memory assume physically there is a limitation on how much memory you can have it in your system ok. This is a processor and memory this is your embedded system ok. Assume that you have kept a RAM ok you have put a RAM of maybe say you know 256 can be ok this just an example you have you only have a 256 megabytes of a RAM ok. That means, this this is a typical example where you know you have RAM memory and then maybe a flash ok where your code is kept ok. So, any code the or the data that needs to be accessed by a program has to be in the RAM ok RAM. So, maybe this whole memory area is divided into some you know spaces and code data stack everything is there in this RAM. Now, whatever is required the code ok is not the whole code is brought from flash or a hard disk it could be a hard disk also in a typical this system with huge memory, but let us for a embedded system perspective let us assume that there is a flash and we cannot run the code from flash for some reason because the access time of flash is slower. So, always code is also brought into RAM and then executed. So, we are talking about that scenario where we have limited RAM memory and then assume that this is enough for this processor it may not be on it could be anything ok, but what happens is there will be an MMU also could be there you know it is a memory management unit. So, when you write a program you may assume that I have a whole lot of maybe you know 100 MB of memory is there ok. You declare that kind of a huge array of data ok or you have a big code which needs to be executed and they are placed in 100 MB space. So, this is what the program thinks that it has got a space of 100 MB, but physically there is only I am sorry maybe I mixed up the numbers here let me reduce this to 64 MB to convince you know that this memory is lower than this. So, 100 MB of a code and data is there and then you have only 64 MB of actual physical memory. So, this what the programmer thinks as a virtual memory is 100 ok and what physically is there is 64 ok at least a balance of this memory is not available. So, the whole code and data cannot be brought into the physical memory because of this limitation ok. So, but you may wonder how can I run a program which is needs 100 MB, but with the limited memory space it is possible because when you are running a code or when you are accessing a data you are not going to be accessing the whole thing in this same time right. When a particular piece of code is run it may access a particular part of the library and then when it goes to some other part of the code maybe it may access some other part of the data. So, basically what happens is the MMU the memory management unit and then virtual management system may brings in the memory which is needed for the execution to happen both in terms of data and code ok both in terms of the code and data it brings what is required and then it executes them and then you suppose that code goes to some other part of the space code space then that code part of the code which is there in the flash is brought in and this is not written back because code anyway you are not going to be modifying it, but if suppose the data is there it will be written back the old modified data new data will be brought in. So, what I am trying to say is doing using the virtual memory management ok and using a separate hardware across some processor and memory the typical 100 MB space is mapped to 64 physical memory a different point in time ok. So, some part of the memory is brought back and then you execute it and then take it back. So, you might have heard about pages or segment ok. So, assume that you have a page ok this page is currently there page 1 and you are accessing the code that program is accessing the code from here and when this page when the code goes out of this page region what happens is a code fetch prefetch abort generated the MMU memory manager memory controller gives the processor saying that this particular memory what you are looking for is not currently with me in the physical memory. So, what happens then the OS if you know is running then it comes into play play and then that particular page which is there in the or disk or a flash is brought back into the memory and then the control is given back to the processor to execute the same instruction again. So, basically what happens is the physical memory limited physical memory helps you in a bigger memory it will give a feeling that the processor know all the program thinks that this whole memory is available to you, but because it is needed because of the quality of reference it is needed only you know only during the time of execution the relevant pages of that is brought back it could be a page could be a code or a data and then it is quoted from the memory. So, this is the RAM ok this could be some other secondary memory it could be disk or some flash which is slower memory and this is a faster memory ok. So, this is called you know virtual memory and this is called you know which is done by MMU ok. We will be programming MMU how to convert this virtual addresses that you know program gives into a physical address which is in the memory. Now, why I am explaining this we will be explaining this later on also, but what I am saying is when a particular piece of code is not available in the memory or the data ok is not available in the memory that actually goes back the controller memory controller goes back and brings that new page and by replacing this old page into the memory back into secondary memory and then the execution starts. So, when this kind of thing happened the memory management unit of memory controller which knows both of them working together will know that there is a problem in the accessing of memory. So, it gives an abort signal to the part of the and in turn the processor executes a data abort or a free fetch abort and the abort handler ok the abort handler takes care of this swap in the memory and bringing back the new memory ok this handler could be a part of OIS code ok. So, this is what happens during a typical abort situation ok. So, the memory access is not possible to be completed. So, what happens is that particular problem is fixed and then the same instruction is executed again ok whichever cause the memory abort the data abort that instruction is again executed by fixing the problem that means, what the page is brought into the memory and then they will execute it again. Hope this is clear to you ok. So, abort is signaled through the external abort through the input ok by the memory controller ok and then ARM processor checks for the abort exception. So, how so, a processor is executing the instruction in the sequence. So, it has to look for whether abort is there or not there should be no sampled at particular time. So, that is happening when you know the M clock is there at the end of every execution ok every memory cycle not even execution of instruction even every memory cycle because why I am saying it is it is different from the execution cycle because suppose if you have a LDM or a STM that means, multiple data is accessed ok there will be multiple memory cycles ok. So, suppose 16 words have to be accessed ok assume 16 words are to be accessed from memory and then loaded into a register ok using LDM instruction LDM if D or IA whatever. Now assume that this is the cutoff where this much memory this much data is available in the RAM ok assume there is a page page is ending here one page is ending here page boundary and new page is starting here that is possible ok. This part of the memory which is is needed later on in this after this cycle is part of the another page whereas, this particular part of it is another page. Now what happens then register 1 0 suppose you are loading now 1 2 3 4 5 5 registers you are copy you know values you are copying from memory into a register. So, first two registers are copied from the memory whereas, the remaining things to be copied from memory which is not available in the RAM. So, it has to be page fault happened and then it has to be fixed. So, even during a part of the execution the fault can happen the abort can happen during the middle of a instruction execution. So, that is why I am saying that on every cycle every memory cycle this may be a non sequential access and rest of it will be a sequential access, but after this sequential access there will be a memory fault and then another non sequential access happens and continues. So, the processor can be interrupted during every you know it could happen on you know any cycle any part of the memory cycle. So, that is why the processor checks for abort on every memory access cycle. So, abort mechanism allows the implementation of a demand page between memory what I mean the demand page when a particular page is required that page is brought from secondary memory to a RAM ok that is what is called demand on demand you get the page that is called demand paging which is a part of OIS concept which you might have studied in your previous courses. So, I am just giving you a background on when an abort could happen ok. Now, let us concentrate on prefetch abort. So, a prefetch abort is something to do with a code. So, when a prefetch abort occurs 4 marks the prefetched instruction is invalid. Now, I need to give you a another example ok. This is prefetch is happening here ok prefetch and then decode happens and execution happens. So, assume that these are all the stop instructions and your this instruction is being executed this is in decode stage and this is in fetch stage. So, this particular code is on a page boundary this could happen right or ok this is one reason where you you are not able to get the instruction because let us assume that it is on the page bound ok. So, what happens is this memory is not in the RAM this code this code is from this hardware the code is going to different page and which is not available in the RAM that is one possibility ok. Another one is suppose the CPU is here and the memory is there ok assume that you know if there is no memory management unit or anything this is the starting at a 0 and this is a some addressup to may be 7 f f the code code is there ok ROM is there code ROM. So, you know very well that beyond the 7 f f there is no memory at all in the system ok. It is there is a directly mapped memory there is no memory management unit or something ok CPU is accessing the memory and there is a physical limit of 7 f f is the maximum value. Now, you as a programmer you might know that there is a limit in the memory and you you would have written a code such a way that this beyond this the execution do not go. So, suppose let me give you an example where you have written a code add you know there is some assembler something has been written and then you have put a branch to something address and then the code the code is ending here it is not going to go further down ok there is a branch to something above the code could be placed inside the memory itself. So, when this execution is executed instruction is executed it will it is anyway going to jump to a some other address ok it will be higher address here I am saying that it is higher address. So, suppose if there is a branch which points to a lower address ok let us avoid this. So, so there is the code is memory is increasing like this and there is a branch and then the code comes back control codes that. So, there is no code beyond this address at all ok, but prefetch could when this is before being DC executed it is going to access this try to access this part of the memory which is not there physically. So, memory controller may given abort, but it may not be a valid abort. So, that is why when it is accessing a code because it is going ahead and accessing the instructions ahead of actual execution the processor just notes notes it make a note of that that there is a there was a problem when I try to access this instruction ok and that information is passed between two stages ok through a pipeline registers you might have you might remember the pipeline registers that are there to pass on information from one stage to other. So, if this instruction which cost the prefetch abort comes to the execute stage then only it indicates that it is a valid instruction which was to be executed, but it is not available in the memory then it needs the support of OS to handle that abort. So, it is not necessary to create an abort on prefetch itself because there is a possibility that the previous instruction branches and then it never these two instructions are never executed at all. So, to cater for that kind of a condition it is not executed the prefetch abort is not executed until it comes to a execute stage. So, but it does not take the exception until the instruction reaches the execute stage please understand this is the reason why an instruction abort happens during a prefetch, but it gets served during the execute ok it is it will be noted and then if it reaches the execute stage then it abort will be as soon as it enters there is nothing to execute. So, it will go to the abort signal prefetch abort happens. So, this is the sequence ok it is noticed noticed here no action taken in the code stage when it reaches the execute stage action is taken. So, what action to bring the page back into the memory or something so that this same instruction can be fetched again with the or the correction is done. So, now the instruction is available in the RAM. So, it can be executed. So, this is what happens during the abort ok. Hope you understand this if the instruction is not executed because the branch occurs while it is in the pipeline the abort does not take place. Suppose if there is no need for executing that instruction there is no need to it is a abort. So, after dealing with the reason for the abort the handle executes the following ok. Now assume that suppose you know branch is not happened and that instruction has reached the execute stage then the abort handler will be called you know that you know there is a fixed location in the vector table for a instruction prefetch abort. So, that vector table it goes then PC will be now it will give a branch to the handler handler takes care of doing some correction on the why which cost the page fault or the particular cost of the error and then the control is coming back to the same instruction. Please remember prefetch happened when two instruction above was being executed and it suppose this is the address 104 during this time you encountered the process you encountered a prefetch abort and then it when it enters the execute stage the it goes to the control goes to the vector table and then the you know handler is called and then suppose some correction is happened. Now again the PC has to be loaded with the same value 104 ok which originally cost the abort. So, that the same instruction can be now fetched from the memory and executed ok that is the reason why it is coming back to the same instruction. Now I am saying that this is what is done ok let us understand this instruction first. What I mean by that is in the handler after fixing the problem of the prefetch abort the last instruction that is executed in the handler is this ok. If you recall I have explained in the previous section ok when the abort happens what all is done let us go back and recap all those things so that you understand this instruction pretty well. So, prefetch happened ok at 104 ok and it entered the execute stage now it shows that it is has to be executed that is the particular prefetch abort has to be executed. So, processor what does it do? It has to go to the abort mode ok it has to change the abort mode you go to the abort mode suppose you assume that it is the user mode. So, user mode has its own registers and abort mode has got its own register abort ok. So, abort mode has what are the registers R 13 ok and R 14 ok and then S saved program status register ok. I am just recapping on what I you know providing a recap on what I was explaining last class. So, abort happensit goes to vector table ok go and then just address to the abort handler. So, abort is executed now prior to that what needs to be done the instruction which cost has to be actually saved ok, but what is saved is because I told you that prefetch is not handled immediately it goes to you know when it comes to execute stage only it is handled. So, that time what happens is the instruction when it enters the prefetch abort execute stage the PC will be pointing at this is the instruction 104 ok, it will be pointing at 108 actually ok. It is accessing the trying to access the next instruction PC would have been incremented ok plus plus 4. So, it will be accessing 108. Now that time what happens the abort is handled. So, the PC whatever the PC value is stored into the link register of abort mode PC is stored here that is 108 is stored here ok. And then SPSR is loaded with the the user mode register is there right user mode register these are user mode registers it has got a CPSR right. So, CPSR holds the status of the processor including the user mode. So, that this CPSR gets saved here ok in the SPSR of the abort mode and then CPSR is modified the mode bit is changed to abort mode ok, abort it is mode bits are changed the LSB 5 bits are changed and then it executes the handle here ok. Now, the execution has come to the end of the handler. Now, the control has to come back to the instruction which cost the abort that is 104. What is stored is in the abort mode register R 14 what is stored is 108. So, this instruction. So, I have shown it as abort here, but actually when you write a code you will not be mentioning underscore ABT you will be executing R 14. So, what does it mean R 14 means it is in the abort mode. So, R 14 of abort mode register bank register is used. So, it is actually storing the the CPU has already put the PC value which is next to the instruction which cost the abort into the R 14 register ok. So, that value has to be taken and subtracted by 4 why do you have to subtract it by 4 because you are interested in coming back the CPU is you know processor has to execute the 104 actually not 108 because then it will skip this instruction because while accessing this instruction only it was in abort. So, now this you know the abort handler has fixed the problem. So, that instruction is in the memory. So, it has to execute that instruction before going to the next instruction right. So, how will it execute only when you give the control back to the same instruction. So, PC has to be loaded with the 1 4 values 4 by minus 4 has to be loaded. So, that PC comes back to the same instruction and executes it. So, that can be done only when the R 14 is taken from the abort mode because the processor has already saved that return value and it is subtracted by 4 and then loaded into PC. Now, when you have yes this I also have explained earlier when you are doing a PC as a destination register and when S bit is set ok this is a very special case when PC is a destination register and S it does not matter whether sub is done or add is done or move is done does not matter ok. You based on the need you may do anything but only thing is when S bit is set in the instruction ok format when S is mentioned you know S bit in the instruction will be set ok. And then when R D is given as PC CPU automatically copies not only the PC value ok let me ok there is too many things are there. So, in the abort mode you have two things to be copied ok R pertain you forget it that may not not not now it needed now R 14 which is a link register which is holding the return value of ok. And then SPSR which is having the original value of the CPSR where the when the abort happened this is the user mode registers and SPSR is here ok and assume that from R 0 to R 15 ok PC. Now these two have to be loaded with a new value SPSR should come here and R 14 after subtracting minus 4 ok should come here plus these nodes these two should happen together these two should happen together why? Assume that it is not happening together suppose this happens first what will happen? Originally it was having the CPSR value before the prefetch abort happened originally the mode bit was user mode ok correct the 5 bits were referring to user mode. So, since we need to you know bring back the user mode context the same as how it was prior to the abort we are trying to get both the CPSR to be initialized with the SPSR because SPSR where that value was loaded right stored by the processor before the abort was handled. So, if we move this into the CPSR what happens? It becomes user mode correct. So, the ARM processor enters the user mode as soon as you copy this value into CPSR. Now once CPSR is hold having this value this bank register the abort bank registers would not be visible because it has become user mode. So, you cannot access the R 14 of abort mode to get the PC ok ok you may wonder ok why are you doing this let us do this first, but once we do this you know the execution will start and the control is now no longer with the handler. So, the PC is loaded it will start fetching the new instruction from this location and. So, it will be it there is no instruction to say now you have to copy the CPSR also ok. So, you cannot the processor cannot load the PC and SPSR separately it has to be done together by in while executing one instruction which instruction it could be any instruction where we are saying RD is a PC ok that is what ARM has designed such a way that when S bit is set ok and RD happens to be a PC this processor is not expected to only copy PC it is expected to copy the current mode whatever mode it is being it could be abort mode or it could be a supervisor mode or it could beyou knowand defined mode or SWI anything whichever mode the privileged mode the processor is ok because each one of them are having SPSR in each of them. So, whenever PC is modified with S bit set the processor automatically copies the SPSR value into CPSR. So, what happens is both PC and SPSR CPSR get loaded together. So, please remember this is a very important concept which will be done in all this modes wherever the you know the modes are modified from one to the other ok. When you are coming back to the privileged mode to user mode or system mode or whatever mode you are transferring when mode changes happen the CPSR has to be modified and that has to be restored from the SPSR. So, exception handling or interrupt handling will be following this always ok I will be referring to this particular thing again in theother handlers also . So, this should be the last instruction executed after the by the handler. Once this is done it comes back to the original mode it was in ok. Please remember it is need not be user mode the prefetch abort could happen from any mode. So, once the prefetch abort handler is handled it comes back to the original mode it was in by executing this instruction ok. It is a very important concept if you understand please re run this particulartalk and try to let the concept behind this ok. This is very crucial and this is going to be followed in other places also in the exception interrupt. So, I would not be explaining this every time. So, copying both is a must. So, SBIT is set and RD is when RD is RPP and SPS happens to be set the processor automatically copies PC as well as SPSR from SPSR ok it. So, that is what happens I am sorry. So, SPSR is restored and then mode is also changed ok. So, this is the reason why SPSR from SPSR is done and PC is loaded from R14 because once SPSR is restored the mode will change from abort ok making the abort mode registers inaccessible. Change it from abort mode. So, I am not saying that whether it is change it to user mode or system mode whatever mode, but abort mode to some other mode it changes because of that the abort bank register of abort mode will not be accessible once the mode changes in the SPSR that is why both SPSR should be accessed as well as R14 should be accessed together. So, that how will you inform the processor by writing an you know instruction like this. Please remember in the instructionthe handler the abort handler you cannot write sub to PC or quoting abort. If you write no harm what will happen is the compiler or assembler will not give you any warning or error, but what will happen is your program will not be correct because it will not come back to the old you know previous state. SPSR will not be restored from the SPSR. So, you will lose the old it will continue to be in the abort mode. Though it will come back to the code what was running earlier, but the mode will not change. So, please remember code it may be accessing what user was accessing user mode was accessing, but mode is not same in the bank registers will be different what the program sees. So, it will be totally erroneous whatever happens after that. So, you have to be very careful when you are writing handlers ok. Now, I have a question take 2 minutes because I have already explained this. So, you should be able to get the answer quickly ok welcome back. So, all of you must be sure about the answer yes the option is C. I explained you earlier also that if a particular code is not to be executed the system developer would have made sure that maybe you know whatever is needed I have a memory and beyond this I am not bothered about having a memory, but pre-fetch what it does it goes beyond the memory and tries to access something. So, you might encounter the abort because the memory limit is exceeded not because your code has gone out of control it is because of the processor trying to do a pre-fetch ok. That is why ARM processor designers have well thought of about these kind of scenarios. So, they are they are giving that abort only when the situation happens that that instruction has to be executed that means that instruction is needed for the process of the execute then abort is raised. If it is if it is just due to pre-fetch, but actually the program is not using that particular anything beyond that memory limit then there is no need to raise a abort. So, so this is the reason for delaying the pre-fetch abort till it reaches the execute stage very good. Now, data abort is little more complex ok pay attention I hope pre-fetch abort you are now an expert. Let us explain now let us see these two if you understand I think the most complex part of the ARM core is taken care of ok. And then rest of it is very simple because abort handling is the most complex part of any processor and I am trying to explain you know as much as possible so, that you you understand this fully ok. When a data abort occurs the action depends on the instruction type ok. In the previous section I told you what are the instruction could pass data abort ok. Please remember there are few instructions anyway I will be covering one after the other now and we will see. What are LDR in this they are load register and store register instructions. If ok now take an example this is the instruction ok I hope from by looking at this you should be able to understand what it means. Let me explain assume R 1 is having a value may be 100 R 2 is having a value 200 ok. Now, let us put this is the memory ok. Now, what are we trying to do here R 2 whatever is there in R 2 has to be added with the 4 ok. And in that place in that location whatever is the content has to be copied into R 1. Now, I said R 2 is having 200 it is added with the 4. So, 204 is the location in the memory which is to be accessed ok assume it has it is having a value 2 ok. Now, this needs to be copied into R 1 that means, it should be overwritten with the value 2 ok. And then right back is there ok what does it mean this R 2 should be incremented to 204 now because that access has happened. So, R 2 will become like this R 1 will become like this. Hope you understand this instruction once you put a right back that means, this computed offset value is written back into R 2 ok. And it is accessed first and then modified because it is inside the square bracket. So, that value new value is accessed and then R 2 is written with the new value. So, R 2 plus R 4 is 0 4 is done and it is accessed and then now R 2 becomes 204. I am saying that there is a data abort what does it mean the 204 is not in the memory. That means, it is not only one location missing from the memory it is assumed that up to 200 the memory was there physically memory was there. And then from 204 to higher address may be that page is exactly the you know your page see remember that page boundary can happen at any word boundaries ok. So, at 204 when it was trying to access is that memory is not there in the page is not in the memory. So, data abort has happened. Now what needs to be done this particular memory has to be gotten and the same instruction has to be executed again. So, when this needs to be done again you have to bring back the pipeline then this LDR is executed ok. Cold memory see this is nothing to do with the memory this data memory this is data memory ok the 204 or 200 whatever is there in data memory. So, cold may be in some other location which is some 1000 ok our favorite address and this LDR was there ok. And then 1004 and 1008 there are some other instructions ok add and then sub. So, add is here ok and sub is here those instructions are here. Now when this LDR is executed because the data abort happens only when execution happens please remember prefetch abort happens when the code is fetched from the memory because that time itself it will be known, but the reaction or handling the abort is deferred till the execute stage, but actual abort happens during the prefetch stage. Whereas, any data abort happens during the execution because data is from memory is accessed only during the execution not during the prefetch not or not during the decode. So, now when it is executed this abort has happened and what happens similar to what I mentioned in the abort mode there are 2 registers right as I told you R 14 R 13 ok. So, R 13 we do not bother right now R 14 anyway is required, but we are only looking at R 14. So, this R 14 is loaded with a PC which PC which others would have been loaded now assume that when this LDR was executed which is at a location ok LDR is at 1000 I said right LDR is at 1000 and then this abort has happened which what was the PC value will be it will be 1008 you agree because already this is accessed plus 4 is accessed plus 8 is being accessed and then abort has happened. So, R 14 will be loaded with a 1008 ok. Now, it has to be rerun this execute the same instruction LDR has to be rerun means you have to bring back not this 1008 1000 you have to get back to the PC that is a separate then the SPSR is there that is a separate thing apart from that it right back is also there. So, the R 2 register should also be preserved ok it should be it should not be written with a plus 4. Otherwise when this same LDR instruction is executed it will start executing not from you know 204 it will start accessing 208 because after the offset is added. So, R 2 should be old value should be there ok. So, what I am saying is when write back base register is specified instruction then abort handler must be aware of this why write back it should be aware the handler should be aware of the write back because whether this base pointer base register is modified or not during the execution of this instruction is should be aware ok. So, in case of loading instruction the arms are under pressure prevents overwriting of the destination register. So, when you are in case if you are loading into some register you have to the processor as to make sure that that base register is not overwritten with the value from the memory ok. That means, this R 1 should not be modified because if you want to execute this LDR again the R 1 should be old value and R 2 should be old value to the maximum possible. Now suppose memory correct data what has happened some wrong value would have come into the data in the register. So, you should not be copied into R 1 that is something the processor will make you know has to make sure that R 1 is not copied and the R 2 is also restored with the old value. So, that when this instruction is executed again it will run it the same instruction will run properly without any problem. So, that is what seems to be taken care of during the abort when you are running the LDR. Now let us assume swap instruction. Swap does actually two things right it copies this is a destination register ok R D. So, it copies what is in R 2 and then it writes back R 1 ok into R 2. So, one read this is one read and then one write this is a swap. So, data abort when can it happen it can happen in either during this time or during this time. One typical example will be you know can you give an example where read goes through properly, but write results in an abort and it will be difficult to correct it in the abort case also. Suppose a ROM memory is by chance is accessed for a swap look you know because of illegal pointer or something you know some pointer corruption you are trying to do a swap on a address which is mapped to a ROM. So, reading could happen properly because not a problem with reading a location from ROM, but if you want to write into that then there will be abort. So, this cannot be recovered, but I am giving an example where the abort could happen in either read or write. So, abort on read access suppresses the write access ok. Once abort has happened because you know that first read happens after that write happens in a swap instruction right. So, if there is an abort in read then the processor make sure that there is no write cycle followed by that it abort no it does not allow this write cycle to happen that is what we say suppresses the write cycle as well as it does not corrupt the value in R 0 it does not write anything into that as a result of this instruction. So, it will be abort will be handled and the same instruction be executed again. Whereas, if abort has happened during the write access it only suppresses. So, you cannot read as already happened ok. So, write is also happened, but abort has happened during the write then only copying the destination register is avoided. See what I mean this thing is the processor internally handles this because you know the processor only is executing this instruction. So, it can know when an abort has happened during the execution it it knows what to do with the execution ok. It is executing the instruction and the half way to be stopped. Now, what all can be done what all cannot be done this are all well defined because the processor everything that processor does is all predefined. The designer should have already thought about it and if suppose abort happens during the execution what all it can do or what all it is not supposed to do is already predefined and put into the design. So, that is why I am saying that when the write back is there it knows write back instruction is being executed. So, processor is aware of what instruction is executing and it is aware that during the execution of this instruction I have encountered a abort. Now, these are all the design decisions taken by the process designer that the processor will handle this in this scenario like this. So, that the recovery is possible and then running the same instruction after fixing the problem is also correctness is assured. So, to achieve this these are all the rules put into the designer in the design of the processor. So, if suppose write access during the write access abort has happened it suppresses the write into the destination register. That means, what the old value of R 0 is retained that is all because if you remember the data path there is a data in register the memory content comes and then it gets written into the destination register. So, this will not be done by the processor because it knows that this execution is halfway through stop. So, processor can take action please understand all these things you have to know remember the context in which the abort is happening and what is the processor doing. So, the whole concepts and the context and the pipelines should come in your mind to understand these concepts ok. Now, we are getting into a more complex instruction ok. This needs a lot more understanding let me explain you what is LDM load multiple understand that I a means what increment after. So, what is the register base register is R 2 assume R 2 is having a value 200 ok. Let us try to understand what is this instruction mean and then we will see what is the reaction done or what is the action taken by the processor when there is a data abort during this instruction please understand the instruction first ok. So, what are we trying to say here wherever R 2 is pointing at ok whatever address from that address on this copy how many register R 1 R 2 R 3 R 4 4 registers you copy 4 ok. Let me tell you 200 ok let me always say that ok this is lower address and higher address you know to make it easier to understand ok. Sometimes I have understood you know I have drawn the memory in a different direction. So, 200 200 4 ok 208 203 now some value is there in this memory needs to be they all need to be copied into this registers R 1 to R 4. So, which location will come here this will come to R 1 should come to R 1 this content of this should come to R 2 R 2 not 2 8 should come to R 3 and 204 should come to R 4 ok. And then R 2 should be incremented after that means, what you access this and then increment it that means, that is why I said originally it was having 200 means the value at this the patient will come to R 1 then only it will be incremented. So, it goes up R 2 goes up now after the execution is done when success of course, this is successfully done what will be the value of R 2 please remember I have intentionally put the base register as well as I have mentioned the same register in the register list ok. So, originally it was having 200 and then processor takes that value ok it puts it in the address register ok which is connected to address base ok the if suppose if it is supposed to access from 200 to 204 no column the lower address is 200. So, that is put here and then it will do a sequential access of 4 addresses ok. So, keep on accessing those locations one after the other you remember first is non sequential access and then 3 sequential accesses will be done. So, that you will have a sequential memory access memory accesses happening and then now R 2 value will be loaded with the new value which has been in the memory assume that there is a value 4 supports here. Now, R 2 will be having a 4 please remember R 2 is not though it says the write back is there ok R 2 is not incremented to 200 C ok if normally should have happened to not see the new address should have come here, but because R 2 is also in this list is remember the base register and the register list can be same. That means, you are using this as a base register, but you are copying a new value the loading a register from the new value in the memory and overwriting the base register ok. So, it is supposed to have been copied from the memory with a new value which was here in the 204 these are all good when there was no memory abort data abort everything should have happened without any problem ok, but I am saying that there is an abort happened. Now, what should the processor do ok to bring back to the original state to the maximum possible stage. So, that this instruction can be executed what I mean by maximum possible I will explain you same memory ok 4 locations are accessed and then the registers are copied R 1 to R 4 values are copied assume that when it was trying to writing to R 3 ok let us assume that R 2 is also written into ok. If you remember the world value was 200 right R 2 was having 200. So, 200 was there 202 204 was there, but 208 where the abort has happened ok it was not there in the memory. So, this is successfully overwritten this is also overwritten, but now R 3 when it is trying to access the 208 now data abort has happened abort ok. Now imagine what has happened R 2 which was a base register is already overwritten with the value which was in the memory which is 4 if you remember I was saying that it is having a 4. So, it is overwritten now how will the processor can either get this value back because it why should it get the value back because it has to execute this instruction again when you have to execute this instruction it should be back to 200 then only the original intended action can happen, but if that R 2 has been already overwritten with the value in the memory it is lost forever is not it, but what does the processor do ok. It has got a recovery mechanism in this case I will tell you how it recovers ok assume the processor you know that it has got a address the register where it has put the original address 200 and then said it has to be incremented the for 4 times to access the memory. Now what does the processor do ok when in between there is a abort it knows the original address it started with ok and then please remember the whole instruction which is to be executed is in the inside the processor. So, if you recall the register list ok register list is mentioned in the instruction itself with the bits 1 to indicate that which registers are to be loaded or stored ok. Now see you assume data abort has happened something in between somewhere in between what does the processor do it will bring back ok before giving a control to the abort handler what does the processor do on its own it knows which are the registers are to be copied from the register list correct you agree because it has got the register you know instruction inside the processor. So, it knows which are the bits are 1. So, it knows in this instruction whether how many registers were supposed to be copied in this now example it is 4 register it knows ok and then it also knows whether write it back was there or not ok because one of the bits here indicates that write back is enabled and then it also knows which is the base register it knows R 2 was the base register. So, and it also has the address where it is started off with the instruction access you know data access. So, from the register list it will know how many registers are to be accessed and it knows that whether it is a word access or a byte access right LDA in any way in LDM it is all a word access. Ok. So, it knows it is a word access. So, you agree that it can build get back this 204 203 the last value if suppose this instruction was executed successfully what would have been the value of R 2 it knows because it knows how many registers are to be accessed and then it knows it has put the value in address register. So, it can keep this value somewhere ok before the memory cycle starts because you remember once the memory cycle sequential access starts this will be incremented. So, it it can still you know build that back because 4 would have been you know 4 times would have been incremented because from there it would have you know it will be maintaining a counter to say how many times it has been incremented to access the from the memory. So, it somehow it can get that the value 203. So, when the above handler is control is given R 2 is put to not see ok that means, what would be the value of R 2 if the instruction would have been executed fully that value will be put in the base register please remember it will override though the new value was copied from the memory it will again restore it back to the base address because it is going to be aborted now. So, if this instruction has to be re executed. So, R 2 should be having a valid value, but instead of putting a actual original value it started off with because that was overwritten by the memory it at least gives you a part by which the controller the handler can come back you know override the value with original base register and then execute this instruction again. To enable that it will load the value of base register as if the instruction has been completely executed ok and then it gives the control to the above handler. Now, above handler can also read the instruction because it knows which memory location R 2 pin it knows which memory location the above happened. So, it can read the instruction and know how many registers you know where they and then it can reconstruct this value if from 4 registers were there and it was increment of error or decrement based on that it has it will know whether plus 4 or minus 4 into 4 ok needs to be done and that operation can be done and it can recover the R 2 value also, but what happens to the register R 1 which is copied it is permanently lost. So, any register which has been copied from memory is lost, but it can reconstruct to the maximum extent and then it will rebuild the instruction again ok this is what happens during the data abort. So, hope you understood this it needs little more of thinking and understanding of what is happening. So, if you do not please again read through that or hear this particular part of the talk you will be able to reconstruct what happens. So, the write back is specified the base register is updated ok. So, if the base register is in the transfer list R 2 is there in the transfer list as already been overwritten ok with loaded data by the time that abort is indicated I told you that abort has happened after the R 2 is copied. Now, the base register reverts to the original written back value as if the whole transfer had taken place that is what I am saying it will it is it is it comes back to the original transferred ok as if original transfer has happened and then the write back value is write written into not the copied value ok. So, once the write back value is there the handler can reconstruct the instruction R 2 value and then rerun this again to load these values again ok R 1 and R 2. So, why why is it so important these are all is required. So, the after the abort when you run this execution in the same instruction again you will get the same effect that it would have got prior to the abort ok that is the intent. So, for that you need the original base address original base address if you do not have then the instruction cannot be rerun again because it will access some other location not the original base register ok. So, that is why this whole thing is done this way and then the execution starts again ok. So, so whatever the processor is doing is only enabling the handler to take care of the remaining part. So, handler has to do a lot of job it has to reconstruct the original value and put it into R 2 as well as fix any page which is not there in the memory to draw back and then rerun this it has to compute the value which has to be which is pointing at the same address instruction which is cost which cost the abort. So, that it will be executed again. So, the data abort handler also has to do a lot of job, but simultaneously the processor also has to do a enable for the handler to do its job ok. So, on then the processor prevents all register over a thing with the loaded data after an abort is generated. So, it cannot prevent it prior to that because as the value comes in it is getting written to the register ok. So, once the register is copied with the value from memory it it is gone the previous value is gone. Only thing is it can recover as much as possible suppose when the abort happened after that it will not allow any copying to the register. Suppose up to R 2 it is copied R 3 and R 4 are old values ok that is what the processor does ok. This means that the final value of the base register is always written back value if the write back is 65 ok this is very important. If you read this in the manual you may not get the background of all this. So, I try to explain with an example in this talk. So, you will be able to appreciate what is happening and why a processor does all these things ok. This is very very very most difficult part of the architecture ok. If you understand this you know it will be very very easy for you to you know realize what is happening inside a processor ok. So, understanding this abort you know will give you a clarity ok. Now, I am giving you another scenario where the list is very huge list R 1 to R 15 almost all registers from R 1 to R 15 are copied ok from memory overwritten R 0 only is left for some reason ok. I have just given you the example code like this. If such an instruction is there ok if there is a R 15 needs to be copied or you are sure that the registers are copied from lower register to higher register ok. I have already told you whenever there is a register list mentioned the first register list which iscopied with the value from memory is the lower number register ok. And then address which is success is from the lower address ok lower to higher address and lower register to higher register that is what is the way copied orcopying from memory also or writing into the memory also is done in the same way. So, that there is a consistency between storing and restoring the values. So, this actually indirectly helps also that R 15 is not affected if there is a abort. See worst case abort could happen when the last register is accessed you agree it could be the last word which is accessed is causing the abort. If R 15 also successfully are successful then there is no underwrite abort requirement at all. But if during the R 15 when you are trying to fill the R 15 from memory there is an abort then also the R 15 can be preserved ok. Because R 15 preserving is very important because if you want to come back to the old instruction and then you want to run it again ok this value should be proper otherwise you would not get this address at all right. So, this value should be preserved. So, R 15 is always preserved during the abort because it happens at the end of the term used. So, after switching with the abort the instruction can be rerun. Now this is the very very now you will be able to understand this why is the minus 8 very simple you see you have this load instruction which cause the abort ok. So, plus 8 would be the PC value see if please remember whenever abort happens the current PC is stored in the R 14 of the abort mode ok. So, when the return happens you have to the handler has to do the correction processor just copies the PC into the R 14 and forgets it because abort has to be handled. So, it does not have time or anything to even look at the value of this. One way thing is whatever PC is there is loaded now you have to subtract it by 8. So, that the instruction which cause the abort is brought back and you are sure that R 15 is also not overwritten even if it is in the register ways of load in a this is the worst case scenario ok. So, that means, you will be able to get back the old instruction with the previous R 15 value and then original base value. So, that you can successfully execute this instruction after fixing the problem which cause the abort ok. So, this I have already explained both SPSR and PC are the stored. So, that both SPSR and PC gets the old value ok. This is the most critical part of the execute code. So, we have handled that if the handler has copied the return address out ok. This another small caveat if suppose abort is happening repeated abort is happening suppose you are you got into abort mode you are running the abort handler ok it is supposed to be careful, but abort handler ok itself is causing an another abort it could be a prefetch abort it could be data abort ok. This scenario we should remember when recursive abort happens what have what really the happens is now one abort has happened and then you are executing that and another abort happened now it is there is only one register which is R 14. So, this R 14 value which is having the return address of the original abort ok from here the abort have came and then this has caused the abort. So, now this return address ok this address of this instruction will be copied into R 14. Now what happens the original R 14 value is overwritten by the new abort value return value. So, to prevent it this R 14 should be copied into the stack of the abort handler that is where the stack comes R 13 of the abort handler ok stack you copy that. So, that it is a very detailed thing I will be explaining you later on and just giving you an example here that if you are to support ok a re-entrant behavior that means the same abort handler could be called again then it has to save this R 14 and SPSR value ok that is also acquired because that also will be overwritten by another abort happening. So, these two values should be copied into the stack and then that is where at the appropriate time. So, that original instruction can be traced back and then the control can come back ok. So, that is what I am explaining here the restoration of the user registers and return may be you know if you want suppose OS is running and the user registers have to be restored that also can be done because handler will be you know overwriting those registers which are used by the original program. So, handler has to be take care of any register it is using in each program is copied into the stack before it uses and then restore it back in from the stack before coming back to the original address ok that is a typical thing. So, that can be done by this instruction ok multiple register transfers can be done and why this this indicates that it has to copy not only the PC value also the SPSR value into CPSR ok. Similar to that S and R D having this is another way of in a LDMA because you cannot mention a SCR right PC is there in the original list this is used to indicate that when this instruction is executed PC is modified from R 14 ok or actually it is from stack it is taken. So, it is from the stack PC value is loaded actually it is a R 14 value which was in the stack is copied into PC and the SPSR is copied into CPSR ok. Both should be whenever mode change happens this mode has to happen. So, that is what is done by the processor. This will be the last item to be transferred from the memory ok this will this is special form of instruction which indicates that when if you are using this instruction to restore the value on return from the handler ok. Please mention this at the also as a part of the instruction when PC is also in the list then the processor understands that you want the SPSR also to be restored. So, it will do the PC copying as well as SPSR to CPSR will be done automatically that is what it means ok. Similar to what I explained for the Moves ok I hope this is very clear to you by now little little more you know we are getting into another software is interrupt. This is if you recall I said unprogrammed ABOTS or this data ABOT and pre-fetch ABOT which you the programmer does not have any control on whereas, SWA is given by the programmer as a part of the instruction ok andwhich can create an exception ok. This is also a smallyou know you need to be very careful about thishow when you are writing a code ok let us explain and I let me explain you this is original conditional flag. So, SWI also can be SWI EQ you can put ok that means, if 0 flag is set this will be executed otherwise SWI EQ will not be executed that is the conditional flag ok. Let us now there is a common field assume that something is written into this, but the processor does not use this value ok. It knows this all one means it is a SWI instruction and if condition satisfies it execute the SWI instruction that means what. So,it enters a supervisor mode ok let me tell you one example. Suppose under location under you have put an instruction called SWI 0x level you might have seen it in the ARM simulator that this is very often written. Now, the 0x level is stored in this location and then the SWI instruction itself is in the address 100. Now, when this happens it goes to the way interpreted table ok whatever is the entry for the SWI ok that branch happens and then it handles the SWI handler will be called ok it is all very simple. Now, what happens during this time PC is copied whatever the PC value is copied ok actually PC minus 4 it will be copied into the R 14 of the supervisor mode and then as a CPSR is copied into SPSR of the supervisor mode. Please remember whenever SWI is executed the processor switches from whatever mode it is assume that it is in user mode it is switches to supervisor mode ok another mode which I have shown and then there are two registers bank registers R 14 and R 13 are used for that purpose ok. So, this saves the PC value and CPSR value into SPSR and then it goes to a death mode supervisor mode, but this parameter field is notused by the processor internally, but it is used by the handler. So, this is saves it into SPSR this values are saved and it accesses from the pixel operation 8 SCG handler is called. So, for so good ok the SWI rather rather this should be protected ok this is another side note. I told you earlier that this SWI is used for operating system calls supervisor call that means, it is a protected call the code which is OS only can be run. So, you cannot put a malicious code into this that means, what we cannot modify the location 0 x 8 which is a vector address ok should not be allowed to be modified by the user program why? If suppose user program is allowed to touch this vector address user can always write a branch to his his or her own code so that he can indirectly take control of the processor because as soon as SWI is executed it enters a supervisor mode. So, supervisor is protected mode, but if you allow the vector table 8 which is actually a supervisor handler ok the SCG handler if it can be modified by the user then you have given a back door entry into the processor to allow process you know the user code to be able to control what is put here. So, it should be the OS code which comes up first should be initialized it and nobody should touch it. So, that is why I am saying that this vector can be protected so that user mode we can even implement OS and protected. Now, you can run operating system code from the supervisor mode ok ok it needs some OS background, but I hope this clarification this explanation is clear to you. Now, how does SWI return from the handler ok it is process now handler is executed now you should come back to let me ask you one question should it come back to the same SWI or should it come back to the next instruction? See data about prefetch abort that instruction cost it was not completed. So, some fixing was done pages was brought and then the same instruction was executed in the prefetch and data about this whereas, in SWI this is not like any other instruction. So, it is executed as soon as the handler is run fully. Now, after this it should come back to the next instruction not the same instruction please remember ok that is what is the intent. So, what is done it does this move a PC or from R 14 of the SVC mode please remember this is a supervisor mode SVC mode is supervisor mode it has got R 14 register this R 14 register has the return address to the next instruction of SWI ok SWI was here if it was 100 the 104 is the address which is stored in this and ok the processor takes care of initializing the return address next to the SWI instruction similar to what it was doing for branch if you remember branch with link it was copying this address in the next address into link register right it does the same thing because it is similar to the you know branch instruction because the control has to come back to the next instruction that is why processor takes care of giving you the address which is next to the software introduction. So, it has to come back to that by just copying that value into PC ok. So, note that the link mechanism is not reentrant this if you say if you want to make it reentrant then R 14 will be overwritten similar to what I explained you earlier R 14 and the SPSR needs to be copied into stack if you want to make it reentrant please do not bother if you do not understand it now when I talk about reentrants and the interrupt handling it will become clear as you later ok only thing is what I want you to remember that is if R 14 is used ok whenever SWI or any you know the in this case SWI is encountered R 14 will be overwritten with the next instruction. So, inside the handle if you put another SWI it will again put a it will overwrite the value of R 14 that is what I am trying to say. So, you have to save it in stack if you want to restore it. Now, how do you process the SWI handle how does it process the value here ok this 24 bit is used to communicate some information to the processor or not the processor handler ok handler only uses this value what is in the instruction ok. So, that supervisor functions can use this value which is passed by the programmer. Now, this is similar to any other instruction I leave it as an exercise to find out how 2 s plus 1 n is taken by SWI I am not going to explain that. Now, I will give you an example handler ok this is a SWI handler. So, prior to this what all happened it has stored the you know it has stored the location from where the SWI was the you know SWI was called from here with some value 100 suppose ok. It is at the location may be you know 4 0. Now, 4 4 is the next location where next instruction is there. So, it has stored the 4 4 into R 14 of the supervisor mode ok and then CPSR value is copied into SPSR and then control went to 0 x 8 if you recall this is a vector table address from there it is branch to this routine has been called. So, handler is come this is the first instruction encounter. Now, it is executing this STM FD that means, what in the stack ok full decrement that means, currently it is copy you know it is pointing at this location this is stack point at R 13 of the supervisor mode SCC mode ok R 13 of the supervisor mode is you know suppose this is some 500 it is looking you know it is pointing at the stack which is a full location ok this is the standard it is using this particular way of stack manipulation that means, while storing it is decremented which is pointing at full that means, why it is decremented before copying any value. So, it is copying what are the values So, decremented means going towards the lower address this is will be 4 naught 4 fc right 4 fc ok. So, it is going down now how does it copy from the lower address to higher address please remember the stack will all you know LDM copies from lower address to higher address so, let me how many values are there R 0 1 2 3 4 values are here and then 1 here 1 here so, totally 6 values. So, this should not be touched because it is full so, 1 2 3 4 5 6. So, after this execution the stack will have gone down so, much and the value will be lower address this is the lowest address right from 500. So, R 0 will be copied here R 1 will be copied here R 2 is copied here R 3 is copied R 12 is copied and L R what is L R R 14 ok which register it is it is a bank register of fc please remember it is not the original user mode or free or some other mode it is a fc mode R 13 it is pointing at a stack its own stack and then it is pointing at a full location. So, it cannot be copied where it is pointing at and full decrement means it has to be decremented prior to storing. So, the storing happens into the stack you know by pointing by the SP SP is operating and there is a I will erase this so, that you see the you know you see that there is a exclamation mark here that means, right back has to happen stack has to be advanced. So, it is brought to this location whatever the lower value is now what happens it has saved this value so, that this instruction this handler canuse those registers ok it is saved into its own stack and then what does it do it copies the SPSR value I told you that if you want the SWR to be re-entrant it has to save the SPSR value ok as well as R 14 R 14 is copied in here SPSR is you cannot access the SPSR or a SPSR directly you are in a you are in the SVC mode now. So, the processor is in SVC mode so, it copies into R 0 R 0 now it can be overwritten becauseit has been already saved the previous value has been saved ok. So, the handler can freely access theR you know R R 0 here ok. So, it copies that SPSR into R 0 and then store loads it into stack that means, it is SPSR value comes here ok. So, effectively what happened R 14 and SPSR are the values which are being saved by the processor prior to coming into the handler now they are into the stack now. So, now one more SWI is executed it can freely execute because these values are saved into the stack. So, it will go below and then it can come back recover back from the handler ok that is the reason whywe are saving this value ok. Now, what happens please pay close attention to this ok now it is doing a LDR R 0 LR minus 4 ok. So, let me create some space for you see assume that originally the instruction what was executed was in the some place we have it there ok 44 ok. So, LR is actually this 44 is copied into LR you agree before the processor came to the abort handler. So, the R R 14 is having value 44 which is the actual instruction next to the original instruction which cause the SWI this exception. So, when you say LR minus 4 it is accessing this location and then whatever is the content of this location what is the content actually instruction itself is copied into R 0 the original instruction SWI instruction which cause this handler to be executed is copied into R 0 is remember this is very very important because R 14 is already copied by the processor prior to executing the you know entering the handler it has already copied with the return address okwhich happens to be the next location after the SWI. So, that the value is there in R 14. So, you can always get back the instruction which cause the handler the exception and then it is minus LR minus 4 is done and then it is copied into R 0. Now R 0 we are interested in getting thatvalue ok I told you 24 bits are used for passing as a parameter to the handler how will it get it it has to get it from the instruction only. So, first the 8 bits 8 bits are waste you know it is not required by us it is required for the processor what the handler is interested is a remaining 24 bits of the instruction. So, it marks marks of the lower 8 bits and then gets the value ok you should know that it is you knowinvert of this will be done. So, all this will be 0 and then ANDed with the value this all will be 1. So, if you ANDed with the original instruction you will get back this 24 bit value in R 0 ok. Now R 0 has only this 24 bit value all these are all removed and then it is jumping to a handler which may use R 0 value and then it can do whatever it wants using the parameter which is passed and then it comes back here and then it has to first copy this SPSR from there to R 0 ok it can copy to anything but R 0 is a register which can be used by the handler and then it is copied into ok it is copied into SPSR why SPSR because you have a in the SPSR you copied. So, you are restoring the SPSR value and then executing this instruction and which will apart from copying the PC from the R 14 see now originally R 14 was pushed and it is read as PC here ok R 0 to R 3 and R 12 and PC this value what is there is loaded into the PC of the user mode ok or whichever mode it came from and then when you have this charactermark then it copies the SPSR also into the SPSR. So, processor comes back to the original state after this I hope this is very very clear to you please you go through this part of the presentation again if you have any trouble in understanding this ok. So, and then there are some more special instruction this you know just R 15 means it will be copying R 15 into sorry from the stack it will copy into R 15 ok only one register if it is there when it is copying the value from the stack it also copies SPSR I have told you 100 times this SPSR also into CPSR ok that is the indication ok and then what does this mean there is no R 15 here, but R R 14 is there in in case then you have second instruction it actually copies the registers of the user mode ok. So, in a in a supervisor mode you have your one bank registers which are there R 13 R 14 of supervisor mode then in the supervisor mode this is executed actually it is used for the it is used by operating system it wants to save some user registers then it has to get the original R 13 and R 14 of the user registers not the bank registers. So, to enable that kind of a saving they have arm designers have enabled even with R 14 if you give this it will save the user registers rather than the bank registers ok. It is just an information in case you know OS what does it do ok in the privilege mode only you can use it not in the user mode you are already in the user mode there is no special need, but in user mode if you want to refer to the user mode register the R 13 R 14 of user mode register and not the bank register it is not only R 13 R 14 suppose in FIQ ok in your FIQ mode and you are executing this instruction what does it mean from R 8 ok if you remember correctly R 8 to R 14 or bank registers in the FIQ. So, it will access instead of bank register it will access the user mode registers and then save it in the stack ok. So, and it will save it in the FIQ stack whichever mode it is this this will be a the mode from where this is executed and this is from the user mode registers ok R 13 will be the bank register and R 0 to R 14 here also R 13 is the that will be user mode register please pay attention to this at minute you have the base as well as the register list are common ok and it is getting overwritten also ok in this case it is not overwritten, but sometimes you can have a explanation box where the base register and the register lists are same, but in this case it will not be the user mode this will be a the privileged mode register ok. So, we have come to an end of the class and ok this is the last slide of undefined instruction what I mean by undefined instruction means there are 32 bit wide instruction right you know that ARM instructions are 32 bit. So, 2 power 32 instructions are possible in literally ok all 0s to all 1s how many could be there 2 power 32 instructions, but do you think ARM has that many instruction no is not it if that it had that many instruction all of us would have found it very difficult to remember all of them ok. So, the luckily that many instructions are not there even if that you are there the processor needs to handle all of them impossible. So, there are so many book holds in the instruction ok it is not that all the format all the combinations of the bits are used by the processor to indicate the instruction that means, the the part of the instruction which are not used by the ARM can be used for extending the instruction of ARM using co-processors or it could be there using an undefined in exception. So, not all instruction was a valid. So, if any of the invalid combinations of instructions are encountered what happens is when suppose PC is accessing this and then it encounters that this instruction cannot be decoded properly because it is not a valid instruction ok. During decode only it will realize ok this instruction is not following any pattern which is supposed to be done by the you know required by the processor. So, it is not a ARM instruction. So, what does it do? It still passes this to the execute stage and during the execute stage it pass the undefined in exception. So, you remember there is a undefined instruction mode also is there and there is a separate vector table entry is there which will be called and then same R 13, R 14 ok sorry for ordering with there only. So, R 14 is the where after the undefined instruction where it is supposed to come back return address is there and then stack is there. So, the handler of the undefined instruction can now say do something specific to the processor or a system. So, you can expand or extend the instruction set by using this exception that is what I am saying. So, instruction operation may not be implemented in software then a processor attempts to execute it in an undefined exception ok ok. This if you want to implement in software you can do a undefined exception and then handler will do the job. It could be like you know accessing a port or accessing memory or doing some mathematical rotation or whatever you want. So, any even you know you can actually you can give a pattern in the code which will is not one of the ARM instruction and then that takes to the undefined instruction handler and then the undefined instruction handler can do whatever it wants. So, it is similar to SWI, but it is another mode and then you do whatever is required for the particular combination. So, it can be expanded to anything whereas, SWI will be less limited ok. So, that is all about undefined exception. So, we covered most difficult part of the ARM architecture today. I hope you understood this even if you have some doubts please listen to this carefully and then think about yourself ok. You need to think you know you have to bring different bank of registers and then different stack and then when exactly an abort handler or if a pth abort is happening and then what is stored in R 14 and what happens on return you have to think internally internalize in your brain. So, that you understand the complete flow of what happens ok. It is easy to understand, but you have to pay little more attention to what is happening inside the processor ok. Even that is true with a SWI also. So, with this we have come to the 15th session end of QT session and I enjoyed sharing the information with you. I hope you also enjoyed it. Let us meet in the next session. Have a nice day. Bye bye.