 Okay, so here we go, I think this announcement has been already done, so please note that my course always need not ask, whatever is last exam till the last day, okay, whatever has been taught is a part of the exam and since it is a quiz, there will be some problems, so do being calculated. We are last time did little ahead but I will just go back a bit, we actually made the field oxides, either we made the fox using low cost process of this kind or we made SIT, shallow trench isolation, so either way we are now isolated the areas for transistors, we clean everything on the wafer then except the fox and then the silicon is also opened, everything is clean, RCA clean is very thorough that time, before any gate oxidation the wafer has to be ultra clean, okay, that is the major step for us for our MOS performance. So we edge back everything, clean it everything and the wafer is now ready for gate oxides and in other case right now I am talking of SiO2 but in other cases it can be high K in which case it will be deposition process but in this case it will be thermally grown silicon dioxide, typically it is depends on the technology node, it could be 20 A to 100 A or even earlier higher we used to have 300 A of gate oxides, typically these days in thin oxides are needed 800 degree centigrade which has the lowest growth rate probably is tried, okay and maybe so that you have enough time for oxidation. So we actually have grown, please remember that I forgot this, before that we had done two things which is not shown here, one is channel implants we did channel stoppers and in that case we also did PNN implants for making threshold corrections, what I mean by threshold I do not believe that n well concentration here and during the processing later will remain same and I want the VT to be adjusted but the surface concentrations, so I actually implanted NNP to get my N channel and P channel device, okay. So here is after that implants have been done and everything cleaned up and all that gate oxide has been grown, please remember that this process after this process the gate oxide is never is going to be exposed again and therefore this as I keep saying this is the process step which is very crucial for all future successes, immediately after the gate oxide has been grown we push the wafers into what we call as LPCVD reactor, LPCVD stands for low pressure CVD and typically around 1000 amperes of day of polysilicon is deposited. These days because of poly is not the best metallic system, we may try molysilicides, platinum silicide, tungsten, many silicides have been tried, moly is the most common one and for this right now I am talking of a standard process I say okay polysilicon, okay but in future processes this itself may get modified. Now after the poly has been deposited which is around 1000 amperes, we can either make an implant on this to make it by another masking step I can make one side N kind, other kind, P kind or we may not do it right now at all, okay that option I said when I do source drain it will be exposed and that time I will get whatever poly depositions I want or poly dopings I want. Typically I am looking for less than 10 ohm centimeter 10 ohm per square as the sheet resistance when I have a good poly, okay. So will P plus poly will have a lower sheet resistance or N plus poly? No, that is exactly why I thought after so many days you realize this, what is the maximum concentration boron can give and what is the maximum concentration arsenic or phosphorus can give. So it is always preferred to have N plus poly running everywhere because it will have least sheet resistance, okay and therefore even if I for a P channel device I will make P plus poly for the sake of gate but connection from there will not be P plus poly it will run on only connecting with N plus poly ahead everywhere and that is most important that the poly runners or poly interconnects are always N plus dope preferably arsenic doped, okay but as I said these days we are not looking for poly runners too much we may do silicites so it may not be that serious but essentially poly is very crucial for N plus polys. Then of course he said is not wrong mobility has an issue but the major thing is one order higher concentrations possible, okay interconnect from one transistor to other, poly will run poly as a runner, okay. First you will have to start with gate so there will be a poly so first layer may be a poly interconnect internally, okay. If you do a design course or you must be doing it you will say unless there is a poly interconnect we will have a difficulty in running metals, okay. You need too many bridges then, okay. So the first runner is poly, first runner is poly, runner is the word used in design for interconnect, okay. So first runner is poly, okay. So this was what we last time discussed, we have a poly which is either dope, some people dope it now but most people do not and doping if at all has to be done is either by implant or by solid state diffusion or during the growth of poly itself it can be dope by phosphine or diborane, okay. We can add gases along with that so process itself will do it, okay. However as I say rarely people do this but I just thought it is possible. Why I wrote this specifically because poly is also used particularly for RF and analog blocks as the resistors but or even in memories, static runs. So in static run the load many time is these days because of variety of reasons can be resistive even in eProms you need now some what we call interconnect switches which also will require poly. So in those days we will require doping. So this is one possibility how to dope a poly. So either during the growth or during the positions or by implant or finally if you are bad enough everywhere then do solid state diffusion, okay. So till then we did this last time then I start now or maybe I also did this I am not sure. The first thing now I want to do is to create my gate because this is the most important lithography once again I will say because this will decide the W by L of the transistors, okay. So the etching here, delineation here of the gate is the most crucial factor in deciding the RE characteristics of the transistors because here is where I am going to fix up my width and length of the channel, okay and therefore this is very crucial for me. So this step though it is like any other lithography step but it has to be handled very carefully because it is here where if I make 10 percent error I may make 100 percent error in my performance and therefore I am really worried how much error I may because then there will be shift everywhere sometimes I may not have even channels, proper channels. So we are worried here of masking correctly and this is the step which takes care of your circuit performance requirement. We are deposited power resist as usual and etched out the resist by developing, etched out the poly wherever I do not want gate, okay. So you can see from here this and this gates are let us say to be connected in CMOS. So where they will connect, gate connected inside the plane, okay I mean if you go down on the plan then I can connect like this, is that clear or what I should say. If you see a normal CMOS inverter this is what we, this is a P channel. So this gate connection actually is on the, because this is a circuit but in a cross section I cannot show these two points because if I am taking across something here I cannot show the connection but this connection is also possible during this masking itself. So connection between two gates is also possible during this lithography itself, okay. So you should learn this plan elevation cross sections, side elevations whatever it is, okay. So once this many a times here there are possibilities of some options people do for reliability. Some people actually retain the old oxide if they are already done good gate oxide before, some do not and they really etch out. So there were PhD thesis from Sanford which proved that having a fresh oxide is better, okay. For just this a PhD, okay. So think of it why so crucial, okay. After this the first thing we want to do is what we called as for the short channel devices particularly for the channel length less than 90 nanometer or 1.1 nanometers or 0.1 microns actually less than a micron itself all short channel effects are seen but at least below 0.35, 0.25 you will certainly see huge number of problems. So one of the problem which we say is due to the scaling the voltage as I am not getting scaled where our lengths and widths are, okay. So the electric field across the gate oxides as well as across the source drain regions are not scaled down by same proportion as width and lengths and because of that the electric field enhances everywhere, okay. That is our major worry because as the reduced channel length and our voltage is not scaled V by L will increase as compared to normal scale device and this enhanced field both across the gate and across the lateral channel has an issue which has to be sorted out because this additional electric field at the corner of drain particularly one finds that it may allow carriers actually to go into the gate oxide, okay. This is one reason how EPROMs are, this is the process of EPROM writing which may happen without your actually wanting. If charges go into gate oxide what is the worst thing may happen? The threshold will shift. So everything is moving away from what you are designed for. So most crucially you must realize that this LDD called lightly doped drain structure. So to reduce the electric field near the drain and also on the source side, of course there is a method in which asymmetric, they say source area will not do but only on the drain side. It is called asymmetric LDDs but right now standard process both sides, okay. So lightly drained doped they have a depletion width, please remember depletion width is proportional to 1 upon root n, okay. Now lighter this, the depletion width will larger. So it will not be concentrated near the drain but it will also be spreading below the lower regions of the drain on source regions. That means the electric field at the corners will be comparatively lower as compared to shorter depletion widths, okay. This issue is very important in most short channel effect device. The other problem of course is what we call channel length modulations. The third problem is Dibble which is called drain induced barrier loading. So Vasi we asked much more on this before I start, because either I start teaching that course which I do not want to. So if I am really looking for my problem on short channel, I must do something and one of the possibility is to do lightly doped drain structures. Then another thing which I have shown here is also called Hello which also is for the same reasons at least to reduce the depletion width going too far away. So this is called limiters, okay. But in this case there is no Hello shown. The basic process is that, please remember what we are trying is at the drain end, we want n plus p plus to occur for n channel p channel because there is weather resistance is going to be, okay. So I want source and drain should have very highly doped regions but very highly doped regions may create higher fields at the drain end because source will be grounded. So drain will be essentially have huge fields. So to spread out that field, I will reduce the doping near the drain and that process is what we call as lightly doped drains, okay. So what we do is we actually mass, let us say I am making first for n channel device. So I mass this envelope area and then do some phosphorous implants, okay. And since all implants will follow, of course this you can see here I have not kept poly covered since it is n and I am looking for n channel. So even if it goes into poly, I am satisfied, okay. So I may mass that as well but I do not because I say it is a n plus poly I may as well let it go. But in this case also it may happen, I may also have a P so I may have to compensate during n plus P plus that this P which I unnecessarily got there has to be first compensated. So there is another people who actually mass this area, gate mask. So they put resist keep there and done implant. So there are methods which need additional mask, additional problems but otherwise can be done. So since you can see it will follow H and during its little drive-in cycle it will get inside the gate a little bit, okay. Similarly I mass the P well area for n channel device and then I open for P channel device and I do go on implants. Please remember this dotted line was what was that? This was the threshold correction substrate equivalently saying substrate for the device. Well is not my substrate, substrate I created, above which shallow implants. So I have a P plus, instead of P plus what? P implant I will do that is lightly doped P, lightly doped N and therefore arsenic was not put there phosphorus was put. So I was worried that it should not become N plus apriori, okay. So that is the trick, okay and energy should be smaller because I do not want deeper implants, okay. I have done this both then of course I may do arsenic implant for N plus or this. Some people also do arsenic instead of phosphorus but I am not the one who suggest that, okay. Then you can see both mask are complementary, okay. So I can keep same mask resist change, same resist mask complementary, either way it can be done. So now I have both sides, LDD structure for N channel device as well as P channel device lightly doped regions have been created. Please remember gate is protecting it, below that is the channel area there is no LDD, no doping which is only what is the doping in the channel only the implant which you have done for threshold corrections, okay that is the only implant there, is that okay. Now just for the sake of this word hello, hello implants are very word it is just something I have another sheets which you can see mask maybe I should I do 6th. This is an hello implant or what is hello is essentially what we have done is that earlier P or N implant for threshold is there then we did LDD but before the LDD started we actually have another implant and that implant is the substrate implant is that clear. Hello is made for substrates, hello is not N plus P plus but it is for the substrate corners. This was your substrate and I have made another implant there, is that okay. And this is please remember for N plus source and drain extension of course we will create but we will have hello of what kind boron, okay boron is also a P well here so boron is the same as P well there was already P threshold corrections but this implant is not being the channel this is just at the age of the channel. So below the LDD implants you actually have hello implant then LDD implants is that clear first you have hello implants which is same as well and then opposite of that to make a LDD you have N or P implants is that point clear hello is same as substrate implants I mean as they are well implants. So if you have P well you have hello of P type, if you are N wells you have hello of N type, okay. This is called hello this essentially is trying to create ages of the depletion region restricted only to that much place okay a good figure may be coming and then see. So this is what hello implant for so this is a what is SD implant SD means LDD, SD implant is essentially in this what he has written extension as is called extension is for LDD. So SD is also it will be always N plus P plus for N channel P channel not plus but N or P whereas hello will be the well implants please remember this part the hello is essentially substrate additional corner doping for the substrate okay is are the wells at the age of source and drain. Another argument you can see from here so I can also do now the other you can do P plus implant for source drain or P implant for source drain and N for hello is that N well means N for hello and P plus P implants for source and drain same way for the other side. So I have made a hello prior to my LDD this is that clear so it is a prior step and you do not need additional mask this is important you do not need additional mask during whenever I was doing this I did right there both these processes. So how do I do it I just change the source and I just change the energies is that clear so one I want deeper the hello has to be slightly deeper so a little higher energy and in the case of N or P LDDs I will have a lighter energy because I want at the surface is that clear. Red colour is N or P for N channel P channel which is the source and drain LDD why it is blue ash region this is hello this is well whatever well that is same implant okay is that clear to you this fact has to be understood the many time people ask hello hello word was used for something like this maybe I can show you why it was called hello it creates a some peculiar shape and it gives as if there is a image of something shown. So first time an ACM picture has taken the word was found oh it looks like an hello around okay so this word picked up from an ACM picture so do not go any other credence to it there is no word essentially no expansion of HALO or something it is essentially when the ACM was from the cut picture was seen so someone said oh it is it looks hello around so okay so it is what the word is so please get into it how word starts but now it has caught up okay now it has caught up this is called hello implant okay of course as I say there are many other like the circuit as I said the technology which I chose from somewhere else they have what is called resource and range this is another process step but right now forget about that I just wanted to show what is an hello why the word was given hello okay because when I see that I did not see uniform this I says when all around oh I say it is hallowing all around okay hello is the word which you say like most Indian gods they show some hello around his face you know backside same hello okay so having shown you then the next process step so far we did LDD so far we did hallow if needed then I do spacer spacer as I said last time I discussed it but now I will show you where is it now after this I actually deposit on the wafer SIO to deposit word please remember you can even nitride in most places earlier once we used to deposit silicon dioxide it can be even nitride that process or deposition of SIO 2 is through low pressure CVD so this technique we have to learn what is how to do low pressure CVD and the process step if you wish is silent is the gas used for silicon so silent plus oxygen is SIO 2 plus 2 H 2 or if you are using dichlorosilane then SI H 2 C L 2 plus the oxidant is N2O okay so SI H 2 N2O is SI 2 plus 2 N2 plus 2 HCl normally I prefer not to have chlorine around chlorine has some advantages and some great disadvantages in 80s when everyone started everyone thought chlorine will do wonders we have actually spent 3 years to put chlorine inside and finally learned that it has not done as good as what we thought all of us many years may TCA was trying pure chlorine was trying SCL oxidation was trying to improve the NIT or DIT of the MOI structure and finally we realize it does reduces but it creates more drafts so 8 tereca advantage those are disadvantage so way which is better so mostly siren will be used the only difficulty with of course even dichlorosilane is poisonous greatly poisonous siren is not really poisonous but it is extremely flammable you have this this era so probably you will not learn you will not be knowing earlier in English anything which is flammable used to be called in flammable in flammable okay so now after this oxide is this I want to create side walls for the gate so you can see from here oxide was the why deposition process is important because deposition is normally LPCVD in particular is conformal what is conformal word means it follows the last contour if something has to climb it will climb if it goes down it will go down okay so it is a conformal process okay since it is conformal oxide what does it mean thickness every point is roughly the same every point thickness grown is roughly the same that has an advantage and disadvantage disadvantage is if I do it some normal etching in chemical not only this oxide will go everything may go away so I want to restrict that etching process only to all other except this sorry except the side walls okay so I figured out that if I somehow do etching which is an isotropic vertically down and I say okay I protected I etch this oxide on the top let us say some T oxide there I also can etch T oxide here but in this side is how much to T ox is that clear here is a T ox here is a T ox at this step there is a two T ox if my H ent is ionic agent is such that it only can h t ox then for them the right figure which you can see this will h down and this will h on this side but the side wall it will not because it was twice there is that clear so the upper portion goes away lower portion goes away this goes away but space between the side walls of gate you always find oxide retained that is called spacer is that point clear why it is possible because I am etching down and I believe that the way I etch it I will only h t ox only so upper t ox gone in between also oxide but sideways there is no way because ions were etching only vertically down okay and therefore I can create a spacer this is what last time I discussed spacer has its own advantage it does have some little bit of disadvantage as well there is something called boron boron depletion which is another worry but some other day okay so once this side wall formation has been done so do you think we are we are not used additional marks so far is that clear I deposited oxide and I etched it so there is no mask so far used by me I whatever last 7 6 or 7 whichever number I had how much which was the number then I just do not know which was the last number we have 5th mass no not 5th 8th 8th mass we are done so we are still not gone for the 9th mass still we are done now gate we are a slight spacer we are LDD we are hello but mask is only we are done almost everything what really device needs so why 20 or 16 see okay now first thing we have to do is please remember the purpose of hello let us say next step I what is the source in implant I should have very heavy dose and full up it should fill up everything so that the larger the depth what is the better thing the resistivity I mean the conductive it will be higher or therefore contact resistance will be lower the sheet resistance will be lower everything will go fair if I make deeper this but the technology may not allow now deeper source drains because there is a side wall capacitance issue I want to reduce that that means at least the minimum I should do is heavily dope that region I cannot reduce now increase the junction depths because that I will be barred I will be scaling it down for sake of capacitances say if I reduce that I will have increased that is one problem which everyone is facing smaller nodes the source drain depths are smaller thicker thinner and because of that the resistance of source drain is not smaller now okay compared to earlier when I have 2 micron junction I have a very low resistance now I have a 2000 Armstrong's or less then I have much higher resistance at the source and drains so the minimum I want is the surface concentration should be as high as possible okay so I do the source drain implant so first I do for a channel device so I mask the P where annual area for P channel area and doing this I open all region wherever and end transistor is going to come and that deep enough is what because it should be at least filling up the complete source drain areas if it is very shallow it will only go to the surface there was a P implant you did hello implant you did I want every area there we filled up with N plus is that clear I made a implant for threshold then I made a hello and then I also a side wall and N or P there and I want all that side on the left hand side of the gate should be heavily doped so I must have deep enough and higher dose implant so that that becomes N plus strong enough okay so that my resistance is smaller is that clear why my resistance is worrying me this is the drain and source resistance in a transistor if you see a even in analog for example one of the major worries of the source resistance is what anyone gain it is a common emitter with source what is called as degenerated source the gain will be RD by RE or RD by RS if RS is present there the gain can never increase may be 458 I want 100 so this source resistance in analog is very crucial for us okay. However therefore we never go for 22 nanometers sorry I will work 0.25, 0.35, 90, Vodh Foghath 65 okay that is it. So typical energies they are given for the process which is 0.25 micron process is 2 into 10 2 or 4 into power 15 per centimeter square please remember we talk about doses is that clear deaths have decided about the energy. So we only talk of dose and dose is decided about the current collected at the integral I gt what we are is there were dose. So dose is what we are deciding and not the energies decide the depth dose decide the amount of impurities I can push inside okay. So I adjust my dose also there is a word which is important is this source drain also may get another contact on the top because it is silicon right now so I will put some metal on that for making a contact and it should form a good alloy between the two it is called silicidation okay. With poly what it is called if I make a contact with poly silicidation okay silicon we call silicidation polysilicon we call silicidation. So silicidation process is going to happen on source drains some metal will actually react with source drain. So it will eat up some silicon is that clear it will eat up some silicon which means your depth should be sufficient enough that this silicidation process does not take all of it so there is no hello there is nothing left there. So we have to be a little careful these are all design issues process design issues. Typical energy he says is 75 KV and this was what impurities will do arsenic Y and plus plus 10 to the power 21 I can go 4 into the power 20 is the highest solubility I can reach there of course in yes it is a name given poly salicides yeah but they say I am not saying this in this process itself the process there is a separate salicidation process for ROMs so some other day some other technology the word used there if you read somewhere it is essentially they are talking of polysilicides that is why I just said a number name to you it will still not because the solid solidity limit is coming at a temperature you are right but that is the limit up to which no material you get what is I would say it still remain crystalline. So if you have too much of a base time the damage which it will create will not be restored so essentially there is a limit which is close to solid solubility is that that is why you go to 1000 degree centigrade to anneal it so that it reaches maximum recovery as well as full dose. Use the opposite mask opposite resist whichever you think of right now do for boron doping for P plus which is again the same technique why boron and lower energy the range of boron is longer for same energy so you think of it that we we discussed earlier we have shown you that number have been used there 70 KV to 50 KV typically dose is something 10 to power 15 or 16 per centimeter square okay. So now I am made N plus P plus okay I am at channel stoppers I am at hallows I am at LED's okay I made everything what the transistor needs okay I have almost made my both N channel and P channel device so what should be the next thing I need I need to make something contacts to all regions so that I can externally create a circuit out of that okay after this implants which is normally high dose implant and particularly for arsenic the damage will be higher so what should be the anneal cycle at least should be higher temperature 30 minutes anneal are essential for recoveries and what is the advantage of recovery during that the impurities will also get substitutional so it is good to happen there okay. So there is a final anneal as the word says it is a high temperature driving activate the implanted dopants diffuses junctions to their final depths typically 30 minutes 900 or say 1 minute RTA RTA is rapid thermal anneal at 1000 degree is tried so that now I have a source drain I have hello of course not shown here hello plus LED plus gate is also dope during those regions okay so I am not transistors are ready okay now I need as I said the contacts I need a contact from the source contact from the drain contact from the gates okay I need contacts everywhere because unless I take out a contact out of it I cannot actually connect externally anywhere okay on the wafer. So this next thing is first thing is you whatever is the additional oxide here there you get what actually even not HF dip it is called buffered HF dip say it is 10 to 1 or 100 to 1 HF diluted and you actually give 1 second swab as it called dip it and take it it removes all the surface everything what is sticking around the idea is not to disturb any of the other oxides okay side walls nothing should change so it actually whole rock is dipped into but and taken away for not by hand by machine it just goes in and goes up okay and then water is immediately poured on it then dried and everything else okay so this is essential we are now ready for this process which I finished now maybe little more first contact of course will do is called front end process what is it called till the first contact we are not finished that but till the first contact is made for source drain the process is called front end processing okay that means for any circuit irrespective whatever circuit you are looking for this process will be constant except everywhere but that is decided so I have made transistors have given W by else I have brought first contact to source drain and everywhere and now what is the next thing you have to do is to create interconnects between number of such transistors the way you want circuit to perform is that clear you want to make a flip flop you connect some other way you want to make add or you mark some other way you use but this transistors are available to you with their basic connections out for any connection possibility is that clear to you so this is means why it was called front end because front end processes are constant for a given technology node this will be a constant process okay no changes but back end which is the one which starts back end means the interconnect parts ahead is the decision of a circuit man okay circuit people are telling what you want so that is called back end processing okay so the first contact now I have to do it it is titanium silicide contact to source and drain and titanium nitride as a barrier creation of course there are earlier we used to make even aluminium okay as the first contact itself aluminium has all good things in fact I mean people always say why suddenly you went for titanium two reasons we went to titanium aluminium has a problem of when they are very thin the electro migrate very fast some other day will discuss this so since it is a very strong electro migrating material also it oxidizes very it is good because actually that is how you are all blills everything are anodized means passivated that means it becomes alumina so it is so strongly oxygen affinity for aluminium and aluminium oxide is an insulator that correct so we do not want insulator to be contact okay so we wanted metallic contact so aluminium is not so strong contender earlier we have a thicker aluminium so we are no problem now then everything was reducing this aluminium has a pinhole problem aluminium has a oxidation problem then we said okay give it up so aluminium was declared person a non-greater and copper was replacing aluminium okay aluminium has a good thermal conductivity and it has a good electrical conduct that is the two things we are looking for good thermal conductivity and good electrical conductivity aluminium has all of it okay so we deposited titanium deposition what please take it the scope liner I mean it always forms the contours I said just now copper is replacing aluminium's wherever there we are copper interconnects copper has disadvantage copper has gives a second two levels in silicon which are traps so it may kill your mobilities so we must protect copper from silicon so at least first interconnect cannot be copper is that clear it has to have something else second third ten you can go for copper copper also has a problem it has a very strong diffusivity in oxide so one has to put some kind of a clad clad means some kind of a jacket wherever copper goes you have seen a wire it is always inside a copper wire it oxidizes also very fast so it needs a jacketing so additional process this process was found by many companies and everyone claim patents it is called damson process maybe we should discuss later copper cladding with copper interconnects there is where that vanadium oxide was worked as a clad clad okay so I deposited titanium everywhere okay then this process of deposition generally is by process called sputtering okay the process which we will discuss is sputtering okay is also in one way of deposition metal films one of course is elect evaporation the other is sputtering after this titanium has been deposited we actually allow it to react with nitrogen ambient to form a titanium nitride layer on the top okay wherever this please remember formation here some silicon is consumed source drain junction should be deep enough this word is I am keep saying why source drain junctions are very important that deep how much deep you want that some silicon will go away and that is why I wrote again for this that source drain depths are very crucial in present technologies well little less there is no source little more it lost the conducted issues okay so you have a issue which is very difficult to and that you people learn by experience source drain junction should be deep enough to allow titanium silicide is a good conductor which gives low contact resistance with source and drain that is why titanium are used in fact it actually form titanium silicide and it is a alloy okay it is alloy and that can be done by using one on the top of this I actually pass nitrogen and create titanium nitride on that titanium titanium nitride is also a good conductor luckily it is a great thing that titanium nitride is also actually is better than titanium silicide as a conductor running conductor okay we are creating a titanium silicide everywhere uniform is difficult okay alloying can be only restricted areas but nitride can run anywhere okay so this so-called water pink color or orange color is titanium nitride okay and this process normally is not furnace anneals generally it is RTA because one minute everything can be achieved okay temperatures are 600 to 700 please remember in VLSR this is thing has happening all processes should be now lower and lower temperature because whatever earlier you have done that should not get disturbed with this additional temperatures so next processing if implant has been annealed 1000 or 900 no process next should happen for 900 because that DT product should not get added there is that clear so the next processing I had will always be lower temperature than the main implants process temperatures I will create a nitride having silicide and everything done we use the mask 11 to remove the nitride from the areas which you do not want I only want nitride to be connected to the source drains and maybe one of this and this contact may be internal to it which is not shown here this so-called orange one or nitride these are resist you etch out the nitride from everywhere people who always to know nitride agent is ammonia NH4OH plus H2O to H2O where do you use this agent in silicon cleaning do you remember I say HCl plus one is acidic cleaning other is basic this is the same process okay so we removed titanium nitride in this normal 1 is to 1 is to 5 agent and then we also remove please remember my worries are essentially that the spacer should not retain nitride so that is where the whole game was that that is why chemical agent was used because I want from everywhere nitride to go except the regions where I actually looking for interconnects is that point clear why the weight etching is done here and not ionic etching dry etching was not right because I want nitride to go from everywhere else is that clear to you because it is an interconnect and it is not a contact to source drains is that correct it is an interconnect running you have a titanium nitride silicides as the contacts but outside to that I am running nitride layer titanium nitride this has to be understood and therefore you need a mask so that titanium nitride is removed from all places except interconnect regions that is why this is a important step you can see from here everywhere we removed titanium night otherwise it if it is a coplanar it will also go everywhere and if you protect it will also remain there so I want to remove from every other place then if I want a multi-level metal and now this is what I say front end is old first metal has come front end then now what we start is back end starts we also do a conformal layer of oxide now again I deposit silicon dioxide okay typically around a micron this blue one which goes everywhere conformal means it sees the contours okay it is a LPCVD process normally either the phosphosilicate glass or borosilicate glass were tried but of late people are trying what is called as borophosphosilicate glass which has both boroglass as well as phosphogloss the advantage people figured out is the following phosphorous has a tendency to actually tag on to sodium phosphosilicate glass will tag to sodium it will not allow sodium move where boron actually will allow because you know you have a glass which is there and you want to planarize later so I want glass to be little liquefied I won't say liquefied it is called reflow so it's slightly more molten state borosilicate has a lower temperature reflow compared to phospho so if I add a borosilicate when I actually want to planarize I have reflow at lower temperature so I use borosilicate along with phosphosilicate it's a mixture so it's also given a name borophosphosilicate glasses so once I do this which is the blue color this the first thing I do is to use a process which we discussed last time is called chemical mechanical polishing CMP this was not in our times now this is very common process the wafers let's say this is your wafer surface the polish is done like this on the chuck which has a slurry silica sorry which is normally has and some higher pH means what acidic or basic basic higher pH means basic so slurry is slightly base more basic than should not be acidic but acidic will attack everything so pH should be higher enough so you keep maintaining some ammonia ammonium hydroxide solutions round and there is a constant dip pH monitor is going on you keep adding automatically so using this the way wafers are mounted on a chuck and actually polish mechanically not by hand by machine and that essentially removes the top layers the earlier versions please just a minute we have a non-planar surface is that clear now please remember we have gone through so many process steps everywhere steps are different heights okay so we are now to make at least the top of the wafer one plane like this this is called by using a CMP process I can planarize is that okay this planarization is a crucial process step now so far how many mask 11 now here is a 12th mask I want to make contacts to this titanium nitride so I must protect all other even on titanium nitride oxide I mean titanium silicide I want contact to gate I want contact to source I want contact to drain so I must open all those region where the up second metal should actually come and make contact to that these are called either called holes or call vias VIA what is there called we are so I must create vias however in what material I should keep vias only in resist is good enough so first I will actually resist and I create VIA and an H out all other oxides from region where contact is to be made is that clear I removed from the gate I removed from nitride I removed of course here I did not show maybe backside and maybe here where I want the contact to the next layer I must open a window connection to that what is H in mask oxide please remember masking is always done in oxide okay so this this will delineate what the contact regions okay this will now this depth of vias what we are creating is also a crucial how much thick oxide should be if it is too thin the capacitance is very high see ox is lower if it is too thick the VIA deep depth is too high and then next process make clear problem so depth of VIA is decided by how much CMP I do and what I retain as my actual oxide thickness is that point clear to think a thickness of resist I mean for oxide I keep VIA are too deep and the next metal may not go properly if it is too thin there between two layers if the oxide is too thin they will interconnect okay they will connect itself by capacitance at high frequency 1 upon j omega C so my worries are how much so this circuit people will say this is the frequency they will operate so I will accordingly adjust my oxide thickness okay so the next process step I then after the contact is done I actually have another titanium nitride as the next layer of contact okay please remember before the this pinkish layer is actually tungsten please please just just listen this pink layer is a tungsten but below that there is a thin layer of titanium nitride which I deposited which is not so much visible because it was below that of course in this region you can see but even everywhere we will find one thin layer of titanium nitride which over which the tungsten is going to sit the titanium nitride has some interesting features it is a layer typically 100 Armstrong's are what we do and it acts like a barrier firstly it has a excellent adhesion with silicon dioxide titanium nitride makes a good adhesion okay so that is what we are looking for the other is it is a barrier between tungsten and the lower material lower regions okay it should act between the two buffer okay so titanium nitride is a buffer between tungsten and any other metal okay so everywhere wherever I will run tungsten below that there will be a thin layer of titanium nitride and that will be typically 100 Armstrong's okay how to deposit tungsten tungsten fluoride hexafluoride treated with hydrogen at around 450 degree centigrade can reduce it to tungsten NHF now this tungsten then I remove this tungsten please remember this is also conformal because it was deposited this is a CVD so what do I do is I go through another CMP process how much as the thickness of tungsten was so if I remove this top portion of tungsten I get only tungsten just on the contact points where do you want these are called tungsten plugs what are they called plugs so we create tungsten plugs where do you create tungsten plug wherever contact you want above for the second metal you must create between the lower metal and the upper metal the connectivity is through tungsten and this W by L of this tungsten via is decided by the contact resistance and the net resistance you can tolerate okay so once I etch out the or rather I remove the tungsten from the top surface I have another planar available and why this is always possible CMP allows me to grind things so that I should know up to where I have to grind so I finish that process so I get this process which these people are talking this first titanium silicide is not called first interconnect the first interconnect is now going to come okay here they are shown aluminum but could be copper I did not want to show copper because there is another process I have to show which I will show later so this is essentially first metal is aluminum how many metal layers you may expect as large as 7 okay and maybe someday 10 why do you need so many interconnects because if there are one billion transistor on chip for one single circuit how many are particularly if it is a DSP based some kind of a circuit there is only interconnects there are no great circuit devices it is only here to there data going from here here to here here some filter some adder some it keeps doing running around L L H H L L H filtering is going on and so interconnects are extremely heavy now because of such things and we know two metals certainly will not like to do like this if one metal is going here so it should be at least thick enough oxide and I run something on this I will say okay do not run this everywhere do not run in between I run so if I decide that I will not run over everywhere as much as possible I will require much more space to run the interconnects the at least what I will do is one should not interact with three three should not interact with six or five then next nearest neighbor it should not interact the bill it goes about it is okay to thickness of oxide and it saved by you but at least the nearest neighbor on the top or bottom should not get connected so run metal layer should not run one over the other as much as possible and this needs number of metal layers okay so that we avoid connection going from crossing one over okay okay so this is a and since I did is aluminum not because I wanted it but this is what plumbers book has so I thought I will show you but nowadays aluminum will be replaced by copper but the only problem then is as I say aluminum does not require any cladding I may have to create vanadium some kind of a cloud around in which copper should sit okay so there is another game going on okay maybe I will show you damn synthesis so I deposit metal and what do I do wherever that interconnect I want to retain okay I put photoresist H aluminum from elsewhere so which resist I should let us I am using PPR what kind of mass it should I repeat I want to retain aluminum certain regions but I want aluminum be removed from all other regions I am using PPR okay clear field mass why clear because wherever light will go photoresist will be softened out so aluminum will be easy to H out there because there will not be resist there the rest area where I am protecting the PPR light should not go and therefore it should be so that is I repeat the mask is decided or resist is decided generally companies prefer one mask type or one resist type they do not keep changing resist and mask generally not necessary so which which is this number mass for aluminum 13th mass has been used to do first metal first metal if I want the second metal what should I do again I should deposit oxide again put no if you need plugs you put plugs also then the polish it and then again put the second metal layer create wear on a create masks 14th mask on that H of the 14th layer so here is one second metal is another oxide and you can see another plug has been created wherever I will go from one metal to the lower metal that tungsten plug has to be create and tungsten plug can only be created by which it must have titanium nitride blade before so that the same processing is done first I deposit nitride and I deposit in the same CVD actually I do it it is called co-co-CVDs so it is not actually CVDs a molecular beam epitaxy some other word I can do one after the other if I am doing LP CVD I have two reactors I will have to do twice this is second metal if I want third what do I do this put another oxide put create vias titanium nitride tungsten put new metal put another keep doing as many metal layers as you wish to okay so for example he said another two of them may be final the last after number of metals are over there is the last mask is used okay this is called the generally the layer on the top which is shown here for example is silicon nitride okay this is very important two things silicon nitride is a relatively hard material what does that mean so doing handling it does not get scratched down any silicon area it will actually protect the silicon wafer so nitride the second part of nitride is this is excellent passivating material it does not allow any sodium potassium or any other species or even water molecules to get inside it is not hygroscopic so because of that the last layer of the chip is nitride but you need now another mask for what final contacts will go on the chip I mean this package so you need pad patterns to be open and open where nitride is used only at the pad patterns and nowhere else pad is the last mask so your pad pattern which is now open in nitride and that is actually put it into the packaging and therefore either wire bonded or by bumps bonding flip chip and I can make final packaging of the chip so last mask irrespective whatever number of mask you did earlier should be a passivation mask and normally it is and it should be very thin and very good nitride so it is plasma enhanced CVD one of the CVD process which use is plasma enhanced CVD is that point clear to you so how many masks I did 16 for the sake of two metals we are five more metals of five minimum will go there why five you may need more for the plugs so you think of it anything your additional mask for everything you go ahead of that correct so don't think that why not 20 mares 20 I think you must remember at no time the top most metal or the metal should go more than one layer down connection is that clear this connectivity is clear I cannot connect seventh layer to one at any time directly so don't create a view of seven layers there is no possibility of anything going through this so what we'll do is from 7 to 6 6 to 5 5 to 4 43 so keep shifting so the area is constantly varying because of where do you want which connection so when you lay out a circuit you must plan very well that you don't need 7 to 1 connection any time is that clear so the designers when they create a layout also should think what is the technology available and how many minimum connectivity is to be given so it is not process person job it is the designer's job to give me a mask which will allow me less number of interlayer connectivity but that means top to bottom I should not be asked to connect is that clear I am not saying I cannot do it by like this exact I will but that's not the best way of connectivity so try your designs in a way somewhere you use interconnectivity of poly somewhere you use only local tight end and night I didn't commit so don't run everywhere from every other place to every other place this is something designer has to plan which layer I want next so when you lay out you must see colors there I think I hope they are here already come on layout has he has he shown some layers to you you must have seen poly red this essentially those colors are masks for me each color is a mask for me okay so at that time you should plan which connection when okay therefore that is the layout that is the mass I'll receive that's the mass I'll print okay is that clear so designers job doesn't end only on circuit simulation okay which many people believe it's the layout which is the most most limiting the success of the chip design so layout should be very good error free good density with no reality issues in that all that and then you expect my technology to deliver what you are actually expecting which I may not promise in one but I may go second time in one run these are called turn around once you I run through a mass 16 mass and my chip did not work so the first time I'll go and verify there are test area this I'll test where I went am I is the mass problem or my problem okay most problem technology people will always say it's a mass problem my designers say your process has a problem these extra additional extensions are not mine all statements are made but finally you have to pay again but the second around and finally success has to come okay there are no designs in the world which has gone in first term first around there is always first turn one turn around is part of the game this will be required all designers design with a specifications and they keep saying you these are the technology people say these are the things which you must follow which are called design rules you cannot separate diffusion less than this put metal close to this every rule which I need I'll inform him so his layout will take care and now there is a auto design checker so it will not allow even to draw many a times you can force it there is a bypass you can overrule it but normally DRC doesn't allow then why fail because this fail is something which humanly not possible what designers tell the process people technology has said rules design rules what technology people receive from data from designers this you must give me what is that he is asking technology has told no you can't do this you can't do this you can't do this so I had a layout person I said okay I have taken care but what is something a designer keeps telling this man this you must promise what is that he actually tells you the propagation time from source to read he actually specifies why preparation time because L by V is time but we is me so essentially telling this much minimum mobility I am expecting at the surface from because all my analysis was based on some you is that clear so that designers tell only one thing the propagation time for an electron to go from source to drain he said I want a propagation time of 10 picoseconds that's the only data he forces on you so the process should hold to that number any day at all transistors is that clear so please don't think that designers don't have designers are very stringent force they say if you even if 1% or 5% error you go how much error I will have he has to calculate so he has to always worry about speeds and then he will only tell what they called as propagation time so don't think only one-sided this there is a other side people keep telling that your device processing is not good enough to get this much mobility is and I want for both P channel and N channel this much okay and then only I can assure you my circuit will perform is that point clear to you so don't any time feel that things are very trivial any small of course we are few of my PhD student work on reliability issues and we did figure out most processes will show you 10% variations now either your designer should take care of 10% variations or at least you should say some of the processes may actually damage you more than the others so either there are techniques statistical techniques so you'll have to do now statistical designs rather than what we called as fixed designs so you must take care of variations and these variations vary from technology node to technology node to company to company this Monte Carlo method is not very good that's what our results was Monte Carlo says that you know number of variables as much you take let's say your 12 variables so the pseudo-random generation require 2 to the power 12 samples so if you process it for a circuit with some 100 million transistors some next year it will result come so you can use so we figured out that 2 to the power something instead of 2 to the into something if I do say 2 to the power q and 2 into q and q is large I will do much smaller simulations and will be only less than 0.01% away from Monte Carlo so that is our technique to show that analysis much faster for any large circuits or you may even assign which are the critical areas where circuit need not be worried too much slowest path so you anyway that is going to limit so why are you forcing VT everywhere only this area is limiting you so first circuit person should talk with device and then to process and each should translate where what then you can make a better so it is called statistical designs so nowadays most of the designs are statistical okay so this finishes 16 mask standard CMOS tomorrow in Wednesday we will start with a 3 processes or rather 2 processes which which we talked which we haven't done one we said depositions and in depositions also we said few different kinds sometimes are deposited metal sometimes are deposited insulators okay so I need to have a CVD chemical vapor deposition which can either deposit metals or this and then I will are etching I etch everywhere so I need to know etching so 2 processes so tomorrow we start with CVD