 Welcome to this presentation of the STM32L5 clock recovery system. It covers the main features of this module used to control the precision of the USB clock frequency. The goal of the clock recovery system is to obtain a precise enough clock signal for use by the USB module without the need for an external resonator component, just by simply using the USB traffic as a timing reference. The peripheral's main functions are its ability to trim the internal oscillator on the fly to benefit from its fine granularity in order to meet the USB protocol requirements and have enough information available for the user to track in early phases any potential issues. The key features are a selectable synchronization source with programmable pre-scaler and polarity. External pin, LSE oscillator output, or USB SOF packet reception. The possibility to generate synchronization pulses by software. An automatic oscillator trimming capability with no need for CPU action. A manual control option for faster startup convergence. A 16-bit frequency error counter with automatic error value capture and reload. A programmable limit for automatic frequency error value evaluation and status reporting. Maskable interrupts and events. Expected synchronization or eSync, synchronization OK or sync OK. Synchronization warning or sync worn. Or synchronization or trimming error or ERR. Four different sources can be selected for the clock recovery system. An external signal on a GPIO, the 32 kHz crystal, or the USB startup frame signal can be used as a clock source to create a reference signal to calibrate the HSI 48 MHz oscillator. This reference signal called sync is used to reload the 16-bit counter and capture the value of the actual countdown. Depending on this value, the HSI 48 MHz clock frequency, or HSI 48, is fine-tuned to reach the most accurate frequency. The CRS counter value is reloaded with the reload value on each sync event. It starts counting down till it reaches zero. Then it starts counting up to the outrange limit where it eventually stops if no sync event is received before and generates a sync miss event. A sync event received when the counter is below the outrange will eventually find trim, the HSI 48, depending on the philim 7-0 value. If the CRS counter value is below the philim limit, no trim actions are taken. If it is between three times philim and philim, the trim bit is incremented or decremented by one. Depending on the counter direction. If the CRS counter is between 128 times philim and 3 times philim, the trim bit field is incremented or decremented by two trim steps. The following interrupts can be activated by the clock recovery system. The expected synchronization is set when the counter reaches zero and starts counting up. The synchronization OK is set when the sync event has been received within the expected time window. The synchronization warning is set when the sync event has been received within the margins of the OK window, but not yet in the error range. The synchronization or trimming error or trim OVF, sync miss or sync error is set when the sync event has been received too early, not received at all, or if the trim bit field overflows after an update. You can refer to peripheral training slides related to the USB and RCC modules for additional information.