 So, welcome to this lecture on field programmable gate arrays and the course design with digital system design with PLDs and FPGAs. The last lecture we have looked at the architecture of complex PLD essentially we have looked at the logic block, the interconnect switched architecture. In the logic block we have looked at the product MRA, product M allocator, the macro cell consists of flip flops with certain configurable options and we have looked at a given a VHDL code how it is synthesized and kind of place and fitted that synthesized circuit within the CPLD ok. And we also have seen the timing model of it and the IO block and various applications and some kind of features of CPLDs and today we are going to look at much more popular class of devices called field programmable gate arrays and before that we just look at the previous lecture slide so that we can contrast the FPGAs of field programmable gate arrays with the CPLDs complex programmable logic devices. I mean why the FPGAs are much more popular, much more used than CPLD we will be able to understand if you briefly look at it the CPLD part and go to the FPGAs. So let us turn to the slides of the last lecture so we had looked at the Mac 7000 PLD which is from Maltera as an example and we said the CPLDs are kind of hierarchical PLD which consists of simple PLD blocks which is interconnected to a switch. So these are 16 macro cells that means kind of a hand over with the flip programmable flip flops such 16 outputs and you know here it is shown 4 blocks and there is an interconnection and the AND gates input goes from the output of this huge switch like you can see 36 line goes there so you can imagine 36 vertical lines and its complement and there are 16 output that means 16 flip flop sections are there that can be connected to the 16 IO blocks or it can be fed back into the switch as input okay. So also you have IO blocks those pins can act as input as well as output so input pins can come as input to the switch so all these you know that the output fed back or the inputs of 4 section come as the input and output of the switch goes as a input to the AND gates input okay. So essentially if you take 4 you know 4 kind of blocks like this 4 macro cell section or 4 logic array block then what we have as a switch size is you know see here 32 x 4 that is you know 128 inputs and 36 x you know 144 output okay so it is a huge switch and that is one disadvantage of the PLD so you cannot stretch it to a large you know very large kind of device where lot of macro blocks are there or macro cells are there and we also have seen there are clocks which is going to the flip flops if it is not going there you can use it as input similarly output enabled to the enable the tri-state gate you know dedicated output enabled or if it is not being used it can be used as input. So we have seen that this is a cross bar and cross bar is nothing but a 2 by 2 cross bar will have 2, 2 to 1 multiplexer to choose any of the input for 2 outputs so you can imagine n into n requires n into 1 multiplexer so it is very huge in area and it cannot scale very much and that is one issue which the field programmable gate array solves okay. And we had a look at okay this is that switch shown for clarity we have seen that the fed back thing as coming as input and the input itself is the IOP input is coming as input to the AND gate and the outputs are going to the logic block as input to the AND gate okay. And these are the this was a kind of architecture we have in this max 7005 AND gates which can be connected to OR gate, XOR gate as a product term clock, clock enable or the you know asynchronous reset and so on okay and one of the AND gate is fed back into the array. So there are 16 sections, 16 AND gates as expander terms which can be used to cascade okay and if one section AND gate is not used that can be used by the next section and so on okay. And once again the problem remains here these AND gates are very wide there are lot of inputs you know there are 36 variables and its complement can be connected to AND gate which is very rarely needed in you know real life cases. So such a structure will you know make you know this 36 signal even make the switches the programmable interconnect array or the cross bar very big which does not make it scalable. So these two things are the one which is sorted out in the FPGAs where and you do not have such very wide product terms and you do not have a huge single cross bar you know instead of having a central switch which is distributed you know across the device okay we will see the architecture so that it can scale well. So if you look at this particular CPLE you can see the maximum number of the logic blocks in this device offers is 16 but if you stretch it more than that then the huge area will be occupied by this cross bar and so on. So that is addressed in FPGA and we have seen the flip flop as across you know recirculating MUX built in so if you can use one kind of clock enable one level of clock enable for controlling the registers. And this we have looked at it and we said some devices allows a direct connection from the IO pin directly to the flip flop which can be used for synchronization. We have seen the metastability then when there are multiple clock domain one would like to synchronize the input signal so this can be used for fast synchronization otherwise it has to come through the cross bar come in here go through all the way for synchronizing which will make the setup time very huge okay. And many signals may not satisfy that setup time so that is avoided by this particular fast input which is shown in the picture like this you know this Mach 7000s. And we have seen an example of a VHDL code how it is synthesized and how it is really mapped into the Mach 7000 CPLD. And this shows the product allocator of an XC9500 we can see that how a single AND gate is connected to OR or XOR or either the clock or reset and so on. And this shows the product term steering part if it is not used it can be used by the top or bottom macro cell or this can be combined with the previous one and can be used and so on okay. So a lot of possibilities there and this shows IO configuration you have a tri-state gate enable which can be permanently enabled disabled or you can use various signal from the cross bar to choose to enable that okay. So that add to the flexibility and we have seen the timing model which is very simple because between any logic blocks there is only one cross bar connection and this all are specific to the macro cell okay. So the timing analysis is simple and the end to end timing is it is quite fast compared to probably an FPGA but this device since it is not very popularly used it may not be fabricated in the latest device technology to that extent it may be slow like if you have a 22 nanometer technology the latest CPLD latest FPGA will be built on that but the CPLD may not be built on that because the volume sale may not be that high so that is why it is not built on that. So we have seen the features of that basically and or very wide and or number of registers are small timing is simple architecture variation is small the programming technology is flash and the capacity is around 10k. So what we are going to the FPGA what FPGA addresses is this wide decoding is removed a complex cross bar connection is distributed and one more thing is that it basically gives you lot of registers okay. So in a CPLD register to logic ratio is very small that means there are huge AND gates number of AND gates are high but if you compare to the logic the amount of registers available in a CPLD is less. So you cannot think of implementing some kind of memory structures C4s and RAMs and all that in a CPLD but in an FPGA. So we have seen some application where lot of FSM counters random logic is needed the CPLD can be used but otherwise it is tough to use lacks of the memory affects these kind of application like communication, signal processing, cryptography and all is affected by those kind of you know lack of resources. But maybe simple cryptographic circuits can be implemented in CPLD it depends how much what kind of algorithm you are implementing and how much is the key width and so on okay. So basically it depends on that but then I am sure some small cryptographic circuits can be implemented in CPLD. So let us come back to our topic of today's lecture it is field programmable gate array. So as I said what it address is the three lacunae or three features in the CPLD. The CPLD we have seen there is a crossbar which is very huge which is a central resource which cannot be scaled. So in FPGA this particular point is attacked and the interconnection architecture is distributed across the chip. So that chip can scale well you know if you look at the number of logic cell in a FPGA it will run into millions in the case of complex FPGA which allows you allows the designer to even emulate the A6 in FPGA. Sometimes the complex SOCs require multiple FPGAs to emulate or to implement but nevertheless this distributed interconnection architecture is the one which enables the FPGA to become complex in terms of the logic resources and memory resources okay. And the second thing it attacks is that we have seen that in CPLD there are the product terms which is very wide which is not required in practice or in real life. So in FPGA you have the logic resources or the combinational logic with smaller inputs so that the area is not wasted okay the resources are not wasted. The third thing the CPLD suffers from is a lack of registers which is addressed very much in FPGA. In fact the FPGA balances the combinational logic with flip-flop. So each logic block will have a kind of balance between the combinational logic and flip-flop okay. We look back in CPLD maybe there are 5 product terms very wide product terms and one flip-flop but here you will have a much smaller logic in terms of the inputs okay there it was kind of 36 input but in an FPGA it may be 4 input or 5 input or 6 input 7, 8 like that. Now I can say with all the combination and all the variation it start with number 4 and in a big logic block up to the 8 inputs that is what is the FPGA targets and there are a lot of flip-flops okay and many a times these logic combination logic is combined. You start with a 4 input combinational circuit then you combine multiple of them to make 5, 6, 7 and so on okay. So you get lot of flip-flops because if you go for if you combine them still you have the flip-flops corresponding to that logic resources left out. So there are a lot of flip-flops available in FPGA so the registered logic ratio is very high in FPGA which allows you to implement lot of communication or computer networks functions and signal processing blocks and so on okay. So let us go to the slides of this field programmable gate RA that is our almost we are coming to the end of the course. So let us see this so we are going to in a the topics we are going to cover in kind of from a very broader perspective is that we will look at the FPGA architecture of silings mainly I will concentrate on the silings architecture and I will just show some altera very briefly altera and the actel to contrast and we will discuss FPGA related design issues, FPGA related timing issues, the tool flow how to configure FPGA little bit about system on programmable chip or programmable SOC whatever various device vendors call it. So you can call it PSOC which is a programmable system on chip that means the complete system like SOC is built on an FPGA fabric how to debug the FPGA design some case studies and so on okay. So that is the topic the case study is definitely need not be very much linked to the FPGA yes it is linked to the FPGA in the sense that we are going to implement that in FPGA but this will kind of wind up you know put everything together we have learnt till now the VHDL the digital advanced digital design the FPGAs CPLD and all that will be tied together in the case study we are going to handle. So at the beginning of the course we have discussed the evolution of this devices okay we have discussed the evolution of this the PLDs in greater detail but since we have discussed this at the beginning of the course I will just briefly mention that ASIC is something which is built from the scratch okay. The designers might use some kind of standard libraries to implement this the ASIC libraries but more or less it is a huge kind of time it takes and huge cost which is called non recurring engineering cost that means there is a one time design cost lot of area tools are required lot of designers time is required and one need to set up a foundry line to fabricate this. So all that is a one time cost which has to be amortized once the ASIC you know yield goes up because it is an electrochemical process and at the beginning number of good devices out of 100 will be maybe only 80% then as the process is tuned you get 95, 98, 99 then you know it makes sense to make an ASIC. So the trouble with ASIC is that since more or less it is implemented from scratch designed from scratch this cost the NRI cost will make it viable only for huge volumes and it takes a 1, 1.5 years from starting to end for a reasonable complexity ASIC to come to the production okay. So this is one feature of the ASIC so there is a middle ground where these the cells used are fixed by the foundry and they will give you libraries and you pick up the libraries and interconnect them. So only the interconnection is the unknown factor because these the mask everything for the standard architectures, standard blocks are available with the foundry what designer once end of the design what goes is basically the interconnection of these standard blocks okay. It is quicker but the NRI cost is kind of medium not as high as ASIC. So this will work for the medium volume maybe in a lesser time you can design because you are working with standard block and the performance will suffer because it may not be very much optimized at a complete system level. So there are design called mask programmable gate array but this means there are array of logic resources wherein you know it is interconnection is programmed at the foundry. So we can say so this works for medium volume and we can say the field programmable gate array is a field programmable version of the foundry version of this gate array. This mask programmable gate array or standard cell it is interconnection is kind of fabricated in the foundry but here the interconnection is configured in the field okay in a lab or in your workplace. So it is called field programmable gate array okay now when you say field it is not the electric field it means the field you are working okay the lab or something like that okay if somebody is confused with that particular word okay. Definitely it uses devices where transistors where the field is kind of somehow involved in the programming but that is not the name you know meant for basically so that is field programmable gate array. So it involves then the array of some logic resources the interconnection with programmability which can be programmed in the field okay. So that is what is FPGA is about basically it is an array or a matrix of logic resources with programmable interconnection okay. So you have array of them okay not like in a CPLD you cannot say array because it is the width is very less you know you have 2 by 2 or like 2 in the width and 4 in the depth and so on or 4 column wise the 2 row wise and so on. But here it is a huge array of logic resources with programmable interconnection and if you look at the logic resources we know that we have to ultimately do some computation using data path which consist of combinational circuit and flip flops and the data path we are controlling by the finite state machine which also require combinational circuit for next state logic output logic and all that and the flip flops the state flip flops. So we can say the logic resources in any reasonable design involves combinational circuit and flip flop be it data path or the state machine or controllers. So that is provided in the logic resources of FPGA in particular if you look at the combinational circuit or the normal combinational lookup table the maximum use this the lookup table. We will see what is lookup table we have discussed in a way in the case of CPLD in the evolution of CPLD but we will have a you know kind of review on that. Some FPGAs use multiplexers as a combinational logic and you know that a 2 to 1 multiplexer if the select line is connected to A then you have A bar and A is available or if you have a 4 to 1 multiplexer you have 2 select line to the select line you can connect AB and depending on the inputs you get the output or of the output. So a multiplexer is nothing but AND or so you form the minterm of the select lines variables the minterms of that and the programmable OR is achieved by connecting the various inputs as 0s or 1 wherever there is 1 that minterm is a part of the output you know output variable that is the multiplexer of course there are some FPGAs which use gates for implementing the combinational logic. So that is about the combinational logic and if you look at the programmable interconnection these are the technologies used SRAMs that is static RAM and it is a bit of an unfortunate name though at a kind of top level the name is correct but it might kind of mislead you in terms of the technology used for interconnection the flash transistor and something called anti fuse okay or you can for the Americans is anti fuse okay. So here the anti fuse is a kind of opposite of a fuse you know that the fuse you normally pass a current to blow it but the anti fuse is something which does not have a connection by applying a voltage you make a connection okay so that is called anti fuse. And FPGAs as special resources like PLL which is phase lock loop, DLL delay lock loop which is not used nowadays mainly all the FPGAs use PLL phase lock loop which has advantage over DLL maybe we will briefly look at it though there is no particular reason because the current FPGAs use PLL then the memories, RAMs, the FIFOs the same RAM can be used as FIFOs with additional logic memory controllers sometime high end FPGAs need since it has lot of computational you know possibilities or option of implementing complex computation it needs lot of memory and the DRAMs are used DDR3 can be interface and in that case a DDR3 controller implemented in FPG resource may be slow. So there are hard kind of controllers in the fabric network interfaces like the kind of physical interface or the data link of the ethernet and so on okay or at least the blocks used in the prominent network interfaces. Sometimes the complex FPGAs has hard core processors built in so that you can implement a complete SOC solution within an FPGA okay. So that is a kind of nutshell introduction to the FPGA it is evolution what it contains it is a it has evolved from ASIC standard cell or MPGA and FPGA it consists of array of logic resources with interconnect programmable interconnections. The logic resources basically is combination circuit and flip-flops and the combination circuit used in FPGA varies from static RAM sorry the lookup table then the multiplexes and gate. The programmable interconnection mainly uses SRAM technology flash transistors and the fuse technology and there are special resources like PLL, memories, network interfaces, memory controllers and so on okay. So that is the FPGA in a nutshell. So let us look at the slide. So if you look at the commercial FPGAs these are the two major manufacturers who has a market who shares the majority of the market the silings and Altera. Silings has a low cost devices called Spartan series currently they have Spartan 3 and Spartan 6 though it is low cost these are kind of still a lot can be implemented in a Spartan 6 you know complete if you want a complete SOC can be built in medium complexity SOC can be built in Spartan 6 it is low cost but it that does not mean it is low complexity or low performance it may lack some inbuilt processors and hard core certain devices but these are still powerful and they have the complex FPGA the previous generation was called vertex 4, 5 and 6 and the current generation as Arctic's, Kindex and vertex kind of all share kind of similar architecture but they have certain additional resources which is for you know which is suited for either you know the IO requirement or signal processing and so on okay. The silings also have a new devices called zinc which is nothing but a fabric like vertex 7 plus dual core ARM processors are built in okay that is not built into the fabric of FPGA it is in the same silicon chip so it is a hard ARM processor which can clock at very high speed so a complete software hardware solution high performance software hardware solution can be implemented in FPGA. When it comes to Altaira they have the Cyclone kind of low cost devices again that does not mean it is you know kind of low performance or low complexity they have Aria series and Stratix series which is you know which is the complex version of these kind of devices. So and they have a soft core processors called Nios can be implemented in these devices and the silings has a soft core like micro blaze soft core means the design is available in terms of the verilog of VHDL code they have something called pico blaze which is a micro controller 8 bit and the micro blaze is a soft core RISC 32 bit processor. Similarly Altaira has Nios 2 32 bit RISC soft core processor Actel has different all these are the static RAM based FPGAs and when it comes to Actel another manufacturer who has devices like Accelerator and RTAX and all that which is antifuse based and there are flash based ProASIC and there is you know smart fusion with ARM Cortex M3 you know built in hard core with this Actel. So Actel has a certain line of antifuse FPGAs which are quite useful in the space application because it is a kind of a non volatile technology is a one time programmable. These devices if it is SRAM technologies are kind of even if it is radiation hardened programmed and sent into the space because of radiation these memories can get the RAM program like configuration memory can get corrupted but not in the case of this radiation hardened antifuse because it is permanently fused. But it has a great disadvantage saying that it is only one time programmable once you program it it cannot be erased and reused. So it is not very good for prototyping like you can simulate but then you want to test the system during the development not a good idea to use antifuse technologies maybe it has to be tried in static RAM kind of FPGA then once it is matured can be transferred to the antifuse kind of technology. So essentially in a nutshell this may not be a very accurate picture but at least the previous generation of the FPGAs had this kind of architecture. The current ones I cannot say that it is exactly this but then it is a good starting point and it is quite correct you know but there are additional details you know in a current FPGA. So let us look at the structure of an FPGA. So basically you have IO pins around of course there are VCC the ground pins and all that plenty of them for the inner core and IO pins. So normally the core works at a low voltage and the IO pin works at much higher voltage. So this may be under one voltage but then when it comes to the IO pin it may be 2.5 or 3.3 volt devices depending on the technology. Otherwise there are a lot of IO pins around and you can see that there are logic blocks array of them okay here it is only shown 4 by 4 but in real life it can be my say huge number 32 by 32 or 1 to 8 by 1 to 8 and so on even higher sometime. And these are kind of wires all around. So you can see that this may be multiple number of wires which is connected in a switch here. Again the wires all the wires are connected in a switch here and this the bottom and the left are the input to the logic block. And so that means there is a switch here a switch here and this the top and the right hand side is output. So in principle how the design is done in an FPGA is that the synthesized logic is placed across multiple blocks depending on some kind of constraints. And say an IO pin can be connected to the input of a logic block and that output can come here maybe it can be taken to the input of this logic block as well as you know come all the way and to this logic block and this output can be maybe taken to the input of this logic block and so on. So basically this structure allows you lot of possibility of connection and you can see that it is not a single switch like CPL. In the CPL there was there were logic blocks and there is huge switch. But here these are kind of simpler blocks very small logic and flip-flops and lot of them are there. And it is interconnected through a lot of wires and lot of switches which is distributed. So that you know it can be scaled you know big you know you can have a bigger much bigger device than CPLD. And so these maybe there are you know when you talk about switch here, switch here need not that you know all the wires from this switch run to this switch there could be wires running from the first switch to the third switch first switch to the fourth switch and all that. So there could be wires which is a kind of single length of the single block or we can say single length wires or double length wires or quad length or the wires running from one end of the device to the next end of the device. Otherwise these kind of wires different length wires are required because otherwise suppose there is a logic block here the output of which need to go to the input of the logic block at the end. And if you connect by single length wires it will incur lot of switches are required for interconnecting them which you know weighs the area of the switches and it will incur lot of delays for each switch there will be delay. And so end to end delay will be very large and the maximum frequency because we have seen in a data path the frequency achieved is tcq plus tcom plus tsetup and here the combination delay will include the combination delay includes all the wired delays the interconnection delays and in an FPGA if there are lot of switches use these interconnection delays will be more than the logic delay. So that is one issue with the FPGA there could be interconnection delays which is much larger than sometime more than the logic block it depends where the logic is placed within the chip maybe if you have some logic here and output is taken all the way to the right hand side of the FPGA which is very huge through lot of switches then it incurs a lot of delay. So that should be kept in mind the interconnect delay is one kind of disadvantage of this FPGA but that is at the cost of flexibility and cost of scalability of the device this distributed either interconnection is what allows it to grow in sizes but that add to the end to end delay when the circuits are placed and routed within FPGA okay. So this shows a little more detailed diagram so this shows the CLB you can see here and these are the switch blocks all around it at the corners and these are wires you can see that this shows that the 4 wires are kind of connecting this switch to here and you can see there are maybe 7 wires connecting horizontally single length wires and these are the input to the logic block and CLB means it means it is called configurable logic block okay that is one thing once again you should remember that not that the wires are programmable or configurable what logic within the logic block is also configurable. So there is not only programmability in terms of interconnection there is programmability within the logic block okay to make it very flexible. So when you say configure FPGA it means configuring all these connections as well as configuring the logic block okay that should be kept in mind. So it is a configurable logic block and you can see that that means that there are switches between this input wire and the output wire and so on okay. Similarly this shows an output of a logic block is coming to a switch here it essentially means you have either you can connect this output to this input this one this one or this one or maybe this side it does not matter you know you can connect it either way or sometimes it is a single line to which it is connected or there is a disconnect depending on you know the number of outputs and so on okay. So it depends on the vendor and vendor does you know analyze lot of applications which is mapped into this kind of fabric and from the statistics they have to make a judgment on how many wires to place and so on okay. So it is not that the number of wires and type of wires are fixed from device to device depending on the complexity there could be more wires or less wires and so on okay. So that should come from statistics normally this cannot be blindly put maybe they started analyzing the applications and put some wires in earlier generation now they keep statistics of the current applications and when they evolve to the next family of devices they kind of scale it appropriately these number of wires the type of wires and so on okay and if you look at the interconnection itself this is how it is interconnected the switches which is shown here. So you have vertical wires and horizontal wires so what is done is that between a vertical wire and a horizontal wire you have a transistor when the gate is made on it is interconnected okay and you can have a unidirectional connection or a bidirectional connection depending on your need maybe if the output is coming from this side and going to the input on the other side you need only a unidirectional but if there is some kind of data flow signal flow in both directions then you need a bidirectional switch and now if you look in principle if you have a 3x3 this can be connected not only to this it can be connected to this as well as this and you know maybe yes say each of this line can be connected to 3 but sometime providing all possible connection can make this very huge. So many a times is not that a single wire is connected to every other wire and so on okay particularly there may not be any connection between the vertical and vertical wire there is no need because we have seen the output is coming to all vertical lines. So normally the vertical lines are connected to the horizontal wires and but here when it comes to a switch box this part need to be connected to this vertical line to cut through okay. So that connection is required that is you can see that it is shown here. So there is a vertical connection here okay and a horizontal connection here. So there are various switch architectures you can see there is a disjoint connection and where in one each wire the vertical wire is connected to two vertical wire and one other vertical wire a slightly different method of connecting again slightly different method of connecting. So you have the choice you know need not be that this wires need to be connected to this horizontal wire maybe it can be connected to the some other wire. So in this case you can see that this the first wire is connected to the to the top most horizontal wire but here the first wire is kind of vertical wire is connected to the bottom most horizontal wire. So there are different architectures so depending on that is a little bit of a back end detail of the device. So as a designer we need not bother too much about it but as a device if you are in the FPGA design you are designing the FPGA device then one need to bother about it. So we are basically looking FPGA as a device to program our device design. So we need not I mean we need to understand but we need not go into the details of various interconnections and so on. So let us go to the next level. So this is a very old slide from the Siling's data sheet. So that but illustrates one thing in FPGA you would have seen we have discussed there are lot of combination circuit flip flop. So there will be lookup tables flip-flops interconnection wires switches and all. But then you know that these all these need to be configured like switches need to be kind of programmed on or off the logic block need to be configured and so on. So there are a lot of overhead configuration circuitry that means this configuration pattern need to be stored somewhere at the power on these switches need to be programmed and so on. So you should know that the FPGA is not just what the designer sees. The designer mainly see only the logic resources flip-flops and wires but there is an underlying configuration overhead logic and the circuit ok. So that makes the FPGA quite big these wires and the switches and the configuration overhead circuitry will make the FPGA much bigger it will be spread out. So you cannot expect at a row speed the speed like ASIC for FPGA. But there are in FPGA you can exploit that it is a programmable fabric and it is in the control of designer to put you know however many computational unit within FPGA maybe we will do very wide computation like we get 32 bit data we might choose to convert it into 64 bit data or to 32 bit data and do it parallely do it at a much higher data width and so on. To achieve performance so though FPGA lacks in row clocking speed maybe an ASIC will clock at say 1 gig or 2 gig maybe FPGA will clock only at say 200 megahertz or 400 megahertz at the most when reasonable complexity design is put into it. But by design techniques by kind of doing wide data computation multiple cores and so on you can replicate the number of computational units you can do a lot of parallel computation and achieve the performance maybe bigger than much bigger than the ASIC ok. So there is another disadvantage of FPGA the power dissipation will be quite high compared to the ASIC because of the huge area of huge interconnection and naturally the power dissipation will be much higher and you may not because these are kind of prebuilt the resources very custom low power design cannot be done in FPGA because the application is not very evident. So kind of very aggressive low power design cannot be done in an FPGA as an ASIC. So on 3 counts say the row speed the power dissipation the FPGA suffers but then definitely you can achieve high performance with a lot of flexibility of programming reprogramming configuring the FPGA will be able to achieve. So let us move on to the slide. So essentially if you look at the FPGA you have IO blocks and this we did not discuss the IO blocks always contain you see there are the tri-state gate based output. So which can be used as input so these are IO pins and there will be always a synchronizing clock. So we have seen the need for synchronization because this input is coming asynchronous to the clock we use which usually will be the case because we will supply the clock to the FPGA everything internally will be clocked by that clock maybe the signal which is coming from another chip maybe clocked by another you know the clock. So this need to be synchronized so there are synchronizing flip-flop single state synchronizing flip-flop within IO gate IO and it support multiple IO standards so it may be working with 2.5 or 3.3 like low voltage CMOS or it supports some kind of the voltage pattern which is ideal to the PCA express or PCI and so on. So all that is supported in an IO pin. So that is IO blocks then you have array of configurable logic blocks we have said the main thing to note is that it is not fixed it is configurable lot of configuration is possible within logic block. Then there are horizontal and vertical wires with programmable switches in between we have seen that you know there are horizontal and vertical wires with programmable switch. Then these wires could be single length, double length, quad hex or long lines and there are resources available to the user basically the logic block the flip-flop. Then there are resources for configuring the programmable switch in the interconnect sectors and logic block. So there are lot of programmable circuitry which program this logic blocks and program the interconnection of the wires. So that is in a nutshell it is an FPGA a simple FPGA. So in addition high level FPGAs will have as I said DSP blocks, the hard core memory controllers, the network interfaces and so on. So we have covered the essentials of the field programmable gate array. So let us look at this particular programmable connections which is available in static RAM based FPGA. As I said this SRAM is a bit of a unfortunate name the interconnection technology used is a pass transistor and we will see why it is called SRAM. The some FPGAs use flash transistor we have seen that in the case of CPLD and some use a technology called anti-fuse which is opposite of that of a fuse. So let us look at the static RAM. This shows a FPGA architecture with say four configurable logic blocks wires, horizontal wires, vertical wires and switch interconnecting the vertical wires. And this shows that output of a logic cell is connected to the vertical wire. So the connection is an NMOS transistor to connect that pass A0 and so basically if this N transistor is on the output is connected to this input. And similarly this vertical wire has a connection to the horizontal wire using an N transistor. So if the gate is made high it connects okay. Now the problem with this kind of SRAM FPGA is that it cannot remember it cannot it is not the state of the gate of NMOS transistor is not stored you know permanently. So at every power on this need to be programmed okay. So if you look at what can hold a bit a single bit is a flip flop okay. So at the gate of each pass transistor is a flip flop and now when we say we program we are programming the flip flop as 1 or 0 okay. So that can be so there is a flip flop here. And if you see there is a 2 to 1 mark you see here there are say lot of lines, lot of horizontal lines and now you can have a kind of crossbar connection we said that N by N crossbar uses a N to 1 multiplexer. So basically the multiplexer is the one which is so this is a kind of 1 to 1 multiplexer. But here you can think of say 4 to 1 multiplexer which allows you to connect any of the 4 horizontal wires to be connected to the input of a logic cell. So here if there are 4 inputs then you have 2 select lines so there are 2 flip flops connected to the select line. So if you have the ability to program 0 0 0 1 1 0 1 1 and so on. So now so you can imagine wherever there is a switch there is a flip flop. Now you cannot program this flip flops individually. So what is done is that this flip flops are collected together as a static RAM or as a memory which is 8 bit or 16 bit wide. In the previous generation it was 8 bit wide memory in the current generation it is 16 bit wide. So to program means you write this configuration memory which is SRAM. But the real interconnection technology is a pass transistor in an SRAM type of device. So I think we are coming to the end of the lecture. So before I think we instead of going further because then we have quite a bit in the programmable interconnection. So let us wind it up here. So what we have seen is basically general architecture of the FPGA a lot of IO blocks configurable logic blocks and which is distributed across the chip area. The programmable wires with switches in between which is again distributed not a single switch it is like array of switch with the regular wires laid. So the logic blocks can be interconnected through that and when you look at the logic block itself it is a combinational circuit and flip flop combinational circuits are lookup table multiplexers or gates flip flops. Then the interconnection technology is static RAM and diffuse or the flash kind of devices. And so that is what we have essentially seen about the FPGA we have seen the commercial siling salt era and you know actile devices. We have seen some of the families of devices. So the last part was the programmable interconnection we have seen the SRAM kind of technology. So in the next lecture we will continue with this programmable interconnect technology and go to the architecture of the FPGA to understand in deep. So I wish you all the best and thank you.