 Welcome to the last lab of design compiler, so till now in all the labs of design compiler we were doing top down synthesis, now let us look at a sample design and let us try and do a bottom up synthesis. Now bottom up synthesis is we will use I will also show you the characterize and this method type is used in this lab, this lab is directly taken from the documentation, so it uses compile it is an old lab it uses compile command and compile command plus the characterize and write script method is also not very popular nowadays, but at least with this lab you can also set up a design environment for yourself, this lab has multiple things that are being used, so it shows a good usage of soft bottom up synthesis. So also the method methodology is slightly old, but it still gives us a good insight into how to build aspects and what to check how to make sure that design is a net list and how to build it and how to arrange it and so on. Let me give you some, let me discuss some summary about the design itself, this design is the same that is used in lab through, so it is a small design, the top level is called chip level, it has a adder, adder block adder 16, it is a comparator, a MUX mod a multiplied by it multiplied 15 by 15 path segment and there is a cascade mod inside which it contains adder comparable comparator. So what we will do is that you really chips are built like this instead of small designs like multiply or comparator here, the chips will have big designs for example a and then CDT chip will have blocks like USB, HDMI, CPU and so on. Now so the idea here is that, so when you want to do chip level, you cannot for a big chip, you cannot just build it on the ideal type and do this, it is not easy because first of all because of the professional limitation of the tool. Secondly, even if let us say design comparator what people will have passing so many files, still synthesizing chip level, at chip level is not how to say, it is not intelligent why because like nowadays in industry different design teams own different intellectual property like companies or other things would own as they want and if you are synthesizing chip every time there is a design change in HDMI, you are also synthesizing all the other items right. So that is why bottom of course makes more time wherein, we synthesize the underlying design of design first and then as the chip level we will set these designs as both touch and we will compile the chip. Now how to do this, how to so this is clear that in bottom of that the bottom level the hierarchical design could be synthesized separately and then there will be a stitch together. The top level of chip level is usually does not contain any logic or even if it contains logic it is very non-time critical and it is very small so that you actually do not need any optimization to the top level. You just need to RTNHAR is mostly structure generated so you just take it to compile it so to make sure that it is fixed correctly that is the only concern. But now major concern is regarding that not concern, unless they are synthesizing individual part of software I need to have good timing constraints on your chip. If I am synthesizing CTU any block I should have good timing constraints because the optimization depends on that. Now consider so now we will so ideally every design team will write its own better constraints because it knows what all blocks are there, how they are designed. The only concern here is that what about the interface logic that you are talking to each other what about that interface. Now that interface is the only concern how to make sure that that interface is of no problem. For this you have set information also. Now the method discussed here which is the characterized by it is aimed at solving that problem. So it is a two part compile we find that it has lots of good sides and discuss we can have it with. So the basic flow is that at first level first of all let us say now in this example we will synthesize it is added all these blocks at adder, passcode, comparator, multiplier, multiplier, 16, maximum for all these components inside. So each design that is synthesized separately should have its own set of constraints first thing. Second thing in this example cascade mod is synthesized and here the since the comparator at top level and comparator inside cascade mod are both same. In cascade mod synthesis comparator already existing comparator can be stated and it is said to go on touch and adder 8 is not synthesized. So cascade mod if you look at cascade mod level it is synthesized top down but the chip level is synthesized bottom up. So first pass we synthesize each of them with some default constraints we will assign some input arrays and output arrays we will synthesize them. In the next pass is and then we will ask DC to calculate. Now what DC will do based on the first pass synthesis timing data it will allow timing budgets it will assign some input and output delays to the interface signals. For example let us say a signal is traveling from ADDR 16 to cascade mod its input at the level of ADD plus its output at the level of ADDR 16 and input at the level of cascade mod based on the timing data this has it will assign some output delay at ADDR 16 level and some input delay at cascade mod. Simply if we part delay the total part delay it knows total part delay of that interface from ADDR 16 to cascade mod and it will now break that part. And whatever timing it sees on the ADDR 16 side it will go as input delay or cascade mod side and whatever timing is reviewed inside cascade mod it will go as an output delay or ADDR 16. So this is the way it will assign input and output delay. So that is why first pass synthesis is necessary one pass is necessary at least to give DC the timing data. If let us say there is no synthesis is done DC will not have any timing data and it cannot characterize. So before characterize one pass compiler is needed. Now the second pass compiler is done now and then characterize the output of characterize command which will be a set of script. So that is why we call it characterize and write script. So we write this input we will put out to delay then go to the processing function into separate files for each design. Now in second pass we need to compile the input. So that decides the compile process is much more accurate than the first pass. Now but in the industry there is a slight risk to this method that we do we do not use characterize write script. Because see at to characterize for characterize a write script to work we complete with that although in the second pass all these are anything in the chip level synthesis all these are set as do not have they are not touched. But still the complete design data is to be designed. Now consider this problem at a chip level at chip level complete 100000 design data inside DC and it is writing characterize. If you try and do it for a big big chip the characterize will take long long long time with the long time lots of time and that is the problem. So what we do at chip level is that first thing in the industry what we do first thing let us say now the blocks and UFDs UFDs. So each design team will carefully write constraints for UFDs UFDs there will be separate teams who is working on this. So let us say one person for the strongly group will actually spend a lot of time in making sure that the constraints are open. Since these constraints will never ever be characterize by DC these are owned by the user these are noted by the user by the designer. So the designer will work on the constraint if we need a time input and output delays which are slightly more aggressive in nature for this block plus the designer has to make sure that input and output are registered. If the inputs and outputs are registered it is very very easy to work on the input and output there will never be a issue like this. So it is so every block has its own constraints every block will go through the system and now at chip level what I will look I will not be able to complete the problem. I will read the chip level but now I will read a file that is a value of file which is generated from electricity for CPU. There will be a CPU netlist but from the CPU netlist I will generate one more file that will only contain the CPU module definition with inputs and outputs nothing else it is a black box CPU. There are many if you can do it through SRIP you can do it with SRIP you can easily write out the black box verilog model out of the netlist. The only information you need if you need to do it from IBM the only information you need is the module definition and inputs and outputs that is it but no logic. Now I read when I read the top level chip verilog I read the CPU I call let us call this a black box module. So I will read CPU black box model I will read the black box model I will read HDMI black box model and what I will do is I will set them as don't match and I will compile my chip it will take 2 minutes my chip netlist is ready and then later in this chip netlist I will remove the black box and then using even design compiler I will remove this now I will read the complete netlist of input piece HDMI and CPU and I will write out this file. So this way no command in DC none of the command in DC except the write and log in the last we will see the complete design. So we won't have runtime issues this process can be done if you are few minutes to few hours plus you are assured that and then you will obviously do it without we have to do without the Fiat chip mode. Now if you have any if you see any interface that is what they are doing and that is not optimized often you can now feed this back to design to the respective design or to ask them to correct their port connection this is how it works in industry but this again respective of the method see the method is exactly same but in characterize side square the correction of input and output base is being done by DC but when if it comes to big big chips the characterize will be very time consuming so what we are doing we are doing this process kind of manually and sometimes manual works better than auto manual for example in this case but irrespective of the differences whatever lab we see now whatever setup we see now because they will be very helpful for you if you go and now you begin to understand that how things are done in big chips. So let us look at the the so this is the directory structure and so in the RTL has all the files all the files we have already seen that the chip level contains all the instances for U1 U2 U3 U2 2 scope site are there 7 instances then let us go to so again work is where we will work I have created directories here netlist log DB dbdb these are the output directory. So I will write out all the netlist directly I will write out on the log and not directly I will write out all the DB's in the db directory or DB or ddc whatever in the structure directory and then There will be a lot of scripts first and foremost as I told you each design will have its own script starting script the second set of scripts will be generated by character that is right script. So, here let us see the script for let us say we pick up a design either 16 let us see what either 16 that means, so we have either 16 got written. So, here we define some variables which will help us in writing out the report and the log for this particular design. So, report file is either 16 what actually we design is either 16, we set the current design we source the default some default instructions I will show you what default instructions contain. I set some design environment these are just estimated at the first step we define the load on s out and c out we set the driving cell to something either something on all the modules we set drive 0 to clock name now this clock is defined earlier I will show you where and we set some input delay and output delay and then we do a compile and then we do a write command we will write down the dc and then we will source a script we will do the reporting. So, what will happen in the start is that I have reached all the complete design and then I will change the current in the current design to each and every electrical design and then I do compile at that level regarding loads and driving cell it is all right, but in some of the designs there will not be any clock and in some of the designs there will be a clock. So, this is where we take care of this to call constraint where I define the clock delay and these cross these procedures kinds of collection get port CLK if there is a port CLK we we create a clock if there is a if there is no port this does the procedure checking if there is no port containing the clock name if there is no clock then we create a virtual clock and the clock name will simply be either CLK or DCM. So, any hierarchical design if there is a clock port in it then the clock will be created if there is no clock in it then the a virtual clock will be created input and output delays will be assigned to either the real clock or the virtual clock. Then again set load is set to default load there is some default driving cell is set I will change this which will be all x2 which will be the natural and then it will set y0 and y1 clock input. So, this will be the default constraints and I will also change the operating function. So, every design we will let us see now what how do we so you have the these are the adder task etc these are the constraint files with respect to each design and then there will be a report file which will just report out everything into one single report file. Now, this again this report file it uses variables called log path and report file. So, log path is defined in .dcsetup I will show you report file is something which is specific to each design. So, you will get one report with respect to each design there is a read command with a read dot ticker in which we read all the files on the regular files then there is a synopsis dcsetup which is in the work where we set the search path, the link library, target library and so on and here we define the source path the script path and so on. So, that we can use these variables called .log path. So, you do not need to this is a very useful tip that you define some variables related to path in .dcsetup or some common file. So, that you can use this variable and then when another user wants to use your set of scripts you can use it without modifying a lot of files you can just modify file you can just set some variables and then he can proceed he does not need to worry that let us say you are given 20 scripts he does not need to correct it each and every script he needs to just correct these things from what is specific to his things right. So, it is very good way to set up your work area. So, this is how you define your variables and we keep the common stuff in .dcsetup and then there is a top level run command run dot ticker. So, I will start. So, I will start I will not source this directly although you once your environment is stable once you have resolved all the errors you can you can keep using this file again again that is already chosen it. What I will do is I will source single statement at one time. So, first statement that is sourcing is initial compound. So, let us see what initial compile contains initial compile this statement will read the complete article as we saw read dot ticker contains all the read commands it will send the current design it will store the default constraint or default constraint is simply it will send the blocks and so on default loads and so on it will select the worst case operating condition. And then we read these 7 ticker files the 7 ticker files are nothing, but these are specific ticker files for in design we saw for other to see let us see let us say let us see one for path statement for example. So, again it will set what is the report file in design name it is like a parent design nothing, since we are compiling the under time hierarchies we have to change the current design and that it will again source and default constraints. So, any overrides you can do it here. So, for example, input today output today any load or driving and overrides should be done there and then it will define map. So, now this in this place you can do specific stuff which is some special stuff which is specific to each design default constraint is something that is default and these specific compile files for each design you can do something specific here. For example, in cascade mode in fact cascade mode has been a hierarchical design it contains 4 instances the cascade mode in turn contains for example, cascade mode contains a adder comparator in counter and we have counter which is map synthesized separately. So, here the counter is set to the comparator is synthesized separately. So, it says that use compile ones do not touch approach for comparator. So, this this lab is just giving you is showing you ways how you can demonstrate and these one of these ways should be applicable to your design when you are working in a project. So, this is this is how you do a do not touch and then for at the end of each compile step the DPC and the report will be written out. So, let us do the initial compile step we will open decision and we will go to work and open decision. So, meanwhile let us also clean up the report areas because I am the law I will clean up the support. Now, I will I will source the first statement of the run command and I do this source in script path script path is already script path is already set to something. So, we will show you script path was set in what is an offset DC set up. So, with opening when you open decision you should make sure that whatever is an offset DC set up is in fact loaded already. So, let us look at link library set let us look at the scripts path it is set to the parent scripts. So, now we will source this one. So, it will now start reading all the design files and the line design and it will start synthesizing. So, this synthesis whatever you see the log messages this is taking place at hierarchical level it is going to each in every design it is in this kind of design and it is running the compile command as a particular design. So, each design will have a DDC out set up with one reports this will complete pretty quickly. So, we see that there are flags there are negative flags in some of the design. So, this design has a lot of negative flags it is taking some time I have given a very aggressive process in this experiment. So, now let us look at the report directory which was set to log. So, now these are the reports with respect to each and every design. Let us open them let us open them and see. So, but the thing is that now the report constraints let us first. So, the report script that with the reporting for us it dumped everything into every kind of report into one single file for design. So, there is one single file for design in which there is a check design report area report design report constraints and so on. You could choose to create separate reports for separate commands. It is a personal preference and you can choose to do whatever you want, but obviously it is good to have separate reports for separate design. In fact, maybe even a time in report which is separate because that is more important. So, let us look at the reports now. So, now these are the reports this is the area report for for adder 16 and report design and report port. Let us go to end and see what are the this is the what are the timing violation we can this is the the QR report. We see that let us go to report constraints or let us go to the report constraints. So, report constraints minus all valid that tells us that max area we set the max area to be view although it is not needed to set this constraint. So, here it tells us that there are some end points that are valid because I have set a very aggressive drop there are end points that are valid. Now, it tells us what is the timing now see here ok the input loop is fine input loop is fine. The rest of the timing is also fine what is violating is let us go to the violated ones that is all ok fine that is all ok. So, report timing is telling us ok the flag is positive. So, the report is constraints is not all valid because yeah. So, this is the report constraint and the max parts this is the report timing command part type end part type end means only to report on the end points. So, we will do the only thing that is violating is the area. So, we are fine here let us go to the next one which is cascade mode. Now, cascade mode has again a kind of a high field line where you have two adders one comparator and you have two adders one comparator and one comparator. So, again let us search for violated. So, now there are some timing violations there and seems like there is a GTEC component which is very strange that means this is because this GTEC component is very difficult let us check the script the most script. We need to debug why does the GTEC know and there are violations obviously to report the I think the effect to report on the worst part there is a violation from info code and so on. So, we need to check why there is a do not touch here why there is a GTEC yet and then we look at COM 16 report block yeah. So, there is a virtual block here we see that it does not contain any block code. So, you know virtual block created it has violations because ok one thing that output external delay said to be very high because the clock delay is high because that is the clock delay that again very aggressive, but the delay is but it was over there. So, you see the violation same that is ok good to have because now DC will adjust these. Now DC will adjust these input and output delay and make them more real. So, ok let us so there are similar similarly there are reports for even every design. Now, let us debug why did the Cascade mod had GTEC components. So, the problem is that the Cascade mod has it has a GTEC is because we have said do not touch on U 12. Now, let us open U 12 so it is a good test case for a we get to debug some problems also. Let us open the RTL and see Cascade mod and we see that U 12 comparator setters do not touch. Now, when we compile for the first time add if the underlying design let us say U 12 here it said to be do not touch, but U 12 is still not compiled comparator is still not compiled. The script here it is it is reading the RTL the initial compiled thing is reading the RTL it is reading the RTL here and now it is sourcing. So, when it comes to Cascade mod it is said add do not touch U 12 etcetera do not touch. So, DC in fact, never gets to compile with underlying the design that is U 12 which is comparator. So, second pass it will get connected probably and let me see if it is not then do not touch here is not correct. So, in that case we need to remove the do not touch and we could read the either either we should compile the comparator again the sourcing and then when we come to Cascade mod we should read the comparator again. So, there is a there is a problem in this set of script is that it is setting do not touch. Now, let us see if this problem gets corrected in a subsequent steps. So, this is where initial compile is this is where we do our do our first compile what is important here is it is very important thing is that you should have proper timing constraints for each of the underlying blocks. Also if you are using characterize and write set you can start with some basic revisions right with respect to input output. Now, let us again set the current design to be chip level then we let us go back to decision. Also let me show you that DDCs are written here it is net specific I do not think so net specific. So, let us set the current design current design always remember if you are doing design change the current design if the current design is not and you are changing to hierarchical design. But before doing any chip level any top level please remember to change the current design top level whatever is the top level. And now it is writing at a DDC which is ok we will write out the chip level DDC. So, it is always good practice to write out DDCs in the DDC. So, that your snapshot is taken and let us say if you want to figure out what happens before the characterize command you can load up the DDC. So, now let us do the subsequent step which is characterize. Now, we need to characterize now let us see what characterize command what characterize chip is doing there is a script for characterize. Now, this characterize chip changes the current design. So, this is yeah. So, this way what it will do is that it will characterize it will go to chip level it will characterize U1 then U2 then U3 then U4 then U5 then U6 U7 it will characterize when you characterize DDC will calculate something and then you can write the format is DCTC and you will write out these scripts. Now, these are now the updated timing constraints I show you what each of these constraints contains and then it is doing. So, what it is doing in the last it is now what you could do is that to each of these timing constraints if you want to add any specific command for yourself by you are going to say what you want to do for specific like there it is grouping the design went into and it is grouping this design is creating a new group and it is adding this command this group send this group command to the path segment. You will see what effect does it have and then it is format is DCTCN yeah. So, it is it is characterizing U7 then it is changing the current design. So, current design changing is necessary because if you do not change the current design DC will write the path information in terms of the top level hierarchy. You want to make the show make sure that hierarchy is correct for each and every design that is the script should be at the top the script should be written after the design is set to that particular current design in the sense that for example, that you want to write can characterize and write script you will characterize some top level, but when you do want to write script you will have to change the design. For example, for MUXMOD you want the MUXMOD timing constraints to be specific to MUXMOD and not contain hierarchical references to chip level that is why you characterize some top level, but you change your current design change your current design and then write this script. So, here current design is changed is first characterized and then some particular command whatever special thing you want to do is written into this script is this command is written and then this is written into this is redirected and this is appended and this direct script is also appended too. Let us see what we will learn direct price now and see what are what happens we go back to DC and we will. So, see every every source command has a dollar script path which is a variable and the script path is set to now this can be set in dot now this can be set up to anything where your scripts are. So, if you are changing the place where you keep your scripts you do not need to change these all the other script right this this is why the variable that can be defined variable that control the path it is better to define all of them at one place. So, now it is doing something and it gave a error we will correct this and we will correct by the name ok let us correct this ok. So, DC tkl format is not ok. So, we have to ok this this is the problem ok. So, we will source it again it is not a problem we can do characterize again it does not happen. So, now at the end of characterize I mean each write script we are writing a DC tkl file into the script directory let us now see what DC tkl file let us see it for it is open all DC tkl file you can see what it did. So, now see it is setting the current design to the Ida 16 units operating condition by load model particular by load model whatever is selected. So, whatever DC did as part of its synthesis plus it evaluated the timing constraints it will write everything in the DC tkl that is the driving cell the by load model whatever should be used based on the by load model selection PEN out number then load whatever it found see now these loads are not some dummy number these load since we are using characterize the one and already one-par synthesis is done DC load got load to expectations the real load real PEN out load not be dummy or full load. So, that is why you see numbers such accurate number. So, this is where characterize helps you this is the various system in place which will form a 1 1 basic synthesis stuff which is already done. DC let us let us you calculate the accurate analysis condition or more accurate than the earlier part. With each new part if you notice this is simply not a true pass procedure although minimum true pass is needed, but you can also have a third pass that will still improve accuracy. So, many people they will do a 1 pass basic plus 2 pass time frame many people will do just 1 pass time frame just depends on the quality of results that you are getting out of every pass. And now the input delays some of the input delays are see now here the input delay is 1 to 1 dot 2 now this probably is coming from the chip problem. There is a fixed input delay for every port that means this input delay is coming from the this particular port of average 16 is coming from the chip top. And there is little or no connectivity there is there is a simple net there is no way that is why all the input delays are 1.2 and they are of same for all the input ports, but output delay now change is for few ports. Output delay becomes much more accurate for S out because this port is going to some other design some other hierarchical design you will see it at the average. So, it is defining max and min let us see let us go back and look at the RTL. Let us look at the RTL of chip level. So, chip level let us look at data 16 A is coming from chip top that is why whatever input delay we did at data 16 A at chip level is transferred to AL because there is no cell in between, but S out is going to other hierarchical design it is going to comparator it is going to max mode. So, DC based on the interaction of data 16 with these two it has now worked out an output delay. So, we saw that S out has some output delay then A in and B in have fixed input delays and this value of 1.2 is coming from the default or constraints. So, in default or constraints we applied input delay the input delay 1.2 on all inputs this is where it is coming from. So, now I think you would have started appreciating how that is coming from your, you have to do one part synthesis from this netlist from this consuming function DC will now calculate it will calculate output load, calculate input load output delay and so on right. Now, let us see what is the next step. The next step is the second pass compile. So, now it is saying remove design minus all now we have to clear remove design we do remove design minus all it will remove all the designs and then we are doing something with the recompile we are sourcing the recompile. Now, let us see what recompile is what recompiles this is doing. So, recompile obviously there it is reading RTL now we start from the RTL this is now the first class you had your own estimated input output delay and the environment conditions for each design. After characterize you get more accurate number and now you want to start from RTL it is always better to start from RTL. So, first line we are sourcing all the we are reading all the actual files sourcing of the file constraints and now we source the DCPCN compare compare this is the recompile and this was the initial compile this is the initial compile. Initial compile was also reading it was doing the same thing in the top the file constraints it is doing the same thing in the top, but these ones these specific design specific constraint files are now replaced by the DCTPL file. Now DCTPL file by default is the current design we saw that. So, now this is reading DCTPL this is now the synthesis script it replace your own estimation right. So, this is why I see this is the other thing to appreciate here is how the script files are available yes arrange so neatly that it is very easy now to replace anything or replace any design even if you design changes a bit it is very easy to do more. So, spend some time all in also understand how the scripts are arranged this way you will learn when you will work in your project or in your industry how to arrange your constraints. Now after sourcing this compile command is run and then again we will write out the deal and again we will write out the report right and we will also look at the cascade mode ok. Now path segment first has something special because path segment DCTPL. So, TCL is the one that user code DCTPL is the one that design compile mode. So, current design so this is where the something special was added a group command was added and a new design multiple created and MULT and U 100 cells are combined together. Let us see whether we can correspond path segment not be. So, MULT and U 100 and U 100 is combined together with ok I am not sure why group command is move with minus MULT and U 100 ok I am not sure why why group command is nothing it is just to show you that whatever stuff you want to add you can change the current design and you can add it in the same way. So, let us now source this second so we need to look at the cascade mode again we look at cascade mode dot DCTPL and look at what happened to U 200. So, again set do not touch it set here on U 200 let us see if it really solves the problem. So, we see that clock definition is also there or everything is there and let us say for a for a clock that does not have a clock and get smug smug does not have a clock you have you have clock add a 16 it also has a clock comparator I think this does not have a ok it also has a ok this is now a virtual clock because there is no ok there is a port clock it is not created and this create clock is not created on any port. So, that is ok. So, it tells so this in this case the clock is a virtual clock. So, virtually every information that is needed for synthesis is is written out by a characterize right. So, we will now source this we can find now it is doing synthesis and now let us see whether it contains as many violations as earlier. Now, we see that earlier we are seeing some lot of violations because we gave. So, what I now there are few violations why because the input output delay that will become more and more and more actually earlier what happened is that the original still had the clock delay of 12 I changed the clock delay to 5 I made the clock very very aggressive, but I did not play with the input output delay. So, input output delays for this example in earlier case was actually very very very bad values and that is that is a bad value and then the characterize right script now showed us that DC now calculated calculated accurate values and now at least these hierarchical design synthesis is going on faster and now you do not see violations. Now, let us look at the reports now. So, now, earlier the reports were dot r p p now the new ones are d c t p n dot r p p. So, let us look at the violation in one of the designs. Let us look at the there were violations in let us say multiply usually multipliers are the designs let us see multiplier 16 and we will open both the scripts. So, this is the d c t c l 1 we will search for violated here and we see that ok area is something 2066 and the stack is there is no negative factor as it is shown by the report time. Let us open the earlier the earlier one let us search for violated and now we see violations. So, we see big violations why because the input delay input external delay and what is the problem here ok this is input to flop the input external delay is the laboratory hold time is so with here because of some issue some issue in the the constraint the laboratory hold time is 50 bit. So, we have this big violation here. So, we see that earlier there are big violations, but now because of the characterized I split we get some accurate timing constraints and the violations are virtually reduced to 0 very there are very very few violations in the design. So, this is where you work even if you so this is where characterize rights it help you you do not have to spend so much time in writing out constraints for each and every constraint if you want to characterize you can start with some jump constraints and then characterize rights you will do a good job for you right it will take care of the interface time. Obviously, the top level the port level input output timing you have to be careful about. So, in this case for example, the ports that go from the the ports that exist at chip level you have to write good input and output delays for that because characterize will not work on that characterize will work at we saw that added 16 is directly connected the other 16 input pins are directly connected to the top level port and the input delay in this case is not changing. So, the top level input and output delay will not change only the input and output delays with respect to the hierarchical designs will change because now this thing has a function about interface. So, let us look at the cascade same cascade underscore dcctl and see violated area is fine and then there is no violation which is good and I guess cascade does not even have now it does not have the the geotech logic because now the comparator was combined it was compiled one in the first part the comparator was being compiled after cascade mode, but in the second part let us look at the decompile script again to understand it better yeah. So, we started from dv from this cascade mode dvcl we compile and yeah. So, we we set the report file and we when we wrote out the report let us look at now in this case what is happening is that you see the let us see what all it wrote out dvcl are written out yes dvcl is written out and then what about netlist is there any netlist is of no now let us do the last step. So, we did we did the first compile we should compile the second pass compile the character and then second pass compile and now we will write out the dvcl and we also write out the netlist we will write out also the netlist let us use the same command netlist let us say netlist so we wrote out netlist here so we wrote out the netlist let us open this. Let us find out if there are any geotech components here that would be taken here. So, if that problem got resolved solved because we compiled it will be compiled. So, first time we require people already compiled now let us look at. So, there are no chip level timing reports here although I would like you whenever you work I would also like you to add chip level timing reports because that is the most important criteria. Now, let us do some chip level timing analysis we will do let us remove all the designs let us read ddc of the the chip level we will read the initial ddc I want to point out a very important thing I will link and I will do a report timing because it is a ddc it contains all the or what I will do I will do report constraints minus all. So, we see that there are some set of violations here. So, we will what we do we will note down this and we will copy it and then I will remove the design again and I will. So, let us let us also see what kind of violations are there. So, this is a violation from input port to the register and register is inside multiplier. So, this is a particular violation right are all these violations of the similar nature look at there are 4 violations data 16 yeah all the violations are similar. Now, I will remove the design again I will read ddc and now I will read the final ddc I will do a link I will now report constraints minus all wallets. Now, the design has no wallet constraints how did it happen although there were violations from input port to register inside multiplier how did happen. Now, if you compile the design using single pass using top down there will not be any violation right, but we did not do that. So, what how it happened is that in the first pass what is remember we did not compile it from the top we did a bottom up. In the first pass if you remember we did multiplier we did synthesis for multiplier that is separated. The J and C current design to it we had some default set of constraints and we synthesize multiplier 16 by 16 and then we characterize it and wrote out the second set of constraints. Now, whenever it was compiled the first time around initial synthesis the compilation did not optimize this path very very because the input delay as the multiplier level was some non-optimism value. When the characterize command wrote out the input delays the new input delays these new input delays were well done in real space and in the second pass compiled dc was able to do a better job. Therefore, in the final net list we do not see any violation, but we see a violation in the initial path this is the summary of characterize high school. This is how it helps you it is the most accurate way of writing constraints for hierarchical design. So, if you are confused about which similar network to take the design compiler capacity and the number of cores in the machines and the number of memory machines have been going. So, every year it is possible it is getting more than more possible to compile a design top down which was not possible a serious back or which was not practical a serious back. So, I would recommend still if you are working at any design or if it is not a big chip then start think about the top down and make sure you have a top level constraints on everything. If it is not possible if top down is not possible go bottom up arrange your stuff in the similar passion which is shown by this example use characterize write script only when it does not take days to come or number is say more than few hours to complete. If characterize write script is taking more than few hours to complete then rethink about that and may be go may be go with the in the direction that people took this level that is they compile they synthesize that does this block separately and at the top level they just use the platform and do not add, but in this case you have to make sure that your hierarchical designs input and output is a very very good because obviously manually you will not be able to do a job as good as design compiler. So, now you know all the three ways to do synthesis top down bottom up using characterize write script and bottom up using black box. So, I hope this was useful Thank you.