 Hello everyone, I am Prashant S. Malge, Assistant Professor, Department of Electronics Engineering Walchand Institute of Technology, Solapo. Today, we will discuss Built-in Self-Test, the learning outcome. At the end of this session, student will be able to explain Built-in Self-Test method till now we have seen that the testing of the circuit can be done by applying some external inputs and verifying the results obtained from the circuit, but this requires some external equipments to be connected to the circuit. Now an interesting question is whether it is possible to incorporate the testing in the circuit itself so that no external equipment is required for testing the circuit. Such a built-in capability allows the circuit to be self-testable. Now we will discuss one of such technique known as Built-in Self-Test. The figure shows a general arrangement required, a test vector generator reduces the test vectors which are to be applied to the circuit under test. Now the responses received from the circuit are to be compared with the expected outputs for all these test vectors. The response of a good circuit may be determined using a simulator tool of a CAD system. Now these expected responses must be stored on some chip for comparison during testing. Now you will see how to generate the test vectors. So this is a pseudo-random binary sequence generator. So one of the practical approach for generating the test vectors on chip is by using pseudo-random test. Such as pseudo-random test generator can be easily constructed using a feedback shift register circuit. One possible arrangement is shown here. Here the output of the fourth stage and the first stage are fed back to input through an XOR gate which generates 15 different patterns. Similarly this circuit is a representative of a class of circuits known as linear feedback shift register. Now consider that the values X3, X2, X1, X0 are initially set to 1 0 0 0. So in this case as this X of 3 and X of 0 are given this is 1 and 0 so XOR of that is 1. So this 1 will be shifted in the circuit in during the next clock cycle and so the next time the output will be 1 1 0 0. Now XOR of X3 and 0 is once again 1. So next clock cycle this one will be inserted so the next pattern generated will be 1 1 1 0. This way as shown in this particular table it generates 15 different patterns. You can see that all 0 pattern is not in the table because once all 0 is inserted the state of these flip-flops will not change. So this is how a pseudo random binary sequence generator can be used for generating the test vectors ok. Now think and write what maximum number of test patterns can be generated by an N bit linear feedback shift register. Pause the video for a minute and write down your answer ok. You might have written your answer as all 0s is not allowed the maximum 2 raised to N minus 1 test patterns can be generated using an N bit linear feedback shift register. Now we have generated the test vectors. These test vectors are applied to a circuit and now the responses received from the circuit are to be compared with the correct or expected output. So it is not attractive to store a large number of responses to the test on a chip so that they can be compared. The practical solution is to compress the results of these tests into a single pattern. This can be done an linear feedback shift register circuit as shown in this particular diagram. Here the result basically this is a single input compressor circuit, here the result of the circuit can be given as a P and this is a linear feedback shift register. Once again the output of the fourth stage and first stage along with this result are in inserted into a circuit. For applying a number of test vectors the resulting value of P drive this particular single input compressor circuit coupled with the linear feedback shift register functionality. This produces a 4 bit pattern at the output. The pattern generated by the compressor is generally known as a signature of the test state circuit for the given sequence of test vectors. Now this signature obtained from the circuit can be compared against the predetermined pattern to see if the test state circuit is working properly. And so for storing a single pattern as a signature is not a overload on the circuit. Now we will see a multiple input compressor circuit. If the circuit under test has more than one output then a linear feedback shift register with multiple inputs can be used. One such circuit is shown here. In this case this is a LFSR configuration. Here I am assuming that the circuit under test is producing 4 different outputs they are given as P0, P1, P2 and P3. So through these XOR gate those are inserted into a circuit. Once again after applying the test patterns the generated outputs are given to this circuit and it drives the multiple input compressor circuit. The patterns issued that is P0 to P3 will be different on different clock cycles and they will be for each of the input test vector. 4 bit signature generated at the output provides a good mechanism for distinguishing among different sequences of 4 bit patterns that may appear on the input of this multiple input compressor circuit. So this is how the circuit with multiple outputs can also be combined and finally a single 4 bit pattern as a signature is obtained and this signature is now to be compared with once again a predetermined signature for testing that the circuit is functioning correctly. Now we will see how this beast that is built in self test capability can be used in a sequential circuit. As we have seen in a previous lecture the scan path technique is used for testing the sequential circuit. Here these are the external inputs W a multiplexer is used for giving either the external inputs or the inputs which are generated or the test patterns which are generated from this pseudo random binary sequence generator X. During normal operation this particular multiplexer will give you the external inputs during testing the test patterns are given through this multiplexer. The output generated from the combinational part Z are given to a multiple input compressor circuit through which a signature is obtained. Now the next state variables are given to a flip flop and this multiplexers where the multiplexer are forming this shift register part. During testing present state variables are given to the circuit through this serial line. For example, if I have three state variables then during three clock cycle three values are inserted. At the same time whatever output is received here that is next state variables are scanned out through this and they are compressed through the single input compressor circuit and this signature is obtained. And finally, the signature obtained from this and signature obtained from this are compared for testing the circuit and it is decided that the circuit is functioning correctly or not. This is how this built-in self-test capability is useful for testing the circuits. References, thank you.