 So, in this lecture we are going to be seeing a different world of modules which are going to be part of the APB verse that we talked about in the last lecture. So, these are all about peripherals ok. So, there are plenty of peripherals and you know it will not be only possible to cover all of them and there are plenty of implementation too from based on which company is giving and what kind of features they are supporting in those peripherals. So, my intent of this lecture is to give you an overview of the manager important categories of peripherals and their high level functionalities. Maybe I would have referred some specific implementation which I am referring to that in the note below, but this features what I am listing here may not be only restricted to this it could be more than what I am giving here or it could be a subset of this or there may be some changes to those features which are there in a particular category of peripherals. So, what I am going to be sharing in this lecture is only a an overview and then a likelihood of whatever features could be supported in those peripherals. So, it is not limited to that what I am listing here and you know you may have to refer to a particular implementation of the peripherals to know what all the features are supported and how to program them because each peripheral the each implementation may differ in terms of how to program them. So, I am not going into details of which registers and which bits need to be which bits in the registers need to be configured because that is not universal and it is not specific to a you know it is not accepted standard may be there are some conditions that most of you mostly it is implementation dependent. So, you may have to look at the documentation of particular implementation to consider a particular peripheral. So, here let us see what all the peripherals are there and how you know we will give you some overview of each of them. So, that when you both and read some manual of particular implementation you will be able to appreciate what is supported there. The rest of the lectures are going to be two lectures on peripherals and some interconnect protocols and then we will control it with the few details on the features and the of the the let us advance on from here. So, in this lecture we are going to cover this following thing. I am sure all of you would have heard about it or used it in some of the other the direct memory access DNA. So, let me just give you an overview before we go into the details. So, may be I am sorry about this particular ok. Let us see I have a picture and you know which will give you some more details so and I can you know explain more details about the DNA where exactly it is used ok. So, let us go into the slides. So, DNA is used in order to provide high speed data control ok. So, as the name suggests it is directly accessed ok from the memory. So, you know so far we have been saying that if you need to access a memory the processor in the system needs to give the address out ok and then the memory will give a data back ok. This is what we have been told or we have been discussing ok. This is the address who has to give address it is the processor ok and then the memory as a slave device this is behaving like a master the processor and then drives the memory cycle ARLBM or LBR or SDR or SDR instruction. So, memory gives out a data or may be we can write into the memory, but this is not the case always because if you want to involve the processor for every transaction in the memory then it is going to slow down the whole system because processor has some other important things to do other than copying or taking from memory. So, to speed up this the concept of DMA key that is called direct memory access the memory is accessed directly not through the processor ok. Now, you may wonder who wants to access it it could be that you this is ASB bus let us assume that this is AHB ok. Now, I can say what bus I am using because you are all familiar to the AMBA architecture now. The APB bridge is here and then the APB bus is there on this side and then assume that there is a controller I call this as a disk controller. So, sometime may be disk controller could be on AHB, but let me assume that this is access through this for a moment ok or it could be a serial port also here we can have a serial port and then you know you are you are you are a serial port controller and then a serial port is connected. But if there is a need for a transfer of bulk of data into memory ok from some it could be a disk controller or it could be a user here you are may be we know it is a PC connected to this. So, suppose programmer wants there is some buffer of data may be a few bytes it could be few bytes or it could be on page of you know memory data or course needs to be copied into the main memory I am calling this as a main memory. Now, only one way of doing is to on initiate the transfer ok copying from APB to some register here and then from register to memory. So, you can see that if you need to copy a character coming from a peripheral and to be written into memory the peripheral is a slave device. So, it needs to be accessed by someone. So, it could be a processor. So, ARM can access the peripheral register because it is all mapped to a memory, but you cannot do a memory to memory transfer. Memory to memory transfer if you have noticed no instruction in the ARM suppose this whether it is not the kind of a risk instruction ok risk instructions always have a processor register to memory or memory to processor instead, but there is no memory to memory to transfer that is that instruction itself is not supported in any disk family. So, maybe few of them will have that a unique commonly you know if there will be always a exception for this kind of rules, there will be a risk family of processor and in particularly in ARM we have the LTM and STM instruction which which are the only load store instruction with a memory that also it transfers to and fro from memory to register, but our intent is to get some few data blocks of data or a page of data into memory. So, that is from peripheral to memory. So, that cannot be done directly from peripheral to memory unless we introduce a new block in the discussion ok that is called DMA. So, what the DMA does the processor accesses this as a another module in the bus it could be another co-processor or it could be implemented in any way you want, but this registers are it could be accessed as a peripheral also ok and that means, you know it is a it is part of the memory and the this registers are mapped to a particular part of the memory. So, we could write into this some details so, that DMA takes care of transferring from may be a you are here to a memory. So, to do this somebody has to initiate it because this is not a it will behave like a monster, but somebody has to initiate it it cannot do it on its own. So, that is done by a processor like R or it could be done by another processor if it is a DSP processor it is also a master there you know that edge viewers can have multiple master. So, if DSP wants to transfer some data from may be a a speaker or some device or a no video file and then it wants to put the data into the memory before the DSP can process the data. So, even the DSP processor can initiate it, but one of the other processors who can be programmed can initiate a transfer what they do they program the DMA with some information. So, what are the information that they need to give for a transfer of a data say let me choose some other color is seen by particularly. So, the intent is ok let me take a look ok this is the may be a peripheral ok some memory some peripheral ok and this is the memory m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m from the device ok from device is there. So, this it will be writing into one word is now written into that from the device once it is copied from to the memory one more data will come. So, we have to say what is the start address ok it could be the same address and then where the destination address source and destination ok it may be a source address source address and the destination address. So, this is what we are providing into the DMV ok and then we will we will say that what is the length of data from this source address you copy into the destination address this much of length of data may be telling you know hundreds and hundreds words. So, what will happen if you suppose if it is coming from where the device which is supposed to be giving packet of may be a network device which is giving you a hundred words at a time it is supposed to give a hundred words assuming that then you can configure the DNA ok say that you copy starting from this peripheral address to the start now you block some part of the memory and make sure that it is not taken out stacked out or it is not used up by some other process it is it should be free of any access ok it should be only accessible to the DNA preferably other regions and other thing you know the right information should be there, but it should not be over turned by some other some other process or some other procedure. So, you should lock it with this particular area of memory then we can tell DNA the process right that is it, inform the DNA programming their destination address and the start address and the length of the data to be copied. So, if it has to be you know from where it has to be read and where it has to be written to once this is given the DNA starts out there before involving the process that means all free of this transfer once it is written once it is passed on this information to the DNA takes care of transferring it after the complete transfer is done it will interact. So, then and the handler will come and then look at the data then inform the you know procedure process which is waiting for the data then it will take on to the processing as I told you originally you know the ME processing needs to be done by wrong that data has to be in the main memory it cannot be in a disk you know or a peripheral or it could not it you know it cannot be in peripheral registers and you know use it for processing it using ARM instruction. So, before that they have to come to the memory and the responsibility of copying the data from the peripheral to memory is given to the DNA. So, once the DNA is programmed whenever the A visit free of any ever the transaction the DNA also tries to you know get the bus the arbitrator will be looking for all the markers this is one marker here and this is another marker and ARM is another maybe third marker. The three markers are there they will be sharing the bus among themselves and then once this is programmed it will start up with the copying of the data as under the data is available. So, it needs to be available and then it will come and then get programmed and copied. So, this is what happens this is what is done in a DNA. So, I hope this is clear. So, it could copy from peripheral to memory as I explained or it could do from memory to peripheral.