 So, the question was that you know that is an extra advantage because what happens is that there is a drain and there is a source the input is at the source the output is at the drain but the in between terminal gate is actually grounded. So, therefore, the Miller capacitance actually gets grounded right. So, therefore, it is AC performance is better AC performance of the upper transistor is better that is of course, given but the point is right now we are talking of the DC gain and even the DC gain is boosted and the contribution to the boosting of the DC gain is through increasing the output in the output resistance of this. So, that is what is happening essentially if there is a fluctuation of voltage here there will be a current fluctuation here this current fluctuation will be the same as the gm of m 1 and because they are in series the same current flows through both right. So, therefore, the effective gm of these two transistors is the same as the gm of this transistor on the other hand the g 0 is multiplied by the common well common mode gain common base gain common gate gain of this transistor ok. So, g 0 is improved gm remains the same. So, the overall gain is therefore, the product of the two gains ok gm remain the same g 0 got multiplied therefore, the gain also got multiplied g 0 got reduced r 0 got multiplied ok. So, this is the product of the two gains. So, in short the gain is the product of the two gains the gm is the same because gm is the same gm by c is the same ok. So, it will if it is loaded externally then while the miller capacitance will make have a lower impedance, but the cutoff frequency is decided by external load ok. So, now the external load will decide the frequency and your output impedance is high and therefore, the bandwidth will be lower ok. You can also do this by just putting the transistor model across here ok. So, this is the lower transistor on top of that is the upper transistor this is c 0 you do it using networks you get the same result ok. So, now we have got something good, but there is a bit of a problem with this and that is that the DC voltages are not compatible. Remember this input voltage will be somewhere above v t n so that we get into the linear regime right. So, this will be somewhere say within a volt of ground, but this voltage is much higher because there is a full VDS in series with that. Therefore, the output DC the fluctuation is not amplified, but the output DC is very high and therefore, it cannot be directly connected to the next stage ok. If you want to do capacitive coupling then large capacitors cannot be put on chip ok. So, this is a big problem with the ordinary so called telescopic cascord. This is called a telescopic cascord but it looks like a telescope these two portions one on top of the other ok. So, the DC compatibility in a multi stage amplifier is difficult ok. So, the first question I ask is if this is a good differential amplifier ok and actually it is not a good differential amplifier, but you should ask your students is this a good differential amplifier they must first appreciate that this is not a good differential amplifier otherwise you know you teach them some very complicated circuit and they say why is all this complication necessary right. So, first they must appreciate that a simple solution is not a good solution ok. So, what I am suggesting is that I take two transistors like this I apply V i 1 here V i 2 here ok. These two transistors are identical these resistors are identical therefore, their gains are identical ok. So, V 0 1 is a times V i 1 V 0 2 is a times V i 2 therefore, the difference of this. So, a times V 0 2 minus V 0 1 ok the V 0 2 minus V 0 1 is just a times V 0 1 minus V 0 2. So, it is a good differential amplifier. So, why do not we simply use this what is the problem can you spot the problem why cannot we use this as a differential amplifier otherwise this is a simple rather than all that long tail pair 3 current source all sorts of loads and so on. So, why is this not a good differential amplifier ok you can read the answer of the top but also try to apply your mind what happens is that not only do we want high differential gain we wanted to ignore any common mode voltage. That means if the same voltage is applied to both the terminals then it should not affect the gain of this right. In this case what happens is that suppose I raise both the I am the same differential voltage, but suppose I raise both of these voltages let us say by half a volt right the differential is the same, but the absolute value dc value of both the gates is raised by half a volt what will happen to the current current will be much high in both of them and the gain depends on current right. So, even though the output will be proportional to the input difference the differential output will still be proportional to the differential input, but that proportionality constant which is the gain depends on the common mode voltage. Therefore, this circuit will respond to common mode voltage it will not ignore the common mode voltage as a result its common mode mode rejection will be very poor that is why we do not use this for as a differential amplifier otherwise very simple that is also why that if you do not want to worry about common mode voltage this is actually a good differential amplifier and should be used for example many circuits in the these earphone amplifiers for you know hearing aids and so on they need to go till the battery becomes very very low ok so that the battery life is enhanced and common mode voltage does not matter the bias is not going to change a lot there they often use this circuit as a differential amplifier ok it is because it saves there is no voltage drop across a current source at the bottom ok. So, these decisions are not automatic that this is a differential amplifier and therefore use it how it comes about this is a possible differential amplifier in certain applications might be a good differential amplifier though in a general occasion an op amp will be very bad so what we do is we put a current source here now because this current source if these two voltages are same irrespective of what their absolute values are if these two voltages are same they will get the same fraction of this current source ok. So, we put a current source then half the current will go here half the current will go here as a result if the common mode voltage changes the current will not change earlier it was grounded right but by putting a current source here even if you change the common mode voltage the current through each transistor remains the same therefore the gain remains the same this therefore will be a very good differential amplifier. So, we will use it ok I want to get to the tutorial of this so this is an amplifier and if for load it uses this see suppose you want a differential output that means you two inputs two outputs then that circuit would have been ok but in reality what we want is a single output which is proportional to the differential input ok and that is done by this single ended output ok now this is a slightly not a delicate argument but you have to look at the details of this so we will take a minute over this what is I out this is the fluctuating current in the output it is the difference of the current through this and this right this guy sources a certain amount of current this guy sinks a certain amount of current and the differential what comes out of the output right. So, the I out is I of m p 2 and from that is subtract I of m n 2 right so this everyone agrees with ok now I of m p 2 is the same as I m p 1 because this is a current mirror you agree with that this is a current mirror ok. So, these two currents are equal but I of m p 1 is the same as I of m n 1 because they are in series. So, the same current has to flow through both correct. So, therefore, I can put instead of I m p 2 I can put I m n 1 right I of m p 2 is the same as I of m p 1 I of m p 1 is same as I m n 1. So, I can put I m n 1 here right so the I out is I m n 1 minus I m n 2 right which is g m times v i 1 that is I m n 1 minus g m times v i 2 right. So, this is the output current now if I want to define this as a black box as a difference amplifier then I define a capital g m this is a definition not derivation this symbol. So, I define a capital g m such that current is this g m times v i that is how all g m are defined right the output current is g m times input voltage now input voltage is differential. So, I define a differential g m such that the I output is this g m times the input differential voltage right and from inspection again simply say that this g m is the same as this g m correct you got it. So, the effective g m of a different is the same as the g m of a single transistor ok you do not get twice again because you have two transistors right you get the g m of a single transistor as you can see from here right this is the single transistor g m of m n 1 this is the single transistor g m of m n 2 take the differential and if you define capital g m like this then capital g m is same as the g m of a single transistor even though you are using two transistors this part is clear as soon as that is there then many things immediately follow ok. For example, the g m by c is the cut off frequency right at which the gain will drop and that is the same as that of a single transistor. Now the gain of this output stage right that is g m times r now if you look at this point this is at ac ground there is no fluctuation here 0 fluctuation therefore this is ac ground d c at v d d, but ac ground and so is this point at ac ground right because of differential amplifier. So, then this resistor and this resistor are effectively in parallel ok so that is the load resistance g m times the output resistance of m p 2 in parallel with output resistance of m n 2 right that is the r out r 0 of m n 2 in parallel with r 0 of m p 2 now you know g m r 0 you know all that is why we took so much trouble calculating all this formula the gain can be written as g m times this parallel combination of r 0 ok. So, now we know the gain so now we arrive finally at the two stage op amp ok why do we use two stage op amps it makes it decouples the input from the output ok this stage we have already done in great detail up to now right. So, this stage is optimized to handle the input because it is connected to the input and this stage can be optimized to handle the output output capacitance whatever the load and so on you design it according to the output and then the total gain will be the product of the gain of this and this ok. So, that is why two stage op amps are popular and that is what we are going to use now this one is not a big deal this is that single transistor amplifier except that it is inverted the output of this is connected to the p channel transistor and this n channel transistor is acting as a current source. So, we have already analyzed this also ok we know all the results for this. So, we can just put all those results and the eventual gain is a product of these two gains. So, this is what it looks like you have a differential stage here it has a capital g m which is g m 1 1 and output stage which is g m 2 2 ok. So, this is the second stage and now that is the total output gain this immediately bring the problem what is the problem remember this is a single pole response. So, as you pass the bandwidth the phase will shift by 90 degrees this is also a single pole response and this also around its bandwidth will shift the phase by 90 degrees ok if now both of these are similar circuit similar output resistance similar capacitances and so on. Therefore, these two frequencies are the same more or less as a result around that frequency you will have 90 degree of phase difference here 90 degree of phase difference here you will have an overall phase difference of 180 degrees. Now, in op amp we always use with negative feedback. So, you are using this op amp with negative feedback and if this guy introduces 180 degrees of phase difference that negative feedback will become positive feedback because internally the signal has got phase shifted by 180 degrees you put negative feedback, but because it has got shifted at this frequency by 180 it will be unstable it will start oscillating at that frequency if the gain is higher than 1 if the gain is less than 1 then the feedback will not cause any problem. Therefore, we have to make sure that the overall gain which is dropping with frequency drops to below 1 before the phase reaches 180 degrees and that is not very easy to do if both these poles are at the same point ok why is that so have I left you far behind at what frequency does the phase start changing around the bandwidth right, but at the bandwidth the gain is near its maximum right. So, around the bandwidth the phase has already reached 180 degrees right, but the gain continues to be quite high not the highest possible, but continues to be quite high at that point. So, the overall gain cannot be below 1 before the phase reaches 180. So, we have to do something ok and we do it by reducing on purpose the gain of the first stage if you essentially change the poles of these two so that the pole of the first one is very low and the pole of the second one is very high then because of the gain reduction has already taken place for the first one you can make it such that the gain is below 1 when the phase eventually reaches 180 degrees this is called pole splitting this is what we will do and we will put a capacitor here between the output and the input that is a miller capacitor and that will stabilize the gain and if you notice this was already here without this this will not be very stable. So, this is called op amp compensation and done by pole splitting. So, we put this capacitor here and you can now analyze this this is a miller capacitor it is connected between output and input. So, its effective value is multiplied by the gain of the second stage. So, you can use a small capacitor and it will look like a very large capacitor because of the miller effect. So, this is the equivalent circuit this is the first stage this is the second stage and connected between the output and input of this is this capacitor. So, what is the gain bandwidth product of the total this capacitor the output of this is r and this capacitor has got multiplied by a 2 right. So, what is the gain of this a 1 what is the gain of this a 2 and what is the r c time constant the r 0 of this times c times a 2 because of the miller effect right. So, this is a 1 a 2 divided by r 0 1 a 2 c which is a 1 by r 0 1 c that means the bandwidth is set gain bandwidth product is set by just this amplifier independent of a 2 right essentially what you have done is you have multiplied the capacitor by a 2 right. So, the gain has been killed by the same amount that it has been boosted by the second amplifier right. So, this is occurring in numerator as well as denominator the killing is because of the r c time constant. So, you have boosted the r c time constant by the miller effect you know why the capacitor appears a times in this configuration why is the miller capacitance effectively a times its physical value it should not just be algebra you should actually make your students appreciate this. What really happens is the following what is capacitance capacitance is the ratio of charge to voltage right. So, in order to change the voltage by a little bit how much charge you have to place there right that is what the capacitance is now in this case what happens is that suppose I raise this voltage by some delta V correct what happens to this point it goes minus a times delta V right. So, effectively across this capacitor the voltage changes by a times delta V actually a plus 1 delta V right. So, the amount of charge that you have to provide to it is not no more c times delta V if this guy was a ground then this guy will have to provide a charge which is c times delta V, but now it has to provide in order to change the voltage by delta V it has to provide an amount of charge which is a times c times delta V. Therefore, it appears to it as if a huge capacitor to ground is connected to its output in order to change its voltage by a small delta V it has to dump charge which is a times delta V right that is why the miller capacitance gets multiplied by the gain right this part is clear okay this qualitative appreciation for students is very good because then they get a gut feel of what really is happening here alright. Now, let us do the design final thing what is the slew rate now up to now we have done small signal amplification we have assumed that the bias is there and you put a small fluctuation there, but slew rate is a large signal phenomenon that is you say I apply a step input which is large and I expect the output to go towards the other power supply, but because the current is limited the capacitor can be charged only at a certain rate. So, even though the input is a step the output is a ramp right that is to be expected this is an RC circuit it is an it is a it is an integrator right. So, that ramp will when you integrate a constant you will get a ramp that is not very surprising okay first pole response second pole response it is an integrator right. So, that is the question is what is that ramp rate. So, look at this circuit and see how this capacitor is being charged okay what is the rate of change at this output voltage suppose the input has been given a high voltage. So, that all the current is switched either through Mn1 or through Mn2 right this is the current source and such a high voltage has been applied suddenly here that one of these transistor is completely cut off and all the bias current is flowing through the other transistor it could be through this or it could be through this it does not matter that will just change the direction of the output current okay. So, how much current is being poured in from here whatever is the bias current here right the differential current because all the current is going through one transistor the differential current is the full current the bias current right. So, this bias current all the current will go through one and the other will take zero and as we have worked out the output current is Mn2 minus Mn1 current. So, the full bias current is the output from here right. So, what is the CDV by DT here the effective value of C here is A2 times C right. So, A2 times C times DV by DT that is the bias current right that is the rate of change of voltage at this particular point right. Therefore, DV by DT is I upon A2C A2C but this DV by DT is multiplied by the gain of the second stage. Therefore, the DV by DT at this point is I divided by A2C into A2 right and finally that is just I by C right A2 cancels again from numerator denominator this part is clear this total current is charging a capacitor which is C times A2. Therefore, C times A2 into DV by DT that is the current output of this. Therefore, DV by DT is this I Mn4 divided by A2 by C that is the DV by DT at this point this DV by DT is multiplied by the gain of the stage. So, therefore, I divided by A2C into A2. So, A2 cancels and you get I by C right. So, that is what this is right. So, therefore, the final slew rate of a op-amp is controlled by the bias of the first stage and this compensation capacitor that we have put there. Now, we are ready to design our first op-amp these are our design equations this is just a compilation of what we have derived left to now but one now we must worry about the bias ok. So, this is a slightly delicate argument and I will just go through this the rest is straight forward we will just derive those values ok. So, this let us see very carefully first look at this transistor the drain is connected to gate agreed this is like Arjun look at the eye of the bird and do not look at any of anything else then you will be able to concentrate. So, look only at MP1 the drain is shorted with gate ok what is the saturation condition that the drain voltage is larger than Vg-Vt right but because it is equal to Vg it is always larger than Vg-Vt right the drain voltage is the same as Vg. Therefore, the drain voltage is always larger than Vg-Vt therefore, this transistor is always saturated ok. So, this is the ideal we want all transistors saturated. So, we want every transistor to emulate this ok. So, I do not know how many of you are elder brothers or elder sisters of the family I am. So, you have that extra responsibility of being the Badawai then everybody says why are you doing such a thing your siblings will also do that. So, you have to be a good boy all the time. So, this is our good boy MP1 is our good boy it is always saturated we want others to be to follow him ok alright now look at MP2 again concentrate only on MP2 now we want MP2 to be like MP1 then this will also be saturated ok. Now, compare MP2 and MP1 their source voltages are the same check their gate voltages are the same check and their currents are the same check and these transistors are identical right and what have we said that if current is the same the geometry is the same and the gate voltage is the same then the drain voltage must be the same otherwise how will they have equal current. Therefore, this voltage is the same as this voltage this is the first argument this is a series of delicate arguments you must establish each one in the minds of your students and only then go ahead ok. So, what have you established that this voltage is equal to this voltage everybody agrees with this therefore, MP2 is automatically saturation no problem there the problem is MP3 ok. So, now again concentrate on MP3 alone MP1 MP2 we have taken care of concentrate on MP3 alone the source voltage is same as MP1 the gate voltage is equal to this voltage which is equal to this voltage which is this gate voltage. Therefore, the gate voltage is also the same this transistor the gate voltage is this drain voltage which is equal to this drain voltage which is the gate voltage of both correct. So, therefore, this transistor has the same source voltage and the same gate voltage as these two transistors. Therefore, if it is drain voltage is also the same, then this will also be guaranteed to be saturation, in saturation, but in this case the current is not the same. So, we cannot give that argument. Therefore, what we say is that if the geometry ratio of this with respect to these two is the same as the current ratio, so in short, let us say that the current ratio is 5 is to 1. That means, this transistor draws 5 times as much current and is 5 times as wide, then I can consider m p 3 to be a parallel connection of 5 transistors, agreed? Then each transistor, each component transistor also has the same current as this, because there are 5 of those, now that argument applies, source voltage is same, gate voltage is same and current is the same. Therefore, the drain voltage must be the same. So, if I ensure that the geometry ratio between m p 3 and m p 2 is the same as the current ratio between m p 3 and m p 2, then I will guarantee that m p 3 is saturated. If this argument clear, it is a two-step argument, therefore you must appropriately build it up in the class. So, what are we saying? Just to go quickly over it again, this transistor is always saturated argument number 1. Argument number 2, these two transistors have the same source voltage, the same gate voltage and the same current, therefore the drain voltages must be the same. So, this voltage is the same as this voltage, therefore this is also saturated. So, even though there is no short here, there is a what should short between these two. Argument number 3, this transistor has the same source voltage as this, it has the same gate voltage as this, because this voltage is the same as this voltage, which is the gate voltage and the geometry ratio is the same as current ratio, therefore its drain voltage must also be the same. So, if you can ensure that the geometry of this is in the same ratio as the bias current of the two stages, then you will have all transistor saturated, which is what we want to do to get high gain. Now, we can design this. Let us take an actual number tutorial that puts everything in your head like nobody's business. So, let us take k prime in n channel to be 120 micro ohms per world square. This is not unusual by the way for a 0.35 micro ohm technology, half micro ohm, not a very modern technology. So, this is not a very bad number to take. So, let us say that k prime n is 120 micro ohms per world square. Let us take k prime p to be half as much. This we discussed yesterday also, you very often take the p channel mobility to be half that of n channel mobility. Let us take it as 60. These are just numbers, you could have chosen other numbers. This is just to illustrate. I am just simply saying that these numbers are reasonable of actual technologies. Take the 2 VTMs to be plus minus 0.4, though that we will not be using at all. We want to design an op amp whose DC gain is 80 dB, whose gain bandwidth product is 50 megahertz and whose slew rate is 20 volts per micro ohm. These are the specifications given to us. Let us go ahead and now design it. Now, the order is very important and what you do is that you design based on those specifications which involve the least number of specifications. So, that the specifications do not come out by simultaneous equations. You can directly nail something. So, that is what we are going to do. First, this is an arbitrary choice and we may have to iterate over it if it does not work out. You choose the value of this capacitor, the compensation capacitor and we have taken a value of 2PF here which is quite representative. If things do not work out, you may have to try various values of this capacitor and later sometime we will discuss how to choose this capacitor. But right now let us take a value 2PF. Also, we assume that the bias current in the second stage is 5 times this current. That means 10 times this. There is an order of magnitude of difference between the bias current of this and bias current of this, single transistor. Because this is 2 times, therefore 5 times between these. This is also fairly standard. But this is what I meant by a 2 stage op-amp. Essentially, the output drives a healthy load. So, it needs a healthy current. So, the current through this is one order of magnitude higher. This is an assumption that we have made. If you do not meet specs, we will come back and revise this. First, from the slew rate. How much is the slew rate? I by C. We just worked that out. Depends only on the first stage because the gain of the second stage got cancelled out. So, that is this bias current divided by C. That should be the slew rate. Slew rate is given to us. What is slew rate? 20 volts per microsecond. This is 20 volts per microsecond. This is the slew rate. And this is the capacitance 2PF. So, C dv by dt that directly gives us 40 microns. That means this transistor should take 40 microns. This is clear enough? So, we have already put the current through this transistor to be 40 microns. Now, in DC case, these two currents must be equal. So, there is 20 microns through this, 20 microns through this. And because these are in series, there is 20 microns through this and 20 microns through this. Because this guy draws 10 times the current, there is 200 microns through this. And because it is in series, there is 200 microns through this. You got it? At this point, we know the current through every single transistor. In this consideration, we know the current through every single transistor. This is 40, 2020, 2020, 200, 200. This part is clear? Then I will proceed. Now, the gain bandwidth also is determined by this. We have seen that the gain of the second stage drops out, gain bandwidth. In fact, gain bandwidth and slew rate are the small signal and high signal, large signal components of the same characteristic. So, the loading by C, it is GM by C. So, the effective C is multiplied by A2 because of the Miller effect. And the overall gain is also multiplied by A2. So, therefore, the effective gain bandwidth product of the whole op-amp is the same as the gain bandwidth product for this taking C rather than the Miller capacitor. So, GM by C is given, gain bandwidth product. But C is also given, therefore GM is given. So, that is what we calculate. From the gain bandwidth requirement, what are the GBW? 50 MHz. So, corresponding value of omega is 2 pi into 50 into 10 to the power 6. And that is GM by C. So, that is the GM of MN2. We know that the differential GM is the same as the differential of the single transistor. We had established that. So, that is GM of MN2 divided by C, which is 2PF. Correct? Now, this gives us the GM. Right? So, how much is GM? 628 micro Siemens. Okay? So, you know the GM of this. Okay? These two are identical. Therefore, their GMs must be the same. Their currents and everything must be the same. Now, to get a GM of 628 micro Siemens, GM, this is one of those equations that we had derived. Right? So, that is 2K prime into W by L into ID. Right? That is what we have derived. 2K into ID square root. Right? In this case, we have current bias. Therefore, this is the expression that we have used, which depends on ID. Right? So, 2K prime is K times W by L into ID, which we have already calculated 20 microns. Right? This should be equal to 628 micro Siemens, which we just derived. So, the only unknown here is W by L, which you can calculate comes out about 82. Okay? So, now I know the W by L of this, which is 82. W by L of this is also 82. We know the current through this. Right? And we know the early voltages. Now, as you know, G0 was that current by voltage. Right? So, if you know the current, how much is the current? 20 microns. And the early voltage is given to be 20 volts. Right? So, the output resistance of each one of these. Right? The G0 is 1 micromo, 1 micro Siemens. Right? 20 microns divided by 20 volts straight forward. And we know that the effective load is the load of this and this in output resistance of this and this in parallel. Correct? So, the RL is 2 micro Siemens. Right? So, the gain of the first stage is now known. You know the GM. You know RL. GM times RL. Right? So, GM is how much? 628. GM by G0. Correct? This is the first thing that we derived. GM by G0. So, GM is 628 micromo. The G0 is 2 micromo. Correct? So, the effective gain of this stage of the first stage will be about 300 here. Right? So, the overall gain. Right? What is the G0 of this? 10 times because it has 10 times the current. Right? So, G0 of this is 20 micromo. Correct? So, therefore the gain of this first stage is 628 by 2. Gain of the second stage is GM divided by G0 and G0 is 20 micromo. Right? And this is the total DC gain which must be 10000. Agreed? So, this is the only unknown GM. So, now I know the GM of MP3. Okay? What is the GM of MP3? Come out about 637 micro Siemens. Quick repetition. Overall gain is the product of the gains of the two stages because we know current through all the transistors and we know the early voltage, we know the R0 of every transistor. G0 of every transistor. Right? We know the GM of this transistor. We know the gain of the first stage is GM 628 micro. GM came from gain bandwidth product. Okay? So, 628 divided by 2, this is the gain of the first stage and GM divided by 20 micromo. Each one of these transistors has 10 micromo as the G0. Right? So, this GM divided by 20 micromo. That should give me 10000. Therefore, this should be about 637 micromo. Okay? This part is clear. Now, I know the GM of this transistor. Now, you know, if you know GM and you know I, then you can calculate the geometry. Right? So, that is what we do next. So, to get a GM of 637 micromo with a drain current of 200 micromo, then 637 micromo is equal to 2 into KT prime. This is a P-channel transistor. Right? So, 60 micro ohms per volt square times W by L times 200. Right? That is the current which is flowing through this. 200 micro ohms. Right? 210 minus 6. That gives you the W by L of about 17. Okay? So, now I know the W by L of this. But we promised that the W by L ratio of this and this, these will be the same as the current ratio. Therefore, each one of these transistors should be 1 tenth the width of this. Right? The current is 120. Therefore, W by L also should be 1 tenth. So, therefore, the W by L of this is 1.7 and W by L of this is 1.7. Okay? At this stage, we know the bias currents through both the stages. We know the geometry and current of this, geometry and current of this, geometry and current of this, geometry and current of this, geometry and current of this. as designers what is our final job to find the bias and to find the w by l then you design the transistor now we know the w by l now this bias this bias generation madam should drive will be doing later with you but this bias assume that there is a reference transistor of w by l 4 which they these are mirroring and which carries 10 micro m's just for the sake of calculating so if that is so we assume that in n type reference bias transistor of w by l equal to 4 is available with a current of 10 micro m's okay and these are mirroring the current for this okay so this guy will then have to be what size this is 40 micro m's right 20 plus 20 so 4 times the size therefore its w by l will be 16 right a w by l of 4 gives you 10 micro m's therefore a w of w by l of 16 will give you the required 40 micro m's correct and similarly this has to be 160 sorry 80 it is 5 times the current of this 10 times of this right so this this is 16 this is 80 at this stage we have calculated everything okay finally what is the gain gain is a product of 2 GMR zeros right therefore very often people say why bother with a two-stage op-amp why not just simply use a cascode the cascode gain was also the product of 2 GMR zeros okay but to make it differential then people very often make a differential cascode which looks like this okay we will not get into the detail of this design very similarly but we will not get into the details of this okay so now you know how to design now during the lab tomorrow we will take the same design okay now notice that we have made very bold approximations we have said G zero is directly proportional everything is linear these equations apply these equations apply to a point three five microns such very simple equations they apply okay so the real design will deviate quite a bit from that okay so really then you will have to fine tune but it will give us a very good initial design from which most of the specs have already been met and then the job of the designer is to fine tune fine tune tweak tweak the currents tweak the geometries till you get the response that you want okay so that is what we will do next will stop here there is one final point that I want to make and that is this in op-amp design we have assumed that this stability depends on the value of this capacitor right and what is the capacitor value the physical value multiplied by the gain of the second stage okay now we have multiplied it by what by the DC gain of the second stage in reality this game will stop dropping as a result this capacitor will look like a large capacitor at DC that will look like a smaller and smaller capacitor at higher frequencies therefore you may often find that this capacitor is inadequate to make your op-amp very stable so after you have done this paper design very often you may have to go and fiddle after all the value of this capacitor was an arbitrary decision that we took right in the beginning so after you have done the design you may have to go and tweak the value of this capacitor till you get the stability that you want