 Running five instructions through the pipeline concurrently, however, is not without its risks. So now we're going to look at some of the hazards that can arise in the five-stage pipeline and how we can ameliorate those. We're going to look at three different types of hazards, structural hazards, data hazards, and control hazards. We'll begin with structural hazards because those will be the easiest. Structural hazard is really just some contention for hardware. We have a couple of instructions that want to use the same piece of hardware at the same time, but there's only one piece of hardware, so only one instruction can use this hardware. If two instructions try to use it at the same time, they're going to end up providing that piece of hardware with mixed data, and it's going to produce garbage for its results. So we need to avoid this situation, and fortunately in the MIPS architecture, we just won't have to worry about that. Our pipeline has been designed in such a way that we won't ever be trying to use the same piece of hardware at the same time. The one case where that might not be so obvious is with the registers, where we might be trying to write something to a register in the same cycle, we're actually trying to read something from them. But if you remember how we built our memory structures, you can realize that we can only provide new data to a D latch when the clock signal is high. So in the second half of our clock cycle, when the clock signal is low, then we get that data back out. We can't write anything new in, but we can pull new data out. As a result, we'll only actually write to our registers in the first half of the clock cycle. In the second half of the clock cycle, we'll pull data out. So we won't actually have any hardware contention there. For the other pipeline stages, our hardware is set up in such a way that each instruction gets to access one piece of hardware, and that instruction will be the only instruction accessing that piece of hardware in that clock cycle. In the next clock cycle, one instruction moves on to a different piece of hardware, and a new instruction moves in to use the piece that was just vacated.