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Published on Mar 27, 2011
This is demo of a Jupiter ACE clone I've synthetized for a Spartan 3E-250 FPGA device, present in a cheap board, the OLS. This is an excercise to learn Verilog, and this is my first "serious" work with this HDL. The composite video is generated off board, by analog adding the composite sync and pixel signal outputted by the FPGA into one composite video signal, which I've recorded using a Windows USB capture device and DScaler. All you see here is the real thing, not a software emulator output capture.