 Hello, Myself, Giridhar Jain, Assistant Professor in Electronics and Communication Engineering, DoubleIT, Sholakur. Now, today I am going to take lecture on CMOS logic. Now, learning outcome of this session are at the end of this session, students will be able to explain CMOS logic, design logic gates using CMOS logic. Beginnings of this session are what is CMOS logic, MOSFET as a switches, AND logic and OR logic, CMOS inverter, CMOS NAND and NOR logic. Now, first we understand what is the AND logic and OR logic. Now, in CMOS design we make use of PMOS and NMOS. When the MOSFETs are connected in series, it is equivalent to the AND logic, means MOSFET is used as a switches in CMOS logic design. So, when switches are connected in series, it is equivalent to the AND logic. Similarly, when MOSFETs are connected in parallel, means MOSFET as a switches are connected in parallel, it is equivalent to the OR logic. Now, let us understand what is the CMOS logic. Now, CMOS logic consists of pull-up network and pull-down network as shown in the figure. Pull-up network is made up of PMOS only and pull-down network consists of NMOS only. Switches are applied to the gate of PMOS of pull-up network and gate of NMOS of pull-down network simultaneously. Pull-up network is connected to the VDD and pull-down network is connected to the ground. Output depends on the input as per the truth table of the circuit design. Now, specialty of pull-up network and pull-down network is that pull-up network and pull-down network are duals of each other, means for particular combination of input or for any combination of input, at any time only pull-up network or pull-down network will conduct. Now, let us design a CMOS inverter using CMOS logic. So, CMOS inverter is as shown in the figure, it consists of one PMOS and one NMOS. So, one PMOS will act as a pull-up network and one NMOS will act as a pull-down network. Input is A and output is complement of A that is A bar. Now, when input A is equal to 0, PMOS will conduct and NMOS is cut-off that is it is equivalent to the open circuit as shown in the figure. Therefore, output is connected to the VDD that is output is equal to logic 1. If input is made 0, PMOS will conduct and when input is 1, PMOS will not conduct. Now, let us design CMOS NAND gate, two input NAND gate. So, for two input NAND gate input is A and B and the output is Y. So, Y is given by AB bar by using De Morgan's theorem AB bar is equal to A bar plus B bar. Now, we are interested in designing these two input NAND gate. So, while designing this Boolean expression that is Y equal to A bar plus B bar. So, Y is equal to A bar plus B bar so that plus indicates it is a OR operation. Now, whatever is the Boolean expression it is implemented in pull-up network and pull-down network is dual of pull-up network. So, Y is equal to A bar plus B bar is implemented in pull-up network. So, A bar plus B bar means two PMOS are connected in parallel in pull-up network as shown in figure and the dual of pull-up network is a pull-down network which consists of two NMOS connected in series because two PMOS are connected in parallel for pull-up network. So, dual of that is instead of PMOS we make use of NMOS connected in series as shown in figure. Now, let us analyze or check the circuit for different combinations of input. If A and B both are 0 then both the PMOS are on means they act as a closed switch and at the same time two NMOS of the pull-down network are off means they are equivalent to open switch. Therefore, output is connected to the VDD therefore output is logic 1. Now, let us check this NAND gate for another combination A equal to 0 and B is equal to 1. So, as figure shows A equal to 0 means left side PMOS will conduct and NMOS 1 NMOS is cut off and B is equal to 1 means 1 NMOS is on and 1 PMOS is off. Therefore, output is connected to the VDD so output is logic 1. Now, if both input A and B are 1 then both the PMOS are cut off both the NMOS are in on state therefore output is connected to the ground through pull-down network therefore output is 0. Now, design two input NOR gate. Now, what is NOR gate? Y is equal to A plus B bracket close complement of that. So, using De Morgan's theorem it is equal to A bar B bar. Therefore, Y is equal to A bar B bar is nothing but analogic means 2 PMOS should be connected in series and the dual of pull-up network is pull-down network which is 2 NMOS should be connected in parallel. So, here if you look at the figure 2 PMOS are connected in series which is pull-up network and the 2 NMOS are connected in parallel that is a pull-down network. So, this is 2 input NOR gate. Now, for example if you are asked to design a 3 input NOR gate how this circuit can be modified. Now, instead of 2 MOSFET there will be 3 PMOS connected in series for pull-up network and for pull-down network there will be 3 NMOS connected in parallel. So, in this way we can design or implement any Boolean expression using CMOS logic. So, today we have learned what is CMOS logic, how to use MOSFET as a switches, design of CMOS inverter, design of 2 input NAND gate and 2 input NOR gate. These are references. Thank you.