 Hello, and welcome to this presentation of the STM32 General Purpose I.O. interface. It covers the general purpose input and output interface and how it allows connectivity to the environment around the microcontroller. General Purpose I.O. pins of STM32 microcontrollers provide an interface with the external environment. This configurable interface is used by the MCU and also all other embedded peripherals to interface with both digital and analog signals. Application benefits include a wide range of supported I.O. supply voltages as well as the ability to externally wake up the MCU from low power modes. This table shows the differences with the STM32F0 microcontroller. When STM32G0 microcontrollers are in reset state, most of the I.O. ports are configured in analog mode to minimize energy consumption. The Cortex M0 Plus Core has direct access to the GPIO registers through the single cycle I.O. port bus. This provides a low-latency direct path to change the state of outputs or to read the state of inputs. The pull-up or pull-down resistors independently configured for any I.O. pin may remain active while entering a low power mode. It is configured in the PWR module. General Purpose I.O.s provide bidirectional operation, input and output with an independent configuration for each I.O. pin. They are shared across up to five ports named GPIOA to GPIOD and GPIOF. Each of them hosts up to 16 I.O. pins. I.O. ports support atomic bit set and reset operations through BSRR and BRR registers. I.O. ports are directly connected to the single cycle I.O. port bus. This allows fast I.O. pin operations, e.g., toggling of the pin every two clock cycles. No conflict with the DMA can occur because this Cortex M0 Plus port is private to the CPU. Most of the I.O. pins are 5V tolerant when supplied from VDD I.O. X above 1.6V. General Purpose I.O. pins can be configured into several operating modes. An I.O. pin can be configured in an input mode with floating input, input mode with an internal pull-up or pull-down resistor, or as an analog input. An I.O. pin could be also configured in an output mode with a push-pull output, or an open-drain output with an internal pull-up or pull-down resistor. For each I.O. pin, the slew rate speed can be selected from four ranges to ensure the best compromise between maximum speed and emissions from the I.O. switching and to adjust the application's EMI performance. I.O. pins are also used by other integrated peripherals to interface with the external environment. Alternate function registers are used to select the configuration for the peripherals in this case. The configuration of the I.O. ports can be locked to increase application robustness. Since the configuration is locked by applying the correct write sequence to the lock register, the I.O. pin's configuration cannot be modified until the next reset. Several integrated peripherals, such as the USART, Timers, SPI, and others, share the same I.O. pins in order to interface with the external environment. Peripherals are configured through an alternate function multiplexer, which ensures that only one peripheral is connected to the I.O. pin at a single time. Of course, this selection can be changed during runtime of the application through the GPIO XAFRL and AFRH registers. The configuration of any I.O. pin is achieved through three registers GPIO X MODE R or MODE register GPIO X O type R or output type register and GPIO X PU PDR or pull-up pull-down register. Register GPIO X MODE R selects the functionality of the I.O. pin, digital input, digital output, digital alternate function, or analog. Register GPIO O type R is relevant when the pin is in output. It selects open drain versus push-pull operation. Register GPIO X PU PDR is relevant when the pin is not configured in analog mode. It enables, disables, pull-up, and pull-down resistors. The two pins PA9 and PA10 can remap the two GPIOs PA11 and PA12 respectively in order to give access to their functions when the pins are not natively available on the package. With the remapping, alternate functions related to pins PA9 and PA10 are available. Note that this remapping also applies when the package supports pins PA9 and PA10 as independent pins. During and after reset, the alternate functions are not active. Only debug pins can be used in alternate function mode. Pin PA14 is shared with boot zero functionality. Caution is required as the debugging device can manipulate the boot zero pin value, which selects the boot mode. When the external oscillator is switched off, pins related to this oscillator can be used as standard I.O. pins. This is the default state after a device reset. When the external clock source is used instead of a crystal oscillator, only the related OSCI in-pin is used for the clock, and the OSC out-pin can be used as a standard I.O. pin. A new multi-supply scheme of I.O. pins brings new I.O. pin structures. Previously used naming FT for 5 volt tolerant and TT for 3 volt tolerant has been extended by abbreviation suffixes to highlight alternate supply source for each FT and TT I.O. pin. Previously used name FTF for FM plus capable pins has been transformed to FT underscore F. Suffix underscore A marks pins supplied by analog supply. Suffix underscore C is used for pins supporting USB type C power delivery. The absolute maximum rating for each I.O. pin is defined by the lowest voltage of the supplies listed for each I.O. pin. I.O. pins remain active in all modes except standby and shutdown, where the only available configuration is input with internal pull-up, pull-down resistor, or floating input. When exiting shutdown mode, the I.O. configuration is lost. When the MCU is under reset, I.O. pins are forced into an analog input mode. VBAT domain GPIOs, PC13, PC14, and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current of 3 milliamps, the use of GPIOs PC13 to PC15 in output mode is limited. The speed should not exceed 2 MHz with a maximum load of 30 picofarad. These GPIOs must not be used as current sources, for example, to drive an LED.