 Hello, Myself Sunil Kalshatti, Assistant Professor, Department of Electronics Engineering, Valchand Institute of Technology, Sholampur. Today, I am going to explain the gate turn-off thyristor from Industrial Electronics Learning Outcome. At the end of this session, students can describe the construction, working and characteristics of gate turn-off thyristor. Up till now, we studied the thyristor, thyristor is the latching device, thyristor is extensively used in high-power applications. It always suffered from being a semi-controlled device. Thyristor switched on by applying a gate signal. It has to be turned off by interrupting the main current using a commutation circuit. To turn off the thyristor, it requires the special commutation circuit. A Valchand expensive commutation circuit had to be used to ensure the proper turning off of the thyristor. The switching speed of the device was also comparatively slow, even with fast switching thyristor. Hence, the development of gate turn-off thyristor addresses the major problem of the thyristor by ensuring the turn-off mechanism through the gate terminal. It incorporates the best features of conventional thyristor and high-voltage switching transistor. It is also called as a latching thyristor. GTO is the current control device. The ratings are available in the market up to 4000 volt and 3000 ampere. So, for such type of GTO, it requires the gate current one-fourth to one-fifth of this ampere. The turn-on time of the GTO is 2 to 4 microseconds and turn-off time is the 2 microseconds. It is less than thyristor. GTO is a three-terminal PNPN device that can be turned on like an ordinary SCR by positive gate current pulse and can be turned off by the negative gate current pulse. No forced-out of commutation circuit is needed for the GTO. Hence, power circuits using GTO are compact and cheap. GTO has higher switching speed than thyristor. Therefore, switching losses are more. Schematic symbols of GTO. These are the schematic symbols. In the first symbol, the arrow represents that the inward arrow indicates that to turn on the GTO, it requires the positive IG and the outward arrow indicates that to turn off the GTO, it requires the negative gate current. When gate pulse is applied, this gate pulse acts as an IB2 and because of this IB2, the IC2 is equal to beta times beta 2 times IB2 and this IC2 acts as a base current of the Q1. So, the effect of this IC1 is equal to beta 1 beta 2 times IC2 acts as a new base current of the Q2. So, because of this regenerative action, the device conducts and latched into the conduction state. And further, if we remove the IG, it remains in the conducting state. That's why the GTO is also called as a latching device. Current Distribution During Turnoff To turn off the GTO, it requires the negative IG. Means, divert the collector current of PNP transistor away from the Q2. So, effect of this, the collector current of Q2 reduces, so indirectly the base current of PNP is reduces, the collector current of PNP is also reduces. So, effect of this, the GTO turns off. During such turnoff, negative IG causes current crowning or current pinching at the center of cathode junction, which not only slow down the turnoff process, but can lead to device failure because of second breakdown. Current crowning is reduced by the reduction in current gain of PNP transistor. This is the schematic construction of ordinary ACR. This is the four-layer PNPN device, anode is connected to the P region and cathode is connected to the N region and the gate is connected to the P region. This is the schematic cross-section of the GTO. This structure is also called as a interdigited gate cathode structure. As compared with previous one, here N regions are diffused in the anode section and heavy lead-up to N regions are diffused in the cathode section. When we apply the negative IG, the GTO turns off, but there is the possibility of current crowning. To reduce the current crowning and avoid the second breakdown, it is essential to reduce the gain of the PNP transistor. The gain of the PNP transistor can be reduced by using the diffusion of gold. The gold-plated GTO retains its reverse blocking capability, but has high onset drop. That's why this methodology is never used. By introducing anode to N-base short-circuiting spots, due to this onset drop reduces, it loses its ability to block the reverse voltage, but turn off process is fast. Therefore, again this methodology is not used, because in this methodology, the device loses its ability to block the reverse voltage. The third method is very popular, interdigited gate cathode structure. Generally in the large GTO, the interdigited gate cathode structure is used. In this structure, the emitter consists of many parallel N-type fingers diffused into the P-type gate region. Here N-type fingers are diffused in the P region. Due to interdigited gate cathode distance between the gate and cathode erudices, emitter with erudices effect of this turn off time erudices. It helps to minimize the current crowding at the center and increases safe operating area. This configuration ensures simultaneous turn on and turn off of GTO. How to reduce the current crowding in the GTO? By using the interdigited gate cathode structure, the distance between the cathode and gate erudices, so stored charge carries are swept out with faster rate, so it reduces the possibility of current crowding. Fine, holding and latching current of GTO are considerably higher compared to the similarly rated thyristor. By using interdigited gate cathode structure and by anode short-circuiting spots, the holding current and latching current of GTO are considerably higher compared to the similarly rated thyristor. So, GTO Vi-character 6, as long as input is less than forward breaker voltage, the GTO remits off. When we apply the gate pulse, the forward breaker voltage erudices and device gets latched into the conducting state. By increasing the IC, the forward breaker voltage is erudices. And when we apply the reverse voltage, the device remains in the reverse blocking state. Whenever the reverse voltage crosses the one particular limit, VPRR, the device enters in the reverse breakdown region and there is a possibility of damaging the device. That is why generally this is avoided. GTO gate characteristics, it shows the relation between the gate voltage and the gate current. When the gate voltage is minimum, gate current is minimum and when gate voltage is maximum, gate current is maximum. These are references. Thank you.