 Hello, and welcome to this presentation of the STM32 Serial Audio Interface, or SAI. It covers all the features of this interface, which is widely used to connect external audio devices. The SAI, integrated inside STM32 products, provides an interface allowing the microcontroller to communicate with external audio devices, such as amplifiers, ADCs, DACs, or audio processors. This interface is fully configurable and supports most audio standards, allowing easy connection to existing audio devices. Thanks to internal synchronization features, the number of IO pins is reduced to its minimum. The SAI can be programmed into four different modes. The free protocol mode access to the adjustment of several parameters, allowing the SAI to support standards such as I2S, PCM, TDM, etc. Thanks to its flexibility, it is possible to customize the serial interface if needed. The SPDIF protocol mode allows the SAI to transmit audio samples using the IEC 6958 standard. The PDM interface mode allows the SAI to connect up to six digital microphones for beamforming, or simple speech capture applications. This mode is only supported by SAI1, the AC97 protocol. The SAI supports all the usual audio sampling rates, according to the crystal frequency used for the application. The mode field of the SAI configuration register configures the subblock in master or slave mode, and in transmitter or receiver mode. Each subblock controls a unidirectional data link. The two subblocks of the same SAI unit can be associated to control a full duplex link. It is also possible to synchronize several SAI interfaces together. Companding algorithms are implemented in the SAI to reduce the dynamic range of audio signals. The SAI also provides a FIFO buffer of eight samples and up to two interrupts and DMA interfaces. The SAI is composed of two independent subblocks, subblock A and B. Each subblock has its own APB interface, clock generator, FIFO buffer, DMA interface, and interrupt interface. Each subblock can be configured in receiver or transmitter mode and in master or slave mode with its own protocol. Internal synchronization allows two subblocks to be synchronized. For each subblock, FS is the frame synchronization, SCK is the bit clock, SD is the serial data, and MCLK is the master clock. In addition, a PDM interface allows the connection of up to six digital microphones. The STM32L5 embeds two SAI instances, SAI1 and SAI2. SAIX can receive a kernel clock from each PLL, from HSI-16 oscillators, from an input pad SAIX-EX-TCLK. The kernel clock is used by the SAI in order to generate the timing of the serial audio interface when configured in master mode. The free protocol mode makes it possible to emulate most of the common audio standard interfaces thanks to the flexibility of changing the behavior of several parameters such as data justification, data size and position, frame size, frame period, frame polarity, sampling edge for the clock, number of slots. The following example shows some of the possibilities of the interface for the I2S-like protocols. In an I2S-like protocol, each edge of the frame synchronization FS is used to align the slot positions. The frame length, the duty cycle and polarity can be adjusted. The clock data strobe edge can be selected as well. The position of the slots with respect to the frame edges can be selected. The size of the slots can be also adjusted. There must be an even number of slots per frame in I2S-like protocols. The following example shows some of the possibilities of the interface for the TDM-like protocols. In a TDM-like protocol, only one edge of the frame synchronization, rising or falling, is used to align the slots position. The frame length, the duty cycle and polarity can be adjusted. The clock data strobe edge can be selected. The position of the slots with respect to the frame active edge can be selected. The size of the slots can be also adjusted. The number of slots per frame, up to 16. The SAI is able to handle up to 16 slots and each slot can be individually activated or not. The inactive slots can be set in high impedance. The slot size is always larger than or equal to the data size. The SAI allows to control the position of the data inside each slot and to set the unused parts of the slots to high impedance if needed. This function can be helpful when the data line is shared between several devices. In master mode, the SAI can generate the master clock MCLK depending on the audio system configuration. This master clock provides a reference clock to the external audio codecs. In master mode, the SAI generates the frame synchronization signal FS and the bit clock SCK. The data line SD can be either input or output. In slave mode, the MCLK signal is generally not used but can be generated if needed thanks to MCK EN bit. In slave mode, the SAI receives the frame synchronization signal FS and the bit clock SCK from another device, external or internal. The data line SD can be either input or output. In master mode, it is up to the SAI to generate the appropriate timings to provide the correct sampling rate. In slave mode, the sampling rate is provided by the external audio device. Note that it is possible to generate a master clock to an external device even when the SAI is not enabled. This feature can, for example, provide a clock to an external codec during the configuration phase. The clock generator is needed for master mode communications. It is used to adjust the sampling rate of the serial audio interface. The clock generator provides the root frequency for the MCLK, SCK and FS. When no div equals zero, the frame length must be a power of two and the ratio between the FS frequency and the MCLK frequency is set to 256 or 512 according to the OSR bit. The SAI XCURCK is provided by the RCC block. The master clock is generated as soon as the MCKEN bit is set to one, even if the SAI is not enabled. When no div equals one, the frame length can take any value from 8 to 256. In this case, the frequency of the SCK bit clock is directly given by the clock received on SAI CK input, divided by the MCK div value. The internal synchronization can be used for communications needing two data lanes, such as full duplex, I2S. All the sub-blocks synchronized together must use the same protocol characteristics. One of the sub-blocks can be configured in master mode, while the other is in slave mode, or it is possible to configure both sub-blocks in slave mode if the master device is external. In order to reduce the data size, it is possible to insert an ALaw or micro-law compander in the data path. Note that ALaw and micro-law are not lossless compressors. Companding modes are generally used in telephony. The small values are amplified, and the big values are attenuated. The SNR tends to be identical for strong and for weak signals. The SAI also provides a mute function. In transmit mode, the user can choose to send zeros on muted slots, or the previously transmitted value. The previously transmitted value is limited to configurations having one or two slots per frame. Note that in transmit mode, the TX5O pointer is still incremented, meaning that data which was present in the FIFO and for which the mute mode is requested is discarded. The receive mute mode can be helpful to detect a number of consecutive slots having all data reset to zero. The anticipated or late-frame error detection function increases the interface's reliability by detecting unexpected frame synchronization misalignment. The status flag is set, and an interrupt request can be generated as well. The application software will have to restart the SAI interface. When an overrun condition occurs, the OVR-UDR flag is set in the SAI status register. This flag is cleared when the software sets the COV-RUDR bit in the SAI clear flag register. The SAI guarantees data alignment even if an underrun or an overrun occurs. The SAI supports the audio IEC 6958 standard in transmit mode when configured for the SPDIF protocol. The SAI generates the preambles and the parity bit P according to the transmitted data. The software has to handle the CS, U, and V bits. In the IEC 6958 specifications, the block structure is used to decode the channel status and user information. Each block contains 192 frames. Each frame contains two subframes. The SAI automatically generates the BM and W preambles. Preamble B detects the start of new block and the start of a channel A. Preamble M detects the start of a channel A when it is not a block boundary. Preamble W detects the start of a channel B. Each subframe contains 32 bits divided into three fields. A synchronization preamble allowing the detection of the block and subframe boundaries. A payload of 24 bits. Status bits V, U, CS, and P. The FSA ICK frequency must be adjusted in order to generate the proper audio sample rate FS. The data inside the transmit FIFO must be aligned as shown in this slide. The most significant bit of the data must always be at position 23. The pulse density modulation or PDM interface is provided in order to support digital microphones. The PDM interface remaps the bitstream received from the digital microphones into TDM frames. The PDM interface waits for the reception of 8 bits from each microphone before sending a new TDM frame. In addition, the PDM interface offers an 8-bit delay line for each microphone stream. These delay lines are working with the resolution of the bitstream clock provided to the microphones. It enables beam-forming applications and removes constraints on microphone placements. When the PDM interface is enabled, the serial interface of the subblock A cannot be used to connect an external device. This serial interface is connected internally to the PDM interface and the subblock A must be configured in TDM modes as an RX master. The figure shows an example of connection of four digital microphones. Note that each data line, D1, D2, or D3, can be connected to one or two digital microphones. The subblock B is still available for other applications and can be used to connect an external device using TDM, PCM, I2S, or any other supported protocol. With this PDM interface, the bit clock frequency has to be adjusted according to the sampling frequency and the number of microphones. The frame length is also adjusted according to the number of connected microphones. The SAI is able to work as an AC97 link controller. When this protocol is used, the frame length, the slot number, and slot length are set by the hardware. Several events can be enabled in order to generate interrupts. The wrong clock configuration or WCKCFG event can be used in order to inform the user that the frame length of the SAI has been improperly programmed. This feature is relevant only in master mode. This table shows an overview of the SAI activity for the various possible power modes. The SAI is active in run and sleep modes and frozen in all stop modes. The SAI must be reinitialized after exiting standby or shutdown mode. The SAI needs the bus interface clock, APB, and the kernel clock, SAICKX, to work properly. For a full duplex master mode, two data lanes are needed, so two subblocks need to be used. The master subblock A provides the synchronization to the slave subblock B, using the internal synchronization feature. Note that in this example, the subblock B only uses the SDB. The number of IOs is reduced to its minimum thanks to the internal synchronization. This is another kind of full duplex mode, using the TDM protocol. Slot 0 is active for subblocks A and B. Slot 1 is inactive for subblock A, and slots 2 and 3 are inactive for subblock B. For both subblocks, the frame structure has four slots. Subblock A will generate three samples per frame. Subblock B will receive two samples per frame. This example shows the most important SAI settings in order to capture the samples provided by four digital microphones. In typical applications, the microphones receive a bit stream clock frequency 64 times higher than the wanted audio rate. If the application needs to handle a 16 kHz audio stream, then the bit stream clock provided to the digital microphones must be 16 kHz multiplied by 64, which corresponds to a clock frequency of 1.024 MHz. As there are four data streams, the bit clock, SCKA, must be four times higher than the bit stream clock provided to the microphones, which results in a bit clock frequency of 4.096 MHz. Using this configuration, the SAIA writes into its RX-FEFO and 8-bit data every time a slot is received. In order to reconstruct the 16 kHz audio signal, software has to perform a low-pass filtering of each microphone stream, followed by a decimation by 64. This is a list of peripherals related to the SAI module. Please refer to these peripheral trainings for more information if needed. Reset and clock control. Nested vectored interrupt controller. General purpose input-output interface.