 This is the lecture that we are going to take today. So this is also a PDF file but this is not that convenient to print because this is by way of presentation. So there are things like this. Now you are most welcome to make use of these as well. So this is essentially a lecture through projections but also the same material is available as logic nodes. So these are nodes on the same. Every diagram that you see in projections is here but the text is a little detail which is appropriate so it reads like a book. So the same is found here with the table of contents and as much as you would find in a book and it is the same material that you are going to see here. So the idea is that this thing can be distributed to students so that they can print out and it is more convenient to read as a book. On the other hand the other material is more convenient to use as projection material. So almost all the material is available in both these forms separately and it will be there on your CD when you leave. So you are free to use it in any way that you wish. So we will begin with essentially a transistor model. We are going to use MOS transistor and we need to model this so that we can design things with it. So generally this is the course on VLSI design that we teach and this is the proper place to begin because what I find is that many students are not that confident with MOS devices. They have done bipolar devices and so on. These days it is becoming a little better but I do include a transparency or two about how MOS devices operate. This is not a device physicist view it is a designers view of an MOS device. We would notice here that what we have are extremely simple textbook like equations here that we assume a hard turn on we assume no leakage here. So therefore if the gate voltage, gate source voltage is less than the threshold voltage then we assume that the current is 0. If it is greater than VT and on the other hand the drain source voltage is less than the saturation voltage then we have this linear equation and if the gate voltage is greater than VT and VDS is greater than the saturation voltage then we have the saturation equation where the current is independent of the drain voltage. For digital design this is quite okay. We will see later when we do op amp design and so on that this leads to very positive results. You seem to get very high gains and so on which you will actually not realize in real life. But for digital design this is okay as a beginning and of course once you have done the basic design then you have to go to simulation and see that the circuit works with a very detailed model. This is just a paper model. So this model is oversimplified in the sense that it assumes for example that this current is just concentrate on this equation. I am afraid my loyalties are split here for this. Ideally in class I would want you to point there but right now because it is being recorded I am going to use this pointer as far as possible. So this is the equation that is a bit unsatisfactory. It says that the current is totally independent of the drain voltage in this regime and that is shown by actually this is not quite showing the saturation but essentially it according to this equation the current will become totally flat at that particular point. A realistic model actually uses slightly more complicated equations okay and the reason for that is the following. Let us look at those two simple equations. Now this is the equation in the linear regime okay. Now if I take its derivative what will I get? I will get VGS-VT I am taking the derivative with respect to VDS. So this term will just be VGS-VT right and here I will get just VDS right half VDS squared so I will get VDS. So overall I get VGS-VT-VDS okay when I take this derivative. So therefore if VGS if VDS is VG-VT then this will just cancel this okay. So as a result this slope becomes 0 that we see graphically what it says is that this line is horizontal okay. Now the point is that as I come from the left that is the equation that we are looking at this is the this is the equation for low VDS. So as I come from the left at the terminal point the curve is already horizontal and it runs into another curve which is horizontal so there is no problem in this case. However that is a physical approximation in reality we know that current continues to increase. So in that case how am I to merge these two equations? If I keep the saturation voltage the same then the first equation says that the current will become independent of VDS right so it will go and become horizontal and then I say it does not saturate. So you will have an equation which will go and saturate then take off at an angle. So you will have a discontinuity. So to take to get rid of that discontinuity you have these equations. So essentially you assume that there is an early voltage very much like a bipolar transistor this is an approximation by the way for MOS not really true. So if you produce all these lines they will go and meet on the negative side at some point which is the early voltage okay and which shows that all these lines have a positive slope and the slope increases as the current increases okay. Now because it does not culminate in a horizontal line your matching should be such that the last point on this part of the curve should not be horizontal it should have the same slope as the line that it is going to continue as otherwise it will have a kink right. So it is that which leads to this complicated set of equations not actually very complicated notice that this is the same equation this is also the same equation right this is the same equation except that the IDSS is defined that is the saturation current is defined by the same equation as last time and now there is a linear increase in this VD plus VE upon VDSS plus VE. So it is linearly dependent on VD and that is what describes this equation okay. Now I am doing this because this discussion will do double purpose it is really required for analog design in which this lack of saturation is crucial but for digital design most of the time we can use the simpler model that we had seen earlier okay alright. So now we know our CMOS device or at least an NBOS device there we can begin with the proper design. So let us there are various design styles for designing logic and the first of these is the most common this is the CMOS static design style this is what is dealt with in great detail in books and perhaps most of you are familiar with it okay. So I am going to spend comparatively less time on it even though this is the dominant style of logic but this is well explained in books and I expect all of you to be reasonably familiar with it however there are certain things which are not done in the books and those are the ones that I am going to concentrate on in the lecture here okay. So if you have a logic then it should be capable of going to either 0 or 1 that makes meaning that does not need any elaboration. So each logic stage contains the pull up and pull down networks which are controlled by signals okay now the pull up network contains P channel transistors in CMOS. So these are the ones P channel transistors take the output node towards VDD. The pull down network is made of N channel transistors and we have to ensure that both of these do not turn on at the same time nor is it possible for them to be off at the same time. So as a result the output is definitely connected either to ground or to VDD but never to both and never to neither. So there is a definite continuous drive okay. This rule you will see later will be violated by dynamic circuits with charge a node and then just disconnect okay. However for CMOS logic it is continuously driven and no power is wasted statically and that can be assured only if the pull up and the pull down are never on simultaneously okay. So let us take the simplest of these structures which is the inverter. Now the inverter design is very important most you know you would see in books that there is so much discussion about the inverter and the question which should naturally come to your students and if it does not come you should encourage this question from students is why is the inverter so important? Most of the time we do not use inverters we use logic gates, NANDs, NORs and so on. So why should we study an inverter in such detail okay. So what is your take on this? Why is the inverter important? It is the basic building block but in fact it is not the basic building you might say that digital design you give me a NAND and I can design anything with it but you cannot design everything with an inverter. So it is not a basic building block of design it is a basic building block of something else. What it does is that it represents any logic level not necessarily inverter. What happens is that it has a pull up this P channel transistor and it has a pull down this N channel transistor and the condition for pulling up and pulling down can be made more complicated that will automatically lead to other kinds of design. So once you have optimized the inverter design then we can develop thumb rules which will convert this inverter design to any other design. So therefore this is the inverter is the generator for other kinds of design. Once you have optimized the inverter design then you can generate by scaling laws or simple thumb rules other kinds of design that is why we spend so much time on designing inverters. Now if you look at the inverter characteristics you would notice that there are many parts of this which are important. This is the region in which the output is high this is the region in which the output is low and in this region the output is digitally undefined. Now we have to study all of these regimes. Now notice that we have now defined 4 quantities here. There is the input low, there is the input high, there is the output low and there is the output high. Now the question is that these are defined by these 2 coordinate points here. The xy coordinate of this and the xy coordinate of this they define they define these 4 quantities. So how do I choose these points? Why is this point here and not here, not here, not here right? Why is this point here? So let us make it into a discussion otherwise you will fall asleep. So if we define this output low, input high, input low etc by these points how do we choose this point? Because later when we determine the noise margin these are these are the things which are not discussed in textbooks so much that is why I am raising these. Later I am just going to skip over most of the algebra saying you are going to get the notes anyway but these concepts are important and these must be students must be made aware of these concepts. Then let us now look at the basic differential between logic design and analog design. So the answer is so the so the suggestion is that in analog we are worried about the actual value of the voltage which is which must be amplified whereas in logic levels we are only interested in whether it is a 0 or 1 and that of course is the difference. But let us go a step further from there. What it means is that as long as input is 0 we do not care whether it is 0 volts or 0.2 volts or 0.3 volts or 0.4 volts. As long as it is 1 we do not care whether it is 4.5 volts or 3.8 volts or whatever right. Therefore my output should be insensitive to the actual level of the voltage right output should not worry whether if it is a digital circuit. My output should not worry whether the input is 3.8 volts or 4.2 volts or 4.5 volts a 1 is a 1 and it should give me more or less the same output irrespective of what the detailed voltage level is for a digital circuit. On the other hand the analog circuit should be faithful to the input voltage it should not ignore the input voltage right. So that follows and we are going to pick it up later in tomorrow's talk when we do the analog design. So where is the curve insensitive to the exact input voltage where it is horizontal because the differential of the output voltage with respect to input voltage is 0 there and where is it horizontal? It is horizontal here and it is horizontal here and that is precisely the region in which we define a 0 or a 1 the digital mode of operation. Where is it faithful to the input where it is linear? This is the region this is the linear region okay. So the question is where do I delineate the digital region from the analog region okay. So we define this quantity dv0 by dvi okay the voltage the differential the slope of the output voltage with respect to the input voltage okay. Now for digital operation this slope should be low ideally 0 for analog operation this slope should be high right. So therefore this same circuit is now acting as a digital circuit or an analog circuit. So where is the separation? The separation is the point where the gain is 1 if the gain is less than 1 that means any differences at the input are diminished at the output that is what we mean by noise level right you may give it a very poor 0 and the output so it is very important that noise must be diminished and not amplified and therefore the gain which is dv0 by dvi should be less than 1 okay. So now we have got the formula we draw tangents on this curve and pick out those 2 points where the slope is minus 1 this is an inverter so the slope is always going to be negative as the input increases the output will decrease but the magnitude is 1 that is the 45 degree tan theta is 1 right. So we draw those 2 points where the tangent is at 45 degrees right. Now everything to the left of this is more horizontal than this tangent and everything to the right of this up to this point is more vertical right. Therefore this is an appropriate digital portion and this is an appropriate analog portion the same thing applies here everything to the right of this has a gain less than 1 everything to the left of this point up to this point has a gain greater than 1 and therefore these 2 are the natural points what are these 2 points where dv0 by dvi becomes minus 1 these define the definition of logic okay. So therefore this point is the input low anything under this point will be taken as a low right because the output will hardly change in that region only this much change for this whole range of input right similarly this point is the input high for this entire range up to vdd the output hardly changes right. So this is very important to bring why how do we define these logic levels right and these logic levels in case of CMOS become power supply dependent okay they are defined in terms of power supply whereas in case of TTL the power supply is kept constant and therefore the levels are absolute whereas for CMOS the levels are power supply dependent alright. So now we know how this input high output high etc come now these are the range first is let us see what happens if this is the circuit right let us see what happens if this voltage is less than the n channel vt so in this case what will happen this devices of completely off it is drawing zero current right then this guy sees a very high negative voltage its source is at vdd and the gate is at a low voltage so it sees a high negative voltage as a result this transistor is on and this one is off okay so as a result this node through this transistor is connected to vdd so therefore as I change my input voltage from zero to the vt of n channel what happens well that is why we had written down these equations for vgs less than vt ids is just zero right so nothing changes during that range the ideas of the n channel transistor remains zero right so therefore whatever current the upper transistor can provide since nothing is pulling it down this voltage will remain at vdd so that is one range right and as a result this is that range the output remains essentially at vdd till I reach vtn however input law is not vtn even beyond that there is a small region which will which can be taken as low so what happens at that time that means the input voltage has now just gone just higher than vtn therefore this guy takes away a little bit of current but still the current provided by this is much higher than the current provided by this right and as a result the output is still low okay so that is the next regime the nmoss remember output is high at this at this up to this point the output is high right so the nmoss is saturated because it's drain source voltage is high whereas the pmoss is in linear regime because there is very little drain source voltage available to the pmoss this is the pmoss this output is high right so there is very little drain source voltage available to this so this is in linear regime and this is in saturation that is one regime then as I still increase the input voltage both of them get saturated and that is this regime the linear regime in which both are saturated indeed when we do linear design our attempts most of the time is to keep all transistors saturated at all times okay so this is that linear regime and then finally the opposite now the output has come very low therefore nmoss becomes linear and pmoss is now saturated and finally as I increase the input voltage high this pp channel transistor doesn't even see its vt in the negative direction turns off as a result this transistor is off this transistor is on and the output becomes 0 and remains at 0 for all voltages afterwards okay so that qualitatively explains this curve okay so these are it is important to split it off into all these regions now the important point is where are those 45 degree tangents in which regime are these 45 degree tangents okay notice that it can't be in this regime because in this regime because the lower transistor is not drawing any current the output voltage cannot change it will remain just at vdd therefore the slope has to be 0 there so therefore if the output is already started to decrease that means the lower transistor is started drawing some current right and therefore it has to be in this range nmoss saturated pmoss linear similarly this other tangent will occur when nmoss is linear and pmoss is saturated this will be important when we calculate the noise margins late okay so this part is clear so what are the concepts that we want to get first of all the essence of digital design the insensitivity to the input voltage okay the second thing is the delineation of digital mode of operation from analog mode of operation and setting up a quantitative condition from which we will be able to derive the input low and input high and output low and output high okay because once we have said that the tangent at that particular point should be 0 then we can just take the derivative put it equal to 0 and solve that will give us the input voltage output voltage etc etc so that will that way given any technology and any mode of operation as long as we can express the output voltage as a function of input voltage we take it take the derivative of the output voltage with respect to input voltage set that equal to 0 and that will give you two solutions which will then give you these four points okay so that is the concept which must be explained apart from the actual derivation and so on they are important particularly for students will be important but this concept is very important to explain okay now there are a series of slides here which describe the operation in each one of these operations and I will go a little fast because the whole purpose of this lecture is not to do the algebra here the algebra is available to you as notes as well as in lectures but the idea is to understand the concept here so first the n channel transistor is off for if the input is less than VTN P channel transistor is on output voltage is VDD this is the normal digital operation range with input equal to 0 and output equal to 1 next the n MOS saturated is P MOS linear both transistors are on the n MOS is not particularly on because the input has just gone above VT so it is pulling a little bit of current not fully on okay so this is small enough so that the n channel transistor is in saturation the P channel transistor is in linear okay now in this case what do we do how do we solve what you do is that remember those old equations that we had so we put down the current for the n channel transistor and at this time the output voltage is high so we put down the saturation mode equation for this and the linear mode equation for this and equate the two currents right because that will give the settling voltage here when I equate the two currents and now if I solve okay so the ID this is for the P channel the P channel is in linear right so what is the gate source voltage what is the gate source voltage of the P channel transistor this is this is the source right so this is VDD minus VI absolute value right that is the voltage which is applied between gate and source of the P channel transistor from which I should subtract the VTP right so that is the effective gate source voltage right so that is what we have done here VDD minus VI this is the absolute value actually it is VI minus VDD negative and minus VTP we are taking the absolute value of VTP here right so this is the total amount of forward bias so to speak on the P channel and its drain source voltage is VDD minus V0 right it is important to show how it is VDD minus V0 this is the source this is the drain and therefore the voltage is VDD minus V0 right so the drain source voltage is VDD minus V0 so in that equation we just put VDD minus VI minus VTP for VGS and VDD minus V0 for the drain voltage and then this is the current equation okay the N channel is quite simple because it is saturated so you get KN by 2 VI minus VTN N channel okay and you equate these two okay now there is some algebra it is all done step by step nothing is left to chance okay so we will not just go through deriving you know the standard quadratic equation solving B square minus 4 AC and plus minus A and all of that will come okay you can do it at your leisure later but eventually you have an equation for V0 in terms of VI okay so that minus B plus minus root B square minus 4 AC by 2 okay and this says over what regime is this valid because this is valid only when the N channel is saturated and the P channel is linear that puts a limit on the input voltages for which this solution is valid okay next NMOS saturated and PMOS saturated okay this is a tough why is it tough because the current is independent of the drain voltage right so then how will you find this voltage equating currents does not involve this voltage at all right so when you equate these two currents the drain current drain voltage of the two transistors does not take part in those equations at all so there is no way that you can determine the drain voltage however you can determine the gate voltage and it turns out that there is a unique solution for the gate voltage and what it means is that there is a gate voltage here at which the drain voltage is undefined whatever the drain voltage in that range where both are saturated there is a solution that means there is a vertical part to this line when you are using the simpler model when you use the more complex model then you will be able to solve for drain because now the current is dependent on drain voltage and then you can get an inclined equation alright so this is that voltage input voltage when input voltage is this much then the output will go through a transition right for this for this range of voltages and there will be a vertical line there and finally NMOS linear PMOS saturated band etc etc NMOS on PMOS off okay so now you give me a regime and I will tell you what function output voltages of the input okay and I have also told you for what input voltage range those equations will apply okay now we define noise margins so for robust design the output levels must be interpreted correctly at the input stage of the next stage even in the presence of noise so if you want something to be low it should still be interpreted as low if you add some noise to it okay therefore my output voltage must be lower than necessary so that even with the addition of noise it is interpreted as low similarly my output high should be higher than necessary because even with a negative noise spike it should still be considered high by the next stage so as a result the output high must be higher than input high and output low must be lower than the input low and the amount by which this safety factor comes in that is the static noise margin of this family so that we can now easily calculate because we have output in function as a function of VI you choose those points at which the slope is 0 and get those 4 points and the difference between V output high and V input high and the V input low and output V output low that gives you the noise margin okay so that can be easily done again it involves a bit of algebra okay this algebra is a teacher's delight because it allows you to set questions set question papers ask them to solve etc etc so you can you can say what is the noise margin if I operate a CMOS device with K prime equal to this VT equal to this right so you can find out depending on the toughness of the question paper that you want to set but concept wise those are the concepts which are important and that is what we are we are doing where dv0 by dvi you know is minus 1 those are the 2 points that we select okay so that is how we calculate the noise margins just use the appropriate equation put dv0 by dvi equal to minus 1 and solve and you get these nice symmetrical looking equations okay they always involve that 1 by 8 factor so and they are function both of VDD VTN and VTP by the way this is a place where one should pause and tell the students that this implies that digital logic will work properly only if VDD is greater than VTN plus VTP otherwise you will have no noise margin left okay because you are subtracting VDD minus VTN minus VTP and this term occurs all over the place VDD VDD minus VTN minus VTP so therefore it is assumed that it is positive so the stage it tells you why you what puts the minimum limit on the VDD that you should use okay similarly you calculate input high input low and then calculate the noise margins and you get these nice figures okay up to now we have looked only at static characteristics right there was no capacitor there was no CDB by DTN so on of course but it is important to know whether not only that your logic gives you the correct logic functions but it is important that it works fast enough and is designed to be fast enough so you must now do the dynamic characteristics so in dynamic characteristics what we do is that we assume that one of the transistors is off okay so we are not in that close to noise margin region you just assume that one of the transistors is well and truly off in that case for charge of what happens this is at some input low right so the N channel has been turned off and therefore this is the circuit that we must solve for okay and now the drain voltage is no more a constant output voltage is no more a constant it is a function of time okay so the IP that is CDB by DT right so you separate the variables DT by C equal to DV0 by IP okay there is no transistor characteristics on this side and there is no time on this side okay so you separate separated the variables you can integrate these two equations independently so when you integrate what you get is the rise time divided by C is the integral of this from 0 to V output height okay and that tells you what is the charge time yeah one question sir you said you could assume that only one transistor is on the you not going to consider the transistor but won't the rise time also depend on the you know the input signal if it's got a slow input rise time if the input signal itself has got a slow input rise time or fault time will it not affect the you know output it will but that is the way to find out the overall delay of concatenated gates I am assuming that this is the delay for an ideally driven input okay so that delay actually goes to the account of the previous stage we are assuming that our delay starts from the point that the input has already reached this value so it doesn't matter whether it was sharp or slow so that is the delay of the previous stage right and how to optimize the delay of multiple stages that is very important of course and that is the subject matter of process and of course lecture which will immediately follow this okay so there is a logical effort theory of logical effort which allows you to optimize okay for example suppose you want an inverting function and you have a large capacitance to drive where the dynamic considerations are very important is it better to put one fat inverters or is it better to put three inverters okay that optimization is very important that includes the points that you are making and that is what logical effort defines which is what process and okay so once we have this then of course I know what function IDP is of the voltages so now I get an equation which is in voltage I can carry out this integration by the way none of the textbooks for some reason actually do this integration okay they just make some very unsatisfactory approximation saying take the average current or whatever whereas it is actually trivial to do very easy to do okay and it gives you a very good you know feel because when you plot it then you see exactly how the output is rising and finally what you find is that the rise time is logarithmic in this notice there are two terms here one is linear the other is logarithmic okay and that is very nice because that is what you see initially when the transistor is saturated it is constant current charging when the upper transistor is saturated it is constant current charging and that is this linear term but once it reaches the linear regime it is like an RC and then it is exponential charging therefore the time is logarithmic okay so this relationship can be brought out otherwise this is dry algebra but once this qualitative dependence is made clear to the students they appreciate that then by choosing different transistors this term can be made more important or less important by biasing conditions and so on and obviously this is linear this is fast charging in this point it is already shouldering off being logarithmic right so these things should be made clear rather than just writing down the expression for it okay so the first term is the constant current charging the second term represents the charging by PMOS in the linear range so it is like a resistor charging okay and if you just write down the equation for suppose the PMOS was replaced by a resistor then this is the expression that you would have got okay so you can make an equation and see what is the equivalent resistance of the p-channel in the linear rise time similarly you can calculate the fall time okay I am not going to drag you through this whole thing but it follows very similarly and not surprisingly this also has a linear term and a logarithmic term okay so this is when the n-channel transistor is saturated it is pulling a constant current out of the capacitor as a result the voltage is going down linearly but once the voltage becomes low enough this transistor is now in the linear regime therefore it looks more like a resistor and therefore it is not surprising that in this regime you get a logarithmic now notice that while this is very nice it is not necessary that the transistor will enter this regime at all suppose your input high and output low are so defined that the output low is already reached when you are in the linear regime then this term would not be there at all right because this says that after it has reached a zero how it continues to discharge but that may not be of interest to you right so therefore you should be careful about what are the definitions of input high output low and then apply these two terms okay so now we can bring out the conceptual part of this having done all this algebra I think you should have a tutorial for your students in which they actually calculate these numbers the advantages that then they become familiar with the orders of magnitudes of these numbers what are reasonable values what are unreasonable values etc if they have made a mistake in units what sort of unreasonable values should they start so therefore it is important that they practice this with actual numbers and then finally these are the simple expressions that we had gone got for the noise margins so it from here you notice that noise margin is good if VDD minus this is high that means noise margin is good if supply voltage is high but on the other hand power dissipation is more if the noise if VDD is high so there is a tradeoff between power speed and robustness higher the value of VDD you would notice that charge time discharge time also had VDD there so higher the value of VDD faster is the charging and more robust is the circuit unfortunately more is the power so now you have to take a decision do you want low power or do you want noise immunity or do you want speed and you have to come up with an appropriate compromise between these three to set the design parameters of your design and those compromises are immediately clear only when you do it this way otherwise you take average charge average current take some average current this is the charge time you do not get that internal feel of how these things are interrelated so then how do we design an inverter finally now notice that the load capacitance is the external capacitance plus an internal load itself the larger the transistor its own capacitance acts as a load so that cannot be always that cannot always be ignored okay so the load capacitance is this constant external capacitance plus something which is proportional to the transistor sizes I am assuming that KN by keeping KP is constant that means the ratio of N channel to P channel is kept constant so if you do that then you could take either that will just change the the proportionality constant here so if you put this value into the charge time discharge time you find that when self capacitance dominates the load capacitance K by C becomes constant okay what does it mean it means that if you want a faster circuit you must use a wider transistor because it will then dump more current and quickly charge or discharge but that you cannot expect to derive benefit from this indefinitely because as you keep making the transistor bigger and bigger you keep adding to your load and once this term starts dominating then the current and capacitance increase in the same ratio and now you cannot make your inverter any faster okay so there is a technologically technological limit even if you are willing to spend infinite amounts of power there is a technological limit to what is the fastest circuit that you can make and that comes from here okay these are the points which are very not very clearly written in most textbooks and I think these are the things that you should bring out because that will elicit interest from your students that they are understanding these things okay so now alright I have this optimum inverter that I have designed does it mean that now I must start from scratch for a NAND gate and NOR gate and everything from scratch the answer is no now we can just apply thumb rules for example you can treat the NMOS as a resistor and if you have 2 NMOS in series then make them twice as wide if you have 3 in series make them 3 times as wide so that together these 3 transistors look like the single transistor of the inverter okay then this gate will have the same characteristics as the inverter that you had designed okay so this thumb rule is then very easy to apply so this is the formula you take a logical expression this logical expression must be in a form that there is a bar on top okay so do your logical manipulations so that you end up with an expression which has a bar on top now you look at all the dots and places for every dot in the expression you put the corresponding N channel transistors in series and the corresponding P channel transistors in parallel for every plus in the expression do the opposite that means for every plus put N channel in parallel and P channel in series okay for all series transistors scale up their W by the number of transistors which have been put in series okay and for devices in parallel do not change the geometry okay so this is the formula we will justify this formula in a minute and here is an example so here is some impressive looking expression some A dot B plus C dot D plus C whole bar okay suppose you want to implement it in one single stage you do not have to do it as several logic gates suppose I want to do it in one single stage what will happen alright there is a bar on top so we are happy A dot B that means put A and B N channels in series plus that means this whole combination is to be put in parallel with something put in parallel with what C dot therefore the C transistor in series with D plus E that means D and E in parallel okay so it is just like reading out this logical expression wherever you see the dot put things in series like A dot B here whenever you see plus D plus E put them in parallel this D plus E in series with C because there is a dot here okay so that is how the N channels are done exactly the opposite is done with the P channel okay so for example A dot B means A and B are in parallel plus that means this whole combination is in series with C dot D plus E therefore C is in parallel and D plus E therefore D and E are in series okay if you follow why is this rule required this ensures that whatever turns the lower thing on will will guaranteed turn the upper thing off okay let us take an example if A and B are both one then what these transistors are doing does not matter they ensure that the lower part is on correct because through this path right so if A and B are both one that should ensure that the upper channels are upper transistors are off right otherwise both will be on at the same time so what part ensures that if both A and B are one the upper transistor will be off look at this if both are one then both P channel transistors are off right because if the input is high the P channel transistor is off see both are one both of these are off and that ensures that it does not matter what these things are doing the upper transistor will be off okay take an opposite and even simpler example if A is off then this part B does not matter okay now if A is 0 B should not matter notice here if A is 0 that means this is on and therefore B does not matter whether it is on or off it is in parallel okay so that is where this rule comes from that Seabass condition that we had put that at least one of exactly one of these pull up and pull down should be on at a given time that is ensured by this complementarity between N and P okay and then of course you double everything which is in series and leave the parallel geometries untouched why do we do that why should we not have after all we are talking of resistances right so you are saying that if you put an N channel and an N channel in series then R and R in series becomes 2R right but to get back to R I should put 2R and 2R in series right so therefore R by 2 and R by 2 in series right so therefore I must use an N channel which is twice as wide but why not apply this to parallel if I have two transistors in parallel their resistance is only half so cannot afford to make them half as wide each one of them why do not I change their geometries and make them smaller if there are two transistors in parallel the answer is that if there are two transistors in parallel it is not guaranteed that both signals will be one look at these two transistors a and b they are in parallel but it is possible that only a is 0 b is actually 1 in that case this guy will be off and this guy alone should be able to do whatever the inverter was doing right so therefore if they are in parallel you do not change the geometry you keep it at the inverter level if they are in series then you double the width okay so that gives us this set of thumb rules okay we will just go over it once again then we will just be adapted it for every dot in the expression put the corresponding N channel transistors in series and the corresponding P channel transistors in parallel for every plus N in parallel P in series you scale the transistor widths by the number of devices put in series and the geometries are left untouched for devices put in parallel okay and now you can convert an inverter design to anything that you want.