 Hello, and welcome to this presentation of the STM32 real-time clock. It covers the main features of this peripheral, which is used to provide a very accurate time base. The RTC peripheral features an ultra-low-power calendar with sub-second accuracy and alarms, which run in all low-power modes. Additionally, when it is clocked by the low-speed external oscillator, or LSE, at 32.768 kHz, the RTC is functional even when the main supply is off and when the VBAT domain is supplied by a backup battery. The RTC consumes 1.5 microamps at 3 volts, including TAMP peripheral with TAMP detection active and LSE power consumption. The hardware calendar is provided in binary-coded decimal or BCD format to reduce software load, particularly when the date and time must be displayed. Each feature of the RTC can be individually configured as secure, allowing different processes to share the peripheral while being protected from other non-secure firmware access. The key features of the RTC are seconds, minutes, hours, weekday, date, month, and year provided in a binary-coded decimal format. Sub seconds are provided in binary format. Add or remove one hour on the fly to the calendar in order to manage daylight savings. Two programmable alarms which can wake up the microprocessor from all low-power modes. An embedded auto-reload timer which can be used to generate a periodic flag or interrupt with wake-up capability. The resolution of this timer is programmable. The calendar can be calibrated thanks to a reference clock source which is the mains at 50 or 60 Hz. A digital calibration circuit allowing compensation of the crystal accuracy with 0.95 ppm resolution. A timestamp function to save calendar contents in timestamp registers depending on an external event. Trust zone support with the possibility to secure each feature individually in order to protect its registers against non-secure access. The RTC can also be globally configured as secure. Here is the RTC block diagram. The RTC has two clock sources. The RTC clock or RTC CLK is used for the RTC timer counter. And the APB clock is used for RTC register read and write accesses. The RTC clock can use either the high-speed external oscillator or HSE divided by a programmable factor from 2 to 63, the low-speed external oscillator or LSE, or the low-speed internal oscillator or LSI. To be functional in stop or standby mode, the RTC clock must use the LSE or LSI. To be functional in VBAT mode, the RTC clock must use the LSE. The RTC clock is first divided by a 7-bit programmable asynchronous prescaler which provides the CKAPRE clock. Most of the RTC is clocked at the CKAPRE frequency. So, in order to reduce power consumption, it is recommended to set a high asynchronous division value. The default value is 128. Then a 15-bit programmable synchronous prescaler provides the CKAPRE clock. CKAPRE must be 1 hertz in order to update the time and date BCD registers in one second increments. The sub-second register resolution is defined by the CKAPRE frequency. By default, it is 256 hertz. The SSR register resolution is increased by reducing the asynchronous prescaler value. The asynchronous prescaler can also be bypassed. In this case, the sub-second register resolution is defined by the RTC clock frequency. The RTC supports the trust zone protection against any non-secure write access. The protection can be set for the complete RTC by clearing the DECPROT bit in the RTC Secure Mode control register. It is also possible to individually configure each RTC feature to be secure or non-secure. This allows, for instance, the allocation of Alarm A to a secure firmware and Alarm B to another non-secure firmware. The features which can be configured as secure or non-secure are the Alarm A, the Alarm B, the Auto Reload Wakeup Timer, and the Timesteps. In addition, the calendar and prescaler's initialization can be protected with a dedicated bit as well as the calibration features. When the total RTC or a specific feature is protected by clearing the associated DECPROT bit in the RTC SMCR register, the registers remain accessible in read mode with secure and non-secure access. After a backup domain power on reset, all RTC registers can be read or written with secure and non-secure access, except for the RTC Secure Mode control register which can be written with secure access only. The RTC protection configuration is not affected by a system reset. Accessing a secure protected register with non-secure access is done in silent mode. The protected bits are not written without notification. As soon as at least one function is configured to be secured, the RTC reset and clock control is also secured in the RCC. The RTC registers are write protected to avoid any possible parasitic write accesses. First, the disabled backup domain protection bit must be set in the power controller control register in order to enable RTC write accesses. Then a specific sequence must be written in the RTC write protection register. Initialization mode must be entered in order to change the clock prescalar values or the calendar value. The RTC calendar keeps running in all low power modes, in VBAT mode and during reset when it is clocked by the LSE. Initialization of the time and date registers is performed through their shadow registers, which are in the APB clock domain. The sub-second register cannot be initialized. The calendar sub-second, time and date registers content can be read in two different modes. When the bypass shadow registers control bit is cleared, the shadow registers are read. The advantage of this mode is that it guarantees that all three registers are consistent. When the time register is read, the date register is frozen until it is read. When the sub-second register is read, the time and date registers are frozen until the date register is read. The disadvantage of this mode is that when exiting stop standby mode, the software must wait for a synchronization delay to ensure that the shadow registers are updated with the last calendar register values. This synchronization delay can be up to two RTC clock periods. When the bypass shadow registers control bit is set, the actual calendar registers are read directly. The advantage of this mode is that there is no need to wait for the synchronization delay. The disadvantage is that the read values can be false or not consistent due to synchronization issues. So they must be read twice and compared with previous read values to ensure they are correct and coherent. This slide presents the main calendar features. Daylight savings can be managed by software with automatic one-hour addition or subtraction. It is possible to synchronize the RTC clock to a remote clock by adding or subtracting an offset to the sub-second register on the fly with CKAPRE clock resolution. This feature is commonly used in RF applications. A reference clock, mains at 50 or 60 Hz, can be used to enhance long-term calendar precision. The reference clock RTC refin is automatically detected and used to update the calendar when it is present. When the reference clock is not available, the LSE clock is automatically used to update the calendar. This feature is not available in standby, shutdown and VBAT modes. A timestamp function is available. The calendar values, RTC SSR sub-seconds register, RTC TR time register and RTC DR date register are saved in timestamp registers when an IO RTC TS event occurs. A timestamp event can also occur when a switch to VBAT occurs. In addition, it is possible to timestamp the RTC counters when an internal or external temp event occurs. Please refer to the temp peripheral training. The digital calibration is used to compensate crystal inaccuracy and accuracy variations with temperature and aging. This calibration is not suitable for the internal oscillators as the digital calibration total range is too small to compensate internal oscillators inaccuracy. The digital calibration consists in masking or adding a programmable number of RTC clock cycles fairly well distributed in a configurable window. The calibration window can be changed on the fly depending on detected temperature changes, for instance. When the LSE at 32.768 kHz is used as RTC clock, a 1 kHz calibration output signal is provided to measure the crystal frequency before and after applying the calibration value. The accuracy shown here is the resolution of the digital calibration. The calibration window size is configurable between 8, 16 and 32 seconds. For a 32 second calibration window, the accuracy is plus or minus 0.48 ppm. The total correction range is from minus 480 to 480 ppm. The accuracy resolution scales with the calibration window size. Final accuracy in the application will depend on the crystal parameter precision, temperature detection precision, how often the software calibration procedure is launched, etc. In order to reach the precision of the calibration window, the measurement window must be a multiple of the calibration window. The RTC embeds two flexible alarms based on comparison with the calendar value. The alarm flags are set if the calendar sub seconds, seconds, minutes, hours or date match the value programmed in the alarm registers. The alarms events can wake up the device from all low power modes. The alarms event can also be routed to the specific output pins RTC out 1 and RTC out 2 with configurable polarity. The calendar alarm sub second, seconds, minutes, hours or date fields can be independently masked or not masked for the comparison. When the masks are used periodic alarms are generated. In addition to the calendar and alarms, another 16-bit auto reload counter can generate periodic events with wake up from low power modes capability. This counter cannot be read. Depending on the software configuration, the wake up timer clock can be the RTC clock divided by 2, 4, 8 or 16 or the output of the synchronous pre-scaler. With the divided RTC clock, the wake up period can be from 122 microseconds to 32 seconds when the RTC clock frequency is 32.768 kilohertz. The resolution is down to 61 microseconds in this case. With the CKSPRE clock, the wake up period can be from 1 second to 36 hours when the CKSPRE clock is at 1 hertz. The RTC provides two outputs, RTC out 1 and RTC out 2. Depending on the selected configuration, these outputs can provide either the alarm A flag or the alarm B flag or the wake up timer flag. It is possible to combine this output to the temp signal being the OR of all internal and external tamper detection flags of the temp peripheral. The resulting signal is named tamp alarm. The polarity of tamp alarm can be configured as well as the output mode, push pull or open drain. It is also possible to apply an internal pull-up to this output. In addition to the tamp alarm signal, the RTC out 1 and RTC out 2 outputs can also provide a calibration output signal extracted from the pre-scalers. When the pre-scalers are set with their default value and the RTC is clocked by the LSC at 32.768 kilohertz, the frequencies of this signal can be either 512 hertz or 1 hertz. The RTC uses the RTC TS pin for external timestamp and the RTC Refin pin for automatic calibration with reference clock. In addition, another signal named LSC0 outputs the LSC clock. All RTC pins are available in all low power modes, including VBAT, except the RTC Refin input, which is not available in standby and VBAT modes, and the RTC output on PB2, which is not available in VBAT mode. Several RTC events can generate and interrupt. All interrupts can wake the microprocessor up from all low power modes. The alarm A interrupt is set when the calendar value matches the alarm A value. Similarly, the alarm B interrupt is set when the calendar value matches the alarm B value. The wake-up timer interrupt is set when the wake-up auto-reload timer reaches zero. The timestamp interrupt is set when a timestamp event occurs. The tamper 1, 2, and 3 interrupts are set when a tamper event is detected respectively on the RTC TAMP 1, RTC TAMP 2, or RTC TAMP 3 pin. The RTC peripheral is active in all low power modes, and when triggered, the RTC interrupts cause the device to exit a low power mode. In stop and standby modes, only the LSE or LSI clocks can be used to clock the RTC. Note that only the LSE clock is functional in shutdown and VBAT modes. A bit is available in the debug interface in order to stop the RTC counter when the core is halted for debugging. This is a list of peripherals related to the real-time clock. Please refer to these peripheral trainings for more information if needed. Reset and clock control, power control, tamper and backup registers, and debug support.