 Hello, and welcome to this presentation of the STM32MP1 DDR memory subsystem. The key features of the DDR subsystem are support multiple DDR standards, DDR3, DDR3L, LPDDR2, and LPDDR3. For all standards, the maximum frequency is 533 MHz, DDR at 1066 Mbps. Note LPDDR3 is supported without on-dye terminal or ODT, similar to LPDDR2 support. 32-bit interface width can be either fully populated, 32-bit, or half-populated, 16-bit. Note the device may also be packaged with the 16-bit DDR interface only. Density limited to 1 GB due to the memory map address range. DDRSS is supporting single rank only. DDR3 and DDR3L memories are similar except for the supply voltage. 1.5 volts for DDR3, 1.35 volts for DDR3L. For the sake of simplification, we refer only to DDR3L. DRAM topologies can be point-to-point or P2P applicable with a single SD-RAM device on the board. This is the case with 16-bit DDR3L or 32-bit LPDDR2 or 3 memories, or flyby applicable with two DDR3L devices, 16-bit on the board, and a 32-bit full-populated interface. For the flyby topology, the command address bus or CA bus is sequentially routed to the two DDR3L devices. ByteLanes groups, DQ or DQS, are connected point-to-point. It is also recommended to use termination on the command address bus to VTT. The suitable topology is determined by the SD-RAM memory device and the DDR interface width, resulting in a number of SD-RAM devices considering their density. LPDDR2 or 3 devices are mostly available with 32-bit data bus width, while DDR33 or 3L devices are mostly available with a 16-bit data bus width. The DDR subsystem, or DDRSS, is composed of two main parts. The DDR controller, or DDCTRL, and the DDRPHY, or DDRPHYC. DFI is the standard interface between the DDR controller and the DDRPHY. The DDRCTRL is in charge of convert AXI bus transactions to DRAM transfers at DFI interface. AXI port arbitration, DDRCTRL is equipped with a dual 64-bit AXI. Schedule DRAM commands according to traffic classes, or QoS, for optimal DDR utilization, and schedule DRAM refreshes. The DDRPHY, or DDRPHYC, is in charge of drive command access, or CA bus, and write data, DQ or DQS according to JEDEC timing. FIFO read data, DQ or DQS according to JEDEC timing. Programmable initialization of PHY and DRAM for DDR3 and LPDDR2 or 3 standards. This is a simplified block diagram of the DDR subsystem, or DDRSS. DDRCTRL is a multi-standard DDR controller connected to the SOC backbone, and which generates DDR commands at the DFI interface. DFI specification defines a generic interface protocol between a memory controller and PHY interfaces. DDRPHYC is a multi-standard PHY interface, which supports the actual signaling of SD-RAM memory device. DDRPHYC also supports the required initialization sequence, and some fine timing control required by the SD-RAM. DDRCTRL and DDRPHYC have their own control registers. DDRCTRL is connected to the SOC backbone by two AXI ports. DDRPHYC has a slice-based architecture with a command address bus and four byte lane. The main DDRCTRL features are two 64-bit AMBA4 AXI4 ports interface, or XPI, asynchronous to the controller. 64-bit with DFI 2.1 compliant interface to DDRPHYC. Advanced Scheduler and SD-RAM command generator. One-to-one frequency ratio between the DDRC clock and the DDRPHY, aka SDR mode. Advanced QoS support with three traffic classes on read and two traffic classes on write. Options to avoid starvation of lower priority traffic. Guaranteed coherency for write after read, or WAR, and read after write, or RAW, on the AXI ports. Programmable support for burst length options. Four, eight, or sixteen. Write combined to allow multiple write accesses to the same address to be combined into a single write access. Single-rank configuration. Supports the automatic SD-RAM power down entry and exit caused by a lack of transaction arrival for a programmable time. Supports the automatic clock stop or LP DDR2 or 3 entry and exit caused by the lack of transaction arrival. And supports the automatic low power mode operation caused by a lack of transaction arrival for a programmable time via hardware low power interface. Programmable paging policy can be as any of the following options. Leave page open after accesses. Open page policy. Close page when there are no further access available in the controller for that page. Auto-precharge with each access with an optimization for page close mode, which leaves the page open after a flush for read write and write read collision cases. The DDR controller supports the self-refresh entry and exit as follows. Automatic self-refresh entry and exit triggered by a lack of transaction for a programmable time. Self-refresh entry and exit under software control. Support for deep power down entry and exit under software control or LP DDR2. Support for explicit SD-RAM mode register updates under software control. And flexible address mapper logic to enable application specific mapping of row column and bank bit. The DDR controller supports programmable 1T or 2T timing. Refresh control mode can be selected among the following options. Controller generated auto refresh is at programmable average intervals. Ability to group up to eight controller generated refreshes together to be consecutively issued. This reduces the number of page closings increasing the overall efficiency. When the controller generated refreshes are grouped, some refreshes can be speculatively issued when the controller is idle for a programmable period of time. Ability to disable controller generated auto refreshes. Ability to issue a refresh through direct software request. And user selectable ability to perform pre-bank refreshes rather than all banks refreshes for LP DDR2 or 3 devices. This is a simplified view of a DDR interface using source synchronous signaling. The interface has several signal groups. The CA bus group, which consists in command address signals. They are unidirectional and related to the differential clock signals CK CK hash. CA signals are center aligned at PHY output by the delay locked loop circuit or MDLL. The CA bus uses single edge SDR for DD3 and dual edge or DDR for LP DDR2 and 3. The DQ DQS group per byte lane. These signals are bi-directional according to read and write command. The data group includes data or DQ and data mask or DM signals. They are related to the DQS DQS hash strobe. For write access DQ and DQS are center aligned at PHY output by the MDLLs. For read access DQ and DQS are edge aligned at SDRAM edge and the PHY will gate in and out signals and realign DQS and DQS hash for optimal sampling using the SDLL. Furthermore, fine step delay can be applied to individual signals in the group for optimal timing margins. This is covered by the tuning procedure. DDR PHYC uses a byte lane architecture so that all signals in a group are closely matched. It uses a master DLL or MDLL for command address signals to the SD RAM memory and a master slave DLL or MSDLL for each byte lane group. MDLL helps tune the CK CK hash delay by 180 degrees SDR mode in the case of DDR3L devices and by 90 degrees DDR mode in the case of LP DDR2 and 3 devices. MSDLL is used to delay DQS DQS hash output signals by 90 degrees to center align write data. MSDLL is used to delay DQS DQS hash input signals by 90 degrees to center align read data. This is a simplified diagram of the DDR PHY controller. The physical utility block or PUBL includes the control registers and several state machines. PUBL is in charge of the sequence of the PHY activity including the DDR initialization sequence. PUBL supports impedance calibration and several built-in tuning with programmable execution. The MDLL and MSDLL are generating clock phases to the internal timing modules or ITMs. This is a summary of the DDR PHYC features. PHY initialization with DLLs reset and locking. SRAM initialization including MRS and ZQCL commands according to SD RAM standards. Output drive and or OTD impedance calibration or ZCAL. DQS gate training or DQS TRN to position optimal gating of read data. Support read DQ DQSI centering with fine step delay by software. Support read DQ delay tuning with fine step delay by software. PUBL also supports a BIST engine for at speed loopback testing. The complete PHY initialization including SD RAM initialization and DQS TRN is shown in this diagram. The sequence is defined and controlled by the PIR register. This sequence is launched after a system reset. Tuning parameters determined by software during the bring up are saved and restored. The DQS gate is the window during which read DQS propagates to PHY read logic to sample incoming read data. DQS gate position is dependent on the round trip delay. The DQS gate needs to be positioned to quarter bit accuracy. PUBL is supporting a built-in DQS gate training sequence or DUS TRN. It is launched by default during initialization. DQS TRN is using the SD RAM array instead of the DDR3 MPR register. By default row bank column zeros are selected. DQ and DQS can be delayed in fine steps plus or minus 20 picoseconds. DQ bit delays are used to compensate for DQ bit mismatch. DQ bit desquew. DQS DQS hash delays help optimize the placement for DQ sampling or DQS read eye centering. DQS DQS read tuning is a software procedure supported by the STM32 cube MX tool to find optimal settings. Both DQ bit desquew and DQS read eye centering should be done during the board bring up and the determined optimal settings saved to the DDR configuration registers. The power saving scheme is implemented at various locations of the DDR sub system. SD RAM with pre-charged power down, self-refresh and clock disabling. DDR-PHYC with DDL and IOs low power modes and DDR CTL and SOC with clock gating. Self-refresh is the main power saving feature supported by DDR CTRL. It can be entered in three ways. Explicit control from software or SSR based on an idle timeout or ASR or control from hardware or HSR. The DDR CTRL and DDR PHYC registers are programmed according to SD RAM timings and configuration prior to DDRSS initialization. The DDRSS configuration is requiring minimal information from the user through the STM32 cube MX DDR panel. The DDRSS is ready after the DDRSS initialization. Enabling the AXI port is the final step. Besides the predetermined configuration parameters, the tuning parameters are determined during the board bring up using the STM32 cube MX tool. Once the DDR memory is configured and the PHY is tuned for optimized timing, the configuration robustness must be tested. A complete test suite is proposed by the STM32 cube MX tool. Configuration parameters are saved and restored before regular DDR operations. For more details, you may refer to the following documents. DDR3 SD RAM standard, JEDEC, JESD79-3F, LPDDR2 SD RAM standard, JEDEC, JESD209-2F, LPDDR3 SD RAM standard, JEDEC, JESD209-3C, RM0436 reference manual, STM32 MP15XXX advanced arm-based 32-bit MPUs, AN5168 DDR subsystem initialization and configuration, AN5122 DDRPCB design guidelines, and STM32 cube MX tool.