 us Hello everyone we last lecture we saw discuss a lot about last week what are contain, what is continue, now we go back to the introduction for design compiler, first st arb-worthy understanding and loading the EP truth, second step was reading the ANDR design for design compiler వారారం్చినియాయండి. సంప్నినియార్చియాయాచీం. పీరికిక్, నే. మాన్ండియా, సి మ్పెటిర్న్చి. ఎసైటాయ్, బ్లోలిలోక్పివా. . Now writing then law cool for synthesis and for simulation or verification these both are entirely different task, we will see the important contents of RTL coding if the focus on synthesis . So, RTL design the way we go about it is you always start from we have to first think in terms of the when we when we write RTL person to take we should think in terms of hardware what is the hardware there should be some vision in our mind. So, typically any design will be divided into the beta part and you control this. So, we should divide that into really understand what are control signals, how the data flows through the design. Then instead to we specify the behavior of each part. So, the design could be done in two ways a top down approach or a whatever approach in top down let us say in top down I would first think about and visualize what that is the thing. For example, if you contain a memory you can so on and then start writing start writing code from top down in bottom up usually I would first care about what we are doing I would first code the ALE and then go on to make the CT in bottom up. So, both these design techniques co-exist and so usually in a big in a industry where big chips are made both co-exist. So, the chip team will think in terms of top down and the teams who are then designing those individual blocks with thing bottom up and then the blockers and all the blocks are familiar with the RTA response. So, in this example we see that we have a control unit control unit will mostly be a finite state machine like this with the same four states there. Then the control unit will give control signals to the data parts unit the data parts unit will feedback and data signals data parts will have we really did have operators like I did I did I did so step 3 is design circuit. So, step 2 is where we code the RTA step 1 is called the architecture thing step 2 is where we actually code the RTA. In step 3 is conversion of RTL into BLIT which is performed by the IDEA 2 in RTA step 3 is designed. So, the common errors which beginners do when they start coding for synthesis is first is that they might use non synthesizable coding style a wrong code will result into correct simulation, but the hardware will not be correct or the hardware that the tool will not recognize those those non synthesizable coding functions. For example, dollar display, dollar time, hard coded delay values in the end of they are all non synthesizable. They are not they are done they are not able to recognize that by design compiler. So, the compiler the RTA compiler inside design compiler is quite different from the RTA compiler of a simulator. So, we have to keep that in mind by coding. Second mistake common mistake is the code is synthesizable, but without concrete imagination on hardware that is we will see an example where just just by the coding you may actually increase the number of potential logic or there will be long part delay from input to output just because of bad coding style and so the two major problems of this one is either the timing is bad that is the performance is bad or the area is low. So, there are various coding guidelines to make sure that your design is effective in terms of area and timing. We will see some of those. So, the correct method of doing RTA coding is step one you should have some time diagram of your hardware in mind. We should be very very clear about what is the combination part of our design and what is the future part of our design so that we can process it exactly into the RTA it will be an effective RTA. We should follow fixed coding we first study the fixed the coding styles the recommendation and then start coding. It is very very very important to have some block diagram in mind. If the block diagram is absent you will not be able to design the input. So, it helps to start on paper about the architecture. It helps to write down the architecture in terms of block diagram on the paper before starting the coding. And let us say you are going to design a big block which will in turn contain small blocks. It is very important that we synthesize small block form especially if we are beginning to launch into this because this will make sure that we catch all the errors in the beginning itself. So, let us see the examples. So, now there are lot of coding can be done in two ways in two separate ways. First is the structural coding where we describe the hardware directly. For example, let us say you have an adder and a register. So, the functionality says that data out gets the value of data in plus. So, this is an accumulator and the adder is nothing but an accumulator and the value is stored in payload register the RTA code is there. So, you have always add for this block S gets 8 plus 2. So, now this the second so, this the example there this only the the block time is diagram is nothing but the structural description of the hardware. You could also write the behavior description using the register transfer rules like this only that for this block S gets 8 plus 2. So, this is obviously more sophisticated style of coding and you would go in the you would actually code the functionality of the combinational sequence logic like this in most of the cases and your top level. Let us say you are designing a chip you already did you are designing a CPU and you already have a memory unit and all other blocks you could do some structural coding to book up these blocks together at the top level. Let us look at examples for structural description. So, structural description is nothing but describing a hardware with block icons in mind. So, we see the same example again the accumulator instruction this written will look something like this. So, there is a demo circuit demo circuit where module is defined inputs and outputs are defined and then adder and payload is defined. So, the basic unit of I will just illustrate some well of basic concept the basic unit for well of hardware design is a module. So, this is the module demo circuit the module will have some inputs and some outputs. So, the hardware design is a module we will have a module can contain some modules like module demo circuit contains adder and payload register. So, adder is in itself will be a module and you add is nothing but an instantiation of the module adder. Similarly, you ACR is an instantiation of the module payload register. So, structural description in the structural description you would have the instantiation like you add and you ACR and you would have wires that connect between connect among the structural blocks and again you will have output wires. So, assign data out is equal to AC out where AC out is a wire. So, we will just highlight what are what is the what happens in a structural description. So, the module will be defined and the design is specified like this. We define the inputs and the outputs. Now, we look at what are the instantiation modules. So, you add here is a an instance of the adder of the module adder adder is. So, here in this in the slide we do not specify what this adder contains, but it is understood that adder is again will be again a module which will which will implement the functionality of the adder and actually do a plus b which will actually have data in plus the state out is feedback here. Again so, payload register will be nothing but a a band of flip flop. So, with the instance name could be anything it is useful to be meaningful name so, that you can know by the instance name the really the instance name what we do is we define the instance name to be the module name and we add and that is why it is to be. So, it is clear from the name itself that what module the instance belongs to. So, here we see we go inside the adder what adder could be. So, in this case the adder is implemented using case statement. You could see that adder also has a control bit and this control bit again comes from the top from the input to be the control bit. So, based on the value of control so, here the control input is connected to dot off this is called explicit specification. So, the naming convention is such that the input outputs are connected that adder is IN 1 gets AC out adder is IN 0 gets data in adder is OP input gets CTRL adder output gets connected to adder. So, here output is although output is defined to be a register here, but we know that this is a we will see that this is a combinational job completely combinational job and based on the value of case OP. So, in the in one case out gets the addition of two inputs or case of 0 1 out gets one input the case of 1 0 outside 0. Now, we see how wires so add out here is a wire that is used to make connection between out of this we add out gets used here it connects from this to this. So, if you could take one assignment of writing a random model for a for this a few minutes. First you could assume that the adder the adder. So, this is the block diagram which you are given as we discussed we started the block diagram. So, given a block diagram like this try to write a well of code for this. You cannot use this well of code for this assignment also for this first assignment is the very comparatively simple code, but it contains the question is that it contains both combinational and you can you could go over the the reports for both. So, first you assume that adder muck in the register are some modules which are given to you and you write the structural code like like here and then again you could go on to write the constitutive adder muck this will this will kind of be will be a top down assignment. So, you write the structural top level first and then you go on to write the definitions for the some modules. So, in a structural description we always use wire to declare signal because by definition the actual module will not contain any logic apart from just a simple connection. And since there will be so the module here it does not contain anything apart so we can differentiate these two modules, but the only logic here is just connection there is nothing else. So, all these connections will be defined as wire should be defined as wire. Now if you fail to define so what what synthesis does let us say I do not define ACM. So, now synthesis will assume that ACM out and and we use something here we use add out for example we do not define add out, but we are using add out we are using add out here and we do not define it to be wire synthesis will assume that add out is a single bit wire in that way. Any undefined wire is assumed to be a single bit and then what it would do is it will feed the LSD and make all the other bit which you do not want. You want the complete connection so it is a good practice very good practice to declare all wires irrespective of how much bit they have. And when you are doing structural coding try to avoid avoid this vehicle code like all these other data. So, as I mentioned before structural description is usually done for the top level RTL code where the top level is again in arbitrary term it could represent anything it could represent a case it could represent an empty coder or a CTU or some other type of that. But the idea is to start with and the RTL for that block diagram could most probably be a structural description. And then the sub modules will probably use behavioral coding to implement the combinational sequence in that. So, let us look at the another example of structural description where we describe the hardware with Boolean or arithmetic equation. So, the very popular statement is the sign statement a sign will take a wire a sign x is equal to something in this x is a wire as written by some combinational circuit it could be a Boolean equation it could be an arithmetic equation it could be a multiplexer we will see to example. We see an example of a Boolean equation so here wire d is an intermediate wire we assign d is equal to a and d assign d is equal to c or d we could also have assign d is equal to a and d or c you will see to write whatever way you want the most important thing is that we should play about what are the functions. So, these operators are very similar to Boolean operators Boolean operators Boolean operators this is one more example as I told you could write so depending on the maturity of the of the hardware design these assign statements can be very basic or very complex so an adder can be implemented again using simple assign statement assign c is equal to a plus d one more example where you have a b going to an adder and then c as d a plus d c plus d is equal to b something like this so the order it does not matter the order of assign statement assign d is equal to c plus d assign d is equal to a plus d will not change this is different from a regular soccer language that both these assign statements are parallel to each other in the sense that the tool will understand that first d has to be computed first d has to be computed and the d will go as an input to this adder the tool very well understands that the respective of whatever you write so reorder will be the same you could also write assign d is equal to a plus d plus d and again the tool will depend upon what kind of adder your technology that we contain it will be mounted if it does not contain adder circuits then then it will be used and then all it will end we see an example of a mark where based on the value of s c get is the a or b so this is a very simple statement assign c is equal to this operator again in the c style operator it exists through this is one c gets a otherwise c gets b so the the rule of thumb to use sign is that we use it to describe a combination of it good in an arithmetic equation and the expressions are very similar to cc cluster so please note that again that assign statement is a very useful tool we see so the general we saw we saw example of an assign statement now we see the all this block so all this block is again called the event driven block it specifies a rule for event driven simulation the law was originally designed for hybrid simulation and not for synthesis that is why a subset of the law is not everything is so the combination logic we will see how combination of the different ways of writing combination logic but an always block has an always block whenever the value on the LHS has to be registered so we first declare the registers declare variables the registers do not always mean there will be converted to a sequential element we will see what are the rules so always there will be an event place there will be some type of code in between to compute d and e so so these are the different ways in which we write combination logic first is always at the rate we give all in the list we will see the importance of this we have to very carefully choose what all goes here or to be on the safe side we could use always at the rate of start we will see what happens if we do not use if we incorrectly give incorrectly miss out some signal we will see we use blocking assignment now it will be I will not going to detail here about the differences between blocking and non blocking assignment I would request you to go back to your the law handbooks and read about blocking and non blocking it is a very unique feature of the law and the usage of it also determine what will be some place so so one way is always lock always at the rate of signal list or always at the rate of start when blocking then we use non blocking for combination or we could emulate all cases that is we could write a tool table and the tool will know from the tool table how what to do so let us see one example here so now in this so whenever synthesis tool we will see always at the rate of A or B or C that is there is no causage or negation it will assume and it will assume correctly that is this always block actually it is talking about a combination logic because there is no hardware equivalent of for example always there is no hardware equivalent of this it has to be a combination of this there is no flip flop which works on both causage and negation of or any signal so always at the rate A or B or C E is equal to A and B or C you could see in simulation also here what happens in simulation whenever A or B or C one of these changing E gets A and B or C so we see A is changing B is constant 1 C is constant 0 now so these this structure the one contained in the parenthesis after at the rate of it is called the event list so these signals when they change whenever there is an event on these signals again these are C like statements for simulation so whenever this let us say A is changing here E changes here so A B is 1 D is 1 and C is 0 you could so E is nothing but A because A and B B is 1 so it becomes A or with C C is 0 so E becomes A in this way but whenever A goes from 0 to 1 we will also go from 0 to 1 after some time in simulation time let us say E is the value of C because this first of all the circuit level has a C this is even if it had it had a C this always C so the synthesized circuit will represent the combination now in this case E is declared as a register it comes personally to declare E as a register because anything which is assigned assigned a value inside an always C always C as to be declared as a register but it does not E does not E is in hardware is still a wire please note this in hardware after it is synthesized E will remain a wire and not a flip flop or a latch although it is in register because the tool will determine that E is taking E E is a combination circuit and there is no always block in this design which tells us that E is an output of a flop it tells us that E is an output of a combination circuit so that is what synthesis tool does and in hardware E will remain a wire so let us see your example this is one example we saw anyway so we saw here that we could do A or B or C now what happens if we forget C now the simulation the simulation will work if we forget A and A changes now here in the waveform now if we forget to write A here always with the rate A we just write always with the rate B or C now in simulation you would observe that E does not fill because B is constant C is constant a change of A this does not get activated so E will not change but synthesis since it knows E is equal to A and B and R or C so this line will tell design compiler whether this code is sequential or combination now it knows it is a combination and it will just implement this after knowing that the code is combinational it will just implement this synthesis will still implement the same here and now there is a mismatch in simulation because in simulation a change on A does not result into a change in E but the synthesized circuit remains same that is why this is to do this you call it as a rate of star it tells that any input simulation will get triggered by any input and DC will synthesize it correctly and you will never have a simulation in this so this is a very popular coding technique also with the rate of star again you could code like this you could code B is equal to A and B so again these always with the rate of star tells us that these two are combinational again there is a density there is no difference in the earlier code and this code in terms of synthesis again please note that all different all these blocks are parallel to each other they are not sequential in very large statements within one always blocks will go sequentially but all the always blocks are parallel to each other even if we exchange the code we write one always block below the other we switch the order it does not change the symbol or simulation other thing we could do is that we could write a truth table the last example we saw was writing the Julian equation we could write a truth table like this in a case statement we write the cases here again the tools are the design compiler is intelligent quite intelligent enough to determine that what constitutes and it will just implement exactly the same that is why you can actually do a more sophisticated RTA coding and not worry about the optimization because the tools are very good at optimization they will come up with a lower area here the important thing is to make sure that you mention all the cases and as the number of inputs increase it is not too easy that is why this kind of coding technique is very popular this is popular this type of coding technique is popular for very few special cases but that you could also do that this is the truth table so in this truth table you note that the constant has defined to be like 150, 150 and so on just a note on this how do we represent constant binary for binary we use D for H3 we use H we write bits first for example if you want to write a 10 bit 0 so you could write 10 bit 0 or an example is here tick D101 assume to be a 3 bit since it is 101 we could write it explicitly 3 to 310 this being MLB, this being directly again it is a decimal number both like this tick H0982 tick H0982 decimal you could write tick D1234 tick D1234 tick D1234 tick Dactor so this slide just experiences the point that for main statement can be involved by ! now we see you see one more example with case statement here so for example we want to mark something you could write a case statement now please note that here this writing approach table is also in this case we specified constants on e we told the tool that e gets the constant value 1 and 0 on different cases. We could extend this we say that while implementing a must we must we could say that on the value of filter dealers we will be able to get in month that will be done. So, now this with such an structure when all inputs are changing there is a case analysis the tool would assume that it is a must kind of structure. Now what the hardware will look like now depends on the standard cell library. Now in the earlier case also in this case also the tool could use a must to implement it, but again it depends on whether a library contains a must module or not, but most of the library standard cell library do contain the must module they also contain and and not within the standard cell. So, now the tool will see what is the area application of using a must versus using an AND of it and then it will take a proper decision based on the again time limit. So, not necessarily that every case statement will get translated into a must it is not necessarily that every case statement is translated into a AND and AND of circuit. So, it is purely depends on what area numbers are talking about what are the timing they are talking about. So, it depends on if you factor however you could force the user a must by using a very special base special polling technique which I will discuss in the next lecture. I will discuss how to make sure that this code this code gets started into a must. Many times we will want to the tool to implement a must standard success due to very specific cases specific needs and we could do that. So, here also register is not a register in hardware or this is a wire because this is not a computer. Now this out is equal to hx to kx specified a don't play condition what it says as that because sanity is that for case OP being 1 1 we do not care what the output is. So, now what DC design compiler will do is that most probably it will use the values from 2 to 3 1 0 that is out being 0. So, it will choose like in a 2 table in a Kano map for don't play conditions you could make those conditions you could make those conditions 0 or 1 depending on what the lowest amount of hardware you get it is exactly same for the design compiler. It will see what option on out it does into the lowest area it will use that. We could also use it statement is opposite equal to 2 to 3 0 0 out again this is exactly same as the previous case statement, but one now one important thing is that now here in this case we see that in the first line we have specified out to the hx this is very important because here we specified the case of 2 to 3 0 0 2 to 3 0 1 and 2 to 3 1 1. So, what about the third case that about the case it is don't care for example, so here only three cases are defined 0 0 0 1 1 1 and not 1 0. So, what happens in 1 0 if this line is absent if this line is not there the tool the design compiler will assume that if for the the case of 2 to 3 1 0 which is not mentioned here you want to retain the values out to that means, you do not want out to out to change this is not a combination there is a sequence in all the components that is you are telling the tool that for one of the cases I can put as the control value my output should remain unchanged that means, you should remember what the output was this is again a thing. So, this is a sequence of our component now tool will try to install an action that is why it is very important to have this kind of statement where you assign the default value the default value in the first statement itself and then in the later statements to tell what value do you want on different cases. This will make sure that a proper hardware is available you will see how to check for this problem and how to correct it. So, this is all that the rate of star is 2,000 well-off 2,000 month standard well-off 2,000 standard well-off 95 and 2,000 month most 2,000 month is a new law and you could use the features of both actions. One question though that it is not recommended to use its statements to describe larger than 2,000 month because the tool design compiler in most probably in most of the cases they will synthesize the priority kind of input what it seems let us say you have a code like this select is equal to 0, 0 is equal to 0 select is equal to 0, 0 is equal to 0 now tool knows that first it will evaluate if select is equal to 0 and it will give it will give a to o then it will go to 0, 1 so this 0, 0 select is here this 0, 1 select is here then b goes so then c goes to now here we see that the last guy that is b going to a now is going to 1, 2 and 3 this is the priority kind of project priority decoding and this mostly happens for large boxes if you use statement so it is recommended to use state statement for such type of big you use state statements 0, 0, 1, 1, 0 there is a command called with others that means you want for all of the cases for all the many cases of big mark still let us say you have a 4 or 16 is to 1 month you have 4 select lines and you only concerned about what happens to output in 10 or 2, 15 cases you could write all the 10 cases here and write whenever it should take care of the remaining cases and it will assign some default values this kind of code results into a proper much kind of structure where every input has similar kind of delay to the output again the library might not have a 4 is to 1 month might not but it will have some kind of mark and now seeing the case statement the design compiler will try and use it knows that we want the balance circuit and it will try and use whatever mark designs are available there to implement now we see that how the last of the period combination logic is also present so now if you have something like this always a data update if date is proved then you get data it means if date is called then the value of Q is not changed this is again a last of circuit so this code here is actually a proper code for the match now let us say it is used by this is a this code you know by mistake you want it you do not want the match but you want the combination circuit how to correct it first thing is to avoid match you could do you could assign some default value to Q for example you assign Q is equal to 0 now if date is once you get data but then date is 0 you get Q is still 0 so now the tool does not need to store the value of Q so there is no matching again second example is you write the L so this again is kind of a mark structure when date is nothing but the next thing and when date is 1 you get data and date is 0 you get Q so we see what kind of reports tell us that the tool is inferring matches and you have to take for that and correct that if it is a matching again this typically this problem typically happens when you have big case statements so this is one example of one hot coding where decimal gets 10 bits the decimal signal here is 10 bit and only one bit is high in one of those cases but the seductive again 4 bit this is the hex so hex one hex is 4 bit long we have specified 0 to 9 here but what happens to decimal when the value of i is from k to f in this case this code is actually error prone when it is entered into latch so to prevent the latch we add a default statement default means that for all such cases which are not defined here decimal which we will get all 0 this will tell tool that all the cases are defined so please implement a combination of this problem let's see we saw last few slides discussed about the combination elements how to code combination elements how to make sure that the design is latch free we saw different methods we saw writing all this statement using an assign statement using case using if let's see the sequence elements the general scheme is that sequences are it only simulate when clock is triggered so always at the rate positive is very important positive or negative it tells us tells the tool that it's a sequential element it only works on one edge of the clock so the coding side is always at the positive clock we always use non blocking for simplicity although you could use blocking and design compiler will not complain but it might create problems for simulation so that hardware will be correct but the stimulus which we use for the RTL to check it and when we use it for netlist both will produce different that's what we use blocking the time but the hardware will be correct so this is the kind of code we write always as porous clock accumulator edge gets RL so the value of RL gets transferred to ACC edge whenever there is a edge so simulation is triggered by a clock non blocking is used to generate registers and the value gets transferred here so on the edge of the clock you see what is the old value 1 0 1 0 is the old value 0 1 1 0 is the new value if we in the simulation it is changing right at the same time the tools will infer register and it will the last value will be taken the old value 1 0 1 0 now ACC edge gets 1 0 1 0 here on the next edge it gets 0 1 1 0 the hardware is next so this sequential circuit you could always have a combination feeding into it combination circuit so for example here although the porous clock the implement so this is a this is an example of an accumulator register stage output so data out is coming out of register the register into data out is coming out of register there is the input there will be a marks here so this this combination logic here the marks here will be at the input of the register this is an example of finite state machine so the finite state machine in this case the register s here register s here is this state here when s is 0 and x is 0 s stage should be 0 when x is 1 it goes to the next state when t is 0 it goes to again 0 state when t is 1 it remains 1 so the code is like this we define the register s it works at all this porous clock case s now when s is 0 this state register is 0 when x is 0 s gets 0 if x is 1 s gets 1 so when s is 1 when s is 1 depending on the value of t so if t is 1 s gets 1 and when t is 0 s gets 0 so this is how you write this is an example of writing instruction and what are the rules that we should follow in writing instruction so this is the DSF latch example so this is a latch example this is a T latch so please note there is no clock here or whatever you could call you could call the enable system to be created or anything and 2 knows by such as that if there is no s statement it knows that q has to be preserved and it should come into a latch this is a flip clock with an s6 minus 3 set how do we know it is an s6 minus 3 set we always triggered on posits clock or negative region if reset is 0 q gets 1 so in this case it is actually a set else q gets data now this means that even if the reset comes now let us say clock is 0 and reset is a negative region so reset is 0 q is reset to 1 the respective of the state of the clock is 0 so the thing to note here is that if you want to implement a simple reset the reset should be in a sensitive domain it is obviously one s direction either negative or positive this is again a set in a reset so posits reset or posits set and again we check if reset is 1 then q gets 0 if set is 1 then q gets 1 else q gets data forget about this case it is not that okay let me explain this if endf synthesis means that this part of the code here these lines these lines the tool will the synthesis tool is discarded it will not use it it does not see this because if endf synthesis is written that means if synthesis key word is not defined but when you go to design compiler when you read the design into design compiler by default this key word is defined synthesis is defined and tool will ignore this statement because you have dollar right and so on so this condition is checking the case where reset and set are both 1 which is an invalid case but for design compiler if you do not do anything for that first it will look for now an asynchronous set or reset can only be implemented if your standard cell library has a corresponding sequential cell it will look for a sequential cell which has both set and reset and it will just implement for that so it does not worry about whether set and reset be 1 or 0 it will just look for the correct mapping this is a synchronous reset now synchronous reset how do we know the functionality of the reset it is very similar to the earlier case but now the sensitivity is above that means the reset will take an effect only when there is a rigorous process now this statement is called a pragma we will look more a lot more detail into this in the next section this tells the the tool design compiler that please use reset this is a synchronous reset even if you do not use it the hardware it will be correct this is used in very special cases I will come to it in the next section why is it used but here again now if a library contains a flip-flop a sequential element with synchronous reset then it will use it but if not now this is a case where the functionality of reset can be actually implemented using a combination logic so if your standard cell library does not contain a flip-flop with a synchronous reset it will simply implement a MUX kind of structure on data so if reset is 0 data is 0 if reset is 1 the data is nothing but the data coming from outside so it is a MUX kind of structure on the data input it is very similar to data input so it does not matter if a library contains a flop or not the tool will implement it let us see an example of combination versus sequential in an adder so the code on the left-hand side is a combination always at the rate of star the code on the right-hand side is always at the rate of callus flop please note non-blocking so this is the non-blocking, this is blocking what kind of hardware is generated it is very clear that it is simply an adder a combination adder so a gets b plus c on the right-hand side a gets b plus c but now there is the this boundary here is a sequential boundary so a is the output of a register and b and c feed the data input of this so please be very very clear this slide actually captured the summary of the difference between how to code combination how to code sequence so on on simulation a will get b plus c immediately on the left-hand side on the right-hand side a will get the value of b plus c only at the process of the clock please make yourself very familiar, very profitable this difference so for RTL coding we have to be very very clear which part is combination we separate these two in coding we use this coding style for combination circuit and sequence circuit and the caution here is do not try some fancy coding style most probably it won't be synthesized properly the rule of thumb is declaration of variables for structural description we use wire that means correcting two different modules together or assign statement we use wire for behavior description means when we use always block we use register for combination circuits always all signals used or always at the rate of star use blocking or sequential always at posage or always you could always use a negate also use non-blocking so let me summarize in this lecture we saw what how do we code RTL we saw very basics obviously this is a very vast area we could always study a lot more about this how to write effective synthesizable code we will see few examples in the next lecture on effective coding in the next lecture also I will focus a bit on that but I will be focusing more on how the tools read your design and what kind of reports does it produce so we saw the case of writing common logic we saw some we saw that we could use always block or we could use the time statement for writing combination we saw how we could use always for writing frequency we saw that when in what case the tool implements a latch tries to limit the latch and it is our duty duty of an RTL designer to make sure that the latches are only present now latches are bad from timing point of view otherwise they are fine but nobody likes them when it comes to time impact we will see the few reasons why in the next unit so it is very very important to know right at the start if there are any latch problems in the design how do we know that we review the code we see that the always blocks where we intend to implement the combination logic are properly defined all the pieces are defined or otherwise when you review the design in the design compiler the first time it will tell you I will show you the report it will tell you that it is interpreting a latch it will go back and correct all these things and make sure that latches are only present when where we actually need them and again sequence circuit it is very useful to be very clear about what is combination and what is sequential so that you will see one case in the next session where I will show you that writing a bad coding style can result into a increased number of registrations increased number of sequence assignments and correspondingly it will be there so thank you all please I have noted one assignment here writing your envelope code using the structural there is a block diagram here so this is the assignment I was talking about that now it is a very simple assignment now in this case you should be very clear what is combination for example address combination, mark list combination what is sequential register, address sequential so this prior writing this code the top level should be structure and some modules adder, mark register should be defined separately you should code what is inside adder what is inside mark what is inside register again from next as you become comfortable with RTL coding you could take this code to design compiler and see the report