 Hello and welcome to this presentation of the STM32 LCD TFT display controller. It covers all features of the LTDC controller which is used to interface with TFT displays. The LCD TFT stands for Liquid Crystal Display Thin Film Transistor. The controller is highly configurable and interfaces with standard parallel RGB interfaces. The benefits of the LCD TFT display controller include flexible programmable display parameters, integrated pixel format converter and blender. The LCD TFT display controller or LTDC frame buffer can be located either in on-chip memory or in external memory depending on the panel resolution. The LCD TFT display controller provides a 24-bit parallel digital RGB or red-green-blue interface with additional signals for horizontal and vertical synchronization. The LTDC is master on the AHB bus matrix and can access internal memories like internal flash, SRAM 1, SRAM 2, or external memories via FMC quad-SPI interfaces. It also features a dedicated 64-word FIFO per layer. It supports programmable timings and polarity parameters to interface with a wide range of display panels. The LTDC offers flexible programmable parameters, allowing it to support a wide variety of display panels. Programmable display size, for example, QVGA, WQVGA, and VGA. Programmable background color, 24-bit RGB value, programmed in LCD controller register, LTDC BCCR, used for blending with the bottom layer. Multi-layer support with blending, two layers. Dithering, two bits per color channel, 2-2-2 for RGB. The dithering pseudo-random technique is used to add a small random value or threshold to each pixel color channel or RGB value, thus rounding up the most significant bits in some cases when displaying 24-bit data on an 18-bit display. And new programmed values can be loaded immediately at runtime or during vertical blanking. This is the LCD TFT controller block diagram. The LTDC features three clock domains, AHB clock domain or HCLK, to transfer data from memories to the layer FIFO and frame buffer configuration registers. APB clock domain or PCLK to access the global configuration and interrupt registers. And the pixel clock domain or LCD CLK to generate LCD TFT interface signals, pixel data, and layer configuration. The LCD CLK output should be configured according to the panel requirements. To interface with TFT panels, all timings are programmable through the LTDC controller. These timings come from the TFT panel datasheet and are VBP or vertical back porch, VFP or vertical front porch, HBP or horizontal back porch, or HFP, horizontal front porch, Hsync or horizontal synchronization, and Vsync or vertical synchronization. The LTDC output signals are summarized in this table. The LCD TFT controller pins must be configured by the user application. The unused pins can be used for other purposes. The programmable pixel format is used for the data stored in the frame buffer of a layer. This table describes the pixel data mapping versus the selected input color format. The LTDC can be configured with up to eight programmable input color formats per layer. Direct color, ARGB 8888, RGB8888, RGB565, ARGB 1555, ARGB 4444, indirect color, L8, 8-bit luminance or CLUT, AL44, 4-bit alpha and 4-bit luminance, and AL88, 8-bit alpha and 8-bit luminance. When the color format of a bitmap is converted into another one, this operation is called pixel format conversion or PFC. The pixel data is read from the frame buffer and then transformed to the internal ARGB 8888 format as follows. Components, which have a width of less than 8-bits, get expanded to 8-bits by bit replication. The eight most significant bits are chosen. Note that conversion from direct color to indirect color or from indirect color to direct color is easy to do, but converting a direct color to an indirect color format would mean regenerating a color lookup table or CLUT, which is a very complex operation. The color lookup table is only used in case of indexed color for L8, AL44 and AL88 input pixel formats. It supports up to 256 entries per layer. The frame buffer contains an index value for each pixel. The CLUT has to be loaded with the RG and V values that will replace the original RGB values of that pixel or indexed color. Each color or RGB value has its own address, which is the position within the CLUT. Every layer can be positioned and resized. The programmable layer position and size define the first and last visible pixel of a line and the first last visible line in the window. It allows display of either the full image frame or only a part of the image frame. Every layer has a configurable number of lines and line length for the color frame buffer and the pitch. The pitch is the distance between the start of one line and the beginning of the next line in bytes. These parameters are expressed in bytes, not in pixels, so their values depend on the number of bits per pixel. The line length and the number of lines parameters are used to stop the prefetching of data from the layer FIFO at the end of the frame buffer. The LTDC features configurable blending factors. The blending order is fixed and it is bottom up. If two layers are enabled, layer 1 is first blended with the background color, then layer 2 is blended with the result of the previous blending. Each layer can have a default color in the ARGB format, which is used outside the defined layer window or when a layer is disabled. Tricky use case. Layer 1 is enabled. Layer 2 is disabled with default color black. If blending factor is set to constant alpha equals 0xFF, no image is displayed. Only black window is displayed. Default color of layer 2 is black. To bypass the default color, set the blending factor to transparent, alpha equals 0x00. A color key, RGB, can be configured to be representative for a transparent pixel. If color keying is enabled, the current pixels after format conversion and before blending are compared to the color key. If they match for the programmed RGB value, all channels ARGB of that pixel are set to 0. The color key value can be configured and used at runtime to replace the pixel RGB value. Color keying is enabled through the LTDC LXCKCR register. Line interrupt. Generated when a programmed line position is reached. Register reload interrupt. Generated when the shadow registers are relocated during the vertical blanking period. FIFO underrun interrupt. Generated when a pixel is requested from an empty layer FIFO. And transfer error interrupt. Generated when an AHB bus error occurs during data transfer. The LTDC is active in run and sleep modes. An LTDC interrupt can cause the device to exit sleep mode. The device is not able to perform any communication in stop and standby modes. Graphic applications require a high quality user interface. This can be achieved using the STM32MP1 to connect the display thanks to the LCD TFT controller. In addition, the FMC or Quad SPI interface may be used to access an external flash memory containing all of the graphical contents needed such as background images, high resolution icons, or fonts to support multiple languages. This is a list of peripherals related to the LTDC. Please refer to these peripheral trainings for more information if needed. Reset and clock control or RCC. And general purpose inputs, outputs, or GPIO.