 Last class we saw about the various techniques that are available for process evaluation. We saw that we have techniques for electrical measurement, techniques for physical measurement. These are usually the thickness of films, but also lateral dimensions especially in the case of lithography and also techniques for measuring the number of defects and also the type and the distribution of defects. So process evaluation is important because we saw that a typical IC manufacturing can take place in approximately a month's time and has 500 or more processes. So we need to know whether the wafers which pass through each of these processes are good enough in order to go on to the next step. So today we are going to talk about process yield and also productivity of the IC manufacturing process. So when we talked about process evaluation in last class, we saw that for each of the individual processes we define some sort of a process window. So the process window basically defines the parameters that are acceptable to that particular process. For example, if you are looking at oxide growth, then the process window would essentially have the thickness of the oxide that is the range of thicknesses that are permitted and also the amount of defects. So the process window defines the acceptable range of the parameters. So semiconductor IC manufacturing is essentially a complex process. It is a series of processes which are sequentially arranged one after the other as a sort of assembly line. So we start with a blank wafer and ultimately at the end of the process we get our finished die or the finished chip. So for this manufacturing, we usually define something called a process yield and there are three main measurements of process yield. So the first one is called the wafer fabrication yield or fab yield. This is usually abbreviated as fab yield. So this is the ratio of the number of wafers that come out of the fab after processing to the number of blank wafers that start at the beginning of the fab process. So this is the number of wafers out divided by the number of wafers that are started. We can also define something called a sort yield or a wafer sort yield which is the number of good dies in a given wafer. When I say good die, it is essentially a functioning die. So it passes the electrical testing. So the number of good dies, the number of functioning dies divided by the total number of dies in the wafer and then finally we have something called a packaging yield which is the number of packaged dies that pass the electrical test. So I will just abbreviated as E test but E test is nothing but electrical testing divided by the total number of good dies. So the overall yield in a fab is the product of all three of this, the fabrication yield, the sort yield and the packaging yield and this is closely related to the cost of the manufacturing. So typically you want as high a yield as possible because this again will lower the cost per individual die. So today we are going to look into three of this in detail and some of the parameters that affect the various yield values. So we will first start with looking at the wafer fabrication yield. So I am going to abbreviate this as the fab yield and this gives the output of the overall fabrication process. If you look at a fab, we saw that a fab is essentially like an assembly line. So the blank wafer start and then go through each and every process and subsequently after all the processing is done they come out of the fab. So we can call each and every step of the IC manufacturing process as a station and for each station or each step of the process we can define a station yield. So the station yield again is nothing but the number of wafers leaving the station divided by the number of wafers that are entering the station and when I talk about station each and every step in the manufacturing process is called a station. So station just refers to the individual step in the manufacturing process. So if we can define an yield for each and every step in the process and the fab yield is the overall yield or the overall output of the fabrication process then the fab yield is nothing but the cumulative yield of all the individual stations. So the fab yield can be written as station yield 1 times station yield 2 and then this just goes on right. So the overall yield is the cumulative yield of the individual stations which is why when we look at IC manufacturing we want as high a station yield as possible close to 100% because of the fact that the overall fab yield is a cumulative of all the individual station yields. So we can consider this by taking a simple example. So I have different steps. I am going to start with 1000 wafers for each step we can define a station yield which will tell you how many wafers come out and finally you have a cumulative yield. So right now I will only consider a 5 step process just to see how the cumulative yield depends upon the individual station yields but remember a typical IC fabrication can have more than 500 processes so that what we have in 5 steps has to be multiplied by 100. So my first step I will call it to be the field ox. So formation of an oxide layer so initially I will start with say 1000 wafers. The station yield is 99.5% which is nothing but the number of wafers leaving the station by the number of wafers entering so that the number of wafers that come out is 995. The next step is forming the source and the drain mask. So we start with 995 wafers because remember this is an assembly line process. So after the first step the wafers that come out of the first step go to the next step those that come out go to the next step and so on. So we start with 995 wafers your station yield is 97% so the wafers out is 965. So already with just 2 steps we started with 1000 wafers and we have essentially lost 35 wafers even though your individual station yields are much higher than 95%. The third step is your source and the drain doping so you form the individual source and the drain regions. So we start with 965, 99.3 is your station yield, your output is 958. The fourth step is gate ox so 958, 99% is your station yield and you have 938. Then I will write one more step and then stop there so this should be 948 and then contact whole so we start with 948 again I will say 99% overall yield is 938. So we have just 5 steps in a fabrication process we started off with 1000 wafers and at the end of 5 steps we have essentially 938 wafers or you have lost approximately 62 wafers. We can define a cumulative yield which is the product of the yield of each an individual step. So the cumulative yield the first step is 99.5 then it is the product of these 2 which is 96.5 then the product of this with 99.3. So let me just write the numbers 95.8, 94.8 and then 93.8. So the overall cumulative yield after 5 steps is 93.8 the fab yield is nothing but the number of wafers that come out by the number of wafers that go in. So if you look at the fab yield there is again just 938 which is the wafers that come out by the number of wafers that went in which is again 93.8%. So what we see here are a couple of important points. The first is your individual station yields are still pretty high. So this is 99.5, 99.3, 99, 99 the lowest one is for the formation of the mask and that is still pretty high 97. So even though the individual station yields are high the overall yield because it is a cumulative process is lower. Also if we increase the number of steps the overall yield reduces because once again it is a cumulative process. So with just 5 steps you only get a yield of 93.8. So if you have 500 steps then the overall yield will be even lower which is why in the case of IC manufacturing which involves so many processes it is very essential that each of the individual processes have a high yield close to 100% so that the overall process has a high yield. We will next look at some of the processes or some of the issues that affect the station yield. So factors affecting the fab yield. So the fab yield is related to the yield of the individual stations so that some of these factors which also affect the individual station yield. The first factor is the number of process steps. As we saw earlier more the number of process steps lower is the overall yield. So as the number of steps increases the yield will reduce. For example let us say you have a 50 step process and each step so which is your station yield has a value of 99.5. So each step has a yield of 99.5% which means if 100 wafers come in or 1000 wafers come in 995 wafers will come out. So only 5 wafers are lost per individual step. But if you have 50 such steps the overall fab yield is the product of the individual station yields so 0.995 times 50 which is just 0.75 or 75% fab yield. If instead of 50 we had 100 processes the yield will be even lower. So more the number of process steps lower will be the yield. Unfortunately with reduction in the size of the individual circuits because of your device miniaturization the number of process steps actually increases as we go from one generation to the next. So having a high individual station yield is important to get a overall good fab yield. Another factor that affects fab yield relates to wafer breakage and also warping. So this is related to the wafer handling inside the fab. So these days 12 inch wafers are used in a typical IC manufacturing process. The next iteration will go from 12 inch to 18 inch or you are going from 300 millimeters to 450 millimeters. So the handling of these wafers which are pretty huge is essentially entirely an automated process. Later we will look at how the wafers move in a fab and we will also look briefly at the automation process in the fab but the overall handling is automated in order to prevent wafer breakage because if you have wafer breakage once again you will lose these wafers. The number of wafers that come out will be lowered and this again will affect the fab yield. Wafer warping is related to the change in dimension of the wafers as it goes through different heat treatment processes. Especially processes like rapid thermal annealing will take the wafer to high temperature in a short duration of time and also cool it faster. So this can induce thermal stresses in the wafer and also cause a change in the dimension of the wafers. This is called the wafer warping. So once again this can affect the yield of the fab. So wafer warpage is very important especially when dealing with heat treatment processes. The third factor is the process variation. So in last class when we looked at process evaluation we defined a process window for each process which tells you the acceptable parameters that are possible for a particular process. So if a process has a value that is beyond the range of these acceptable values then once again the process is said to have failed and the wafers are said to have failed at that particular process step which will again affect the yield. So it is very important to set the proper limits for any process or the proper parameters for any process. This is called a spec limit. Spec is nothing but short for specification. So the spec limit is set for each process which tells you the acceptable range. For example if you are growing an oxide layer or a nitride layer or any other layer, thickness range would be an acceptable spec limit. Similarly the maximum amount of defects that are permissible would be another spec limit. So the spec limits are too loose so they are too wide. Once again they can cause a process to fail because there will be a lot of variation. On the other hand if the spec limit is too tight then a lot of experiments would not be able to meet the spec limit and once again the wafers will fail. So setting the appropriate spec limit or the specification limit is important when we are looking at trying to get a higher yield. The next one relates to the process defects. These are essentially isolated defects that are caused during the process. So this could be related to the process steps or it could be related to any contamination that arises from the process chamber and so on. So these are isolated defects either related to the process or to the equipment. Again to give an example we can go back to the idea of oxide growth on a wafer. If there are some issues with the furnace so there is some sort of contamination then this contamination can again affect the wafers. So if you produce a spec limit for the defect concentration any contamination in the chamber can affect the defect limits and once again lead to the wafers being rejected. So having a good maintenance or a good preventive maintenance of the equipment is essential in order to reduce the number of process defects. You can also have defects that are related to the mask. This is especially related to lithography so these are your mass defects. So these are essentially defects in the hard mask. The hard mask contains the pattern that is then transferred to each and every wafer. So typical defect could be something like a dust. Usually this is made of glass so they could be cracks in the glass. You could have an damaged mask layer due to handling. All of this will again cause defects in the pattern which will again lead to a lowering of the yield. So typically a mask is cleaned just before using it for transferring the pattern onto the wafer. So cleaning the mask is important because it removes some of the dust and regular mask inspection is also carried out in order to make sure there are no damages to the mask or no damages or cracks in the mask which will again affect the wafer. So these are some of the various factors that affect the fab yield. All of these have to be minimized in order to get a high fab yield. The next thing we are going to look at is the wafer sort yield and some of the factors that affect sort. So we look at the wafer sort yield next. We define wafer sort as the total number of good dice in a wafer divided by the total number of dice in the wafer. So as I mentioned earlier when I talk about good dice these are dice that have electrical functionality in them so that they pass some sort of E test or electrical test. So the factors that affect the sort yield the first one is the diameter of the wafer and linked to that is also the size of the die or the area of the die. So these two are sort of linked. So if you think about it as we increase the number or if you increase the size of the wafer so we increase the diameter of the wafer the number of dice in it will also increase. So if you have more number of dice then your overall wafer sort yield will be high because you will have a higher percentage of good dice and you will also have less number of edge dice. Those is dice that are partially complete and they are located at the edges. So increasing wafer diameter will basically reduce the number of edge dice and again increase the overall sort yield. So the opposite thing happens if we increase the die size so we increase the size of the individual die which means the number of edge dice will increase which will lead to a lowering of the yield. So these two sort of work one against the other so that overall idea is to have larger wafer which are more cost effective. Which is why initially in the IC industry we started with 1 inch wafer which finally grew and now we have 12 inch wafer that are being used and the next generation will essentially have 18 inch wafer. So the driving force behind using larger and larger wafer is to reduce the number of edge dice and to increase the overall sort yield. Again the next parameter is the number of processing steps. So we have seen this earlier in the context of the fab yield. So same thing more the number of processing steps you will have a higher background density or a higher defect density which will again reduce the yield. Then we have other parameters like the circuit density, the defect density, crystal defects so any defects that are present within the silicon crystal which can again affect the processes. So these are defects that are present even before the wafer enters the fab. So this is during the manufacturing of the silicon wafer and also the cycle time or the process time. So all of these are various factors that affect the sort yield. So again if you have a larger cycle time you can have more contamination which will again affect the wafer. Circuit density if you have a higher circuit density the individual components are closely packed which means even smaller defects can essentially damage the chip. Again other things the defect density and crystal defects are sort of obviously related to the sort yield. So there are different models which basically look at how all of these defects affect the fab yield. So let us look at some of the yield models that are currently being used. So we will look at some of the yield models. A yield model basically relates the process so the number of processing steps, the defect density and the chip size to the yield of the process. So it relates the various parameters that essentially come from each step to the overall yield of the process. The simplest yield model is a Poisson model. So this assumes we have a random distribution of defects in the wafer. The defects we are talking here are essentially the killer defects. So defects that can essentially damage the chip and make the chip non-function. You can also have defects that are non-critical. Their density will be typically higher than the killer defects but we will not focus on them because they do not affect the yield of the wafers. So we have a random distribution of defects. So let us say you have a wafer with n chips and n defects, small n defects. Given that these are randomly distributed, the probability of a chip having k defects let us call this P of k is nothing but the Poisson distribution given by e to the minus m, m over k by k factorial where m is nothing but n over n. So the probability of a chip with no defect, so P of 0 which is no defects which is nothing but the yield because we define yield as the number of chips which are good and functioning to the total number of dyes or total number of chips is nothing but e to the minus m. This is the yield of the process. So instead of defining the total number of defects, we can define a chip defect density d naught which is nothing but the number of defects divided by the total number of chips times a where a is the area per chip. So if we define a chip defect density d naught then P of 0 by the Poisson model which is nothing but your yield is e to the minus a over d naught. So the yield again defends upon the area per chip. So if you have a larger chip area which means we have a larger die area, the yield is lower for the same density of defects on the surface which is once again the reason why we go for larger wafers so that the overall number of chips are higher. So the Poisson model assumes a random distribution of defects but that is something that is not always true. So the Poisson model assumes a random defect distribution but in most cases defects are clustered which means there are different models to account for this clustering. Another term used is called decoration. So we say that the defects decorate the surface of the wafer. So in that case you define the yield as an integral f of d e to the minus a d and f of d refers to how the defects are distributed in the wafer. So it is the distribution of defect density. So there are different models that take into account different values of f of d. These give predictions that are much more closer to reality. For example you have a Murphy's model which assumes a triangular distribution so that the yield has an exponential function. You also have an exponential yield model where once again you have different distributions. So according to this model you have some areas in the wafer which have a high density of defects and some areas that are not. So you have high defect densities that are essentially restricted to small areas on the sample. In that case your yield is essentially given by square root of a d naught. This model is called a Siege's model. There are some other models for example there is again a Bose-Einstein model which once again assumes some other distribution of defects which gives a different value of yield. So all of these assume a non-random distribution but the overall common theme behind all of those is that as the dye area increases that is a increases the yield essentially drops. So we have seen three processes or three types of yield. One is the fab yield then we have the sort yield and finally we have the packaging yield. All three of them come together to determine the overall yield in the fab. So the overall yield is nothing but the fab yield times the sort yield times the packaging yield. So we have looked at some of the parameters that affect yield. Yield is one of the factors that goes into the overall cost of producing a wafer. This tells you why a wafer fabrication is such a capital intensive industry. So we look at some of the costs associated with wafer manufacturing. So if you look at wafer fabrication costs there are mainly two main kinds of cost factors. The first is called a fixed cost. So this is related to the presence of overhead so administration, facilities, any development and also equipment. Fixed costs are there whether the wafers are manufactured or not. So they are there regardless of manufacturing. So they are not linked to the volume of manufacturing. Examples of fixed cost are overhead, any equipment that is purchased. So whether the equipment is used or not the purchasing cost will still be there, administration and then facilities, so building facilities and other things all of these come into the fixed cost. The variable cost is related to the amount of material that is produced. So it is related to the volume of manufacturing. So more the number of wafers that are produced greater is the variable cost. So some examples of this are materials, labor because more the manufacturing is done, more the number of labor is required which leads to a greater cost. But more importantly yield which we saw earlier is related to the variable cost because the lower the yield which means you still have less number of wafers that come out and that will lead to a higher variable cost. Because of these different expenses semiconductor manufacturing companies are essentially divided into two main models. The first model is called an integrated device manufacturer or an IDM. So these are vertically integrated companies that own all the steps starting from the wafer fabrication to wafer sort to packaging to circuit design and so on, vertically integrated. So these companies have essentially a high overall cost because they own all the equipment and also all the facilities for doing the research and also the manufacturing. So an example of an IDM, the most famous example is of course Intel but you also have companies like IBM and Samsung. So for these companies a high volume of production with a high yield is essential in order to offset the high cost. The second kind of company is a fabulous semiconductor company. So these are companies that make the circuit design but then the chip manufacturing is done by another company. So they outsource the chip manufacturing to a foundry. So they do the design but manufacturing is done by a foundry. Examples of fabulous companies include AMD and Qualcomm. So the advantage of these companies is that the cost is lower but then the disadvantages their process is basically defined by the foundry or the technology of the foundry to which essentially outsource the job. So if the foundry is based on a 32 nanometer technology, the final product will also be based on a 32 nanometer technology. So the technology is limited by the capabilities of the foundry company. So the yield that we saw before essentially enters into the overall cost of the final wafer. So we want a high yield in order to ensure a lower cost for the individual wafers. So today we have looked at an example of process yield and also how the yield affects the productivity. In the next class we will look at the clean room designs and also how to minimize contamination inside a clean room or why we need a clean room in order to do semiconductor manufacturing.