 Hello, and welcome to the STM32G0 training session. The architecture of the STM32G0 is described in this figure. The STM32G0 is a low-power microcontroller whose CPU is an ARM Cortex M0+. Only the GPIO ports are directly accessible from the CPU by using the single-cycle IO bus. Two masters are connected to the main AHB interconnect called bus matrix in the figure, the CPU and also the DMA controller. The AHB slaves are memories SRAM and flash memory, CRC, AES, RCC, RNG, EXTI peripherals, flash controller registers, DMA and DMA MUX registers, the AHB to APB bridge, the APB peripherals are listed in the blue box on the right of the figure. Most peripherals can request a DMA transfer to the DMA MUX and then the DMA controller in order to transfer data to or from SRAM or flash memory. For instance, characters received by USART1 can be transferred to a buffer in SRAM without software intervention by relying on a DMA channel. This slide explains the various fields of the STM32G0 ordering information. Device family is STM32, product type is G. Device sub-family can be 070 for value line 071 for access line and 081 for security line. Four pin counts are supported from 25 to 64 pins with respectively 23 to 60 GPIOs. The flash memory size can be 64 or 128 kilobytes. The following packages are proposed UFPGA, LQFP, UFQFPN and WLCSP. Two temperature ranges are supported, minus 40 to 85°C and minus 40 to 125°C. The last field indicates the options, typically blank or N, depending on whether USB-powered delivery interface number two pins are available in 28 and 32 pin packages. Therefore the STM32G081RBT6 is an STM32G0 security line 64 pin, 128 kilobyte flash memory, LQFP, MCU supporting minus 40 to 85°C temperature range. Most of the pins are GPIOs supporting multiple functions. Dedicated pins are power supply and ground. Power supply pins are VDD, VBAT and VREF+. Note that VBAT and VREF+, pins are not present in 32, 28 and 25 pin packages. The reset signal is multiplexed with GPIO port F number two and boot zero is multiplexed with GPIO port A number 14. So these IO pads have a dedicated function during reset time and become later general purpose IOs. The devices housed in 64 and 48 pin packages provide two USB-C power delivery ports. The devices housed in 28 or 32 pin packages come in two variants, GP with a single port limited USB-C powered livery and PD with two port USB-C powered livery. This slide highlights the differences between the packages supporting and not supporting two port USB-C powered livery. On the left, the STM32G071KXT supports a unique powered livery interface, PD1. On the right, the STM32G071KXTXN supports two power delivery interfaces, PD1 and PD2. The STM32G0 has three power supply pins, VDD or VDDA. VBAT and VREF+, VDD or VDDA is the power supply of the IO pads and integrated flash memory and also supplies voltage regulators which provide the V-Core supply. V-Core voltage is 1.2V for a system clock frequency of 64 MHz. The VBAT power domain consuming very little energy includes RTC and LSE oscillator, temper detection and backup registers. The VREF+, is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled. On packages where VREF+, and VBAT are not available, these power supplies are internally connected to the VDD pin. The STM32G0 offers a new security feature called Securable Memory Area. The main purpose of the Securable Memory Area is to protect a specific part of flash memory against undesired access. This allows implementing software security services such as Secure Key Storage or Safe Boot. The general purpose input outputs or GPIOs can sync or source up to plus or minus 8 mA and sync or source up to plus or minus 20 mA. The STM32G0 supports flex power control which enables efficient running 7 low power modes and several sub modes. In run mode, the consumption is 100 mA per MHz. Stop 0 and Stop 1 are low power modes in which the state of the cortex M0+, is maintained. Stop 1 is equivalent to Stop 0 with main regulator off, resulting in a smaller current consumption but longer wake-up time. In standby mode, by default, there is neither SRAM nor register as retention because voltage regulators are in power down state. However, there is an option to retain the contents of the entire SRAM. Shutdown mode is similar to standby but without power monitoring and the unique clock source is the low-speed external oscillator. The STM32G0 integrates the following subsystems. System modules PWR, RCC, RTC and Tampers, SysTick, GPIO, CRC and SysCFG. Processor modules Cortex M0+, Core, MPU, NVIC and Software Debug. DMA controller supporting 7 channels. Interconnect based on an AHB light matrix and an AHB to APB bridge. Embedded memories 128 kilobyte flash memory plus 36 kilobyte SRAM. Control modules 132-bit timer, 116-bit timer that can be used to control a motor, 516-bit timers with PWM capability, 2 low-power timers. Analog modules temperature sensor, 12-bit ADC, 12-bit DAC and 2 comparators. USB power delivery modules, 2 modules including BMC and PHY. Connectivity modules, 2 SPI modules also supporting I2S, 4 USARTS, 1 LPU ART, 2 I2C controllers and HDMI CEC. Encryption modules AES and TrueRNG. This session is organized to provide you with the most important information to ensure that you can develop your application as easily as possible. You will find a technical description of all the STM32G0 modules including peripherals and development tools organized into specific sections, system, ARM, Cortex, M0+, CPU, interconnect and DMA controller, memories, control, analog, USB power delivery, connectivity, encryption and development ecosystem. You can browse each section separately and learn about each module in the order of your choice and at your convenience. This session also allows you to search directly for a keyword and you will have a direct access to sections covering this information. Now let's get started with the training. Do not hesitate to follow the events and news about this product on our website at www.st.com.stm32g0. Enjoy!