 Hello, and welcome to this presentation of the STM32WL5 Extended Interrupts and Events Controller, or EXTI. The Extended Interrupt and Event Controller, or EXTI, provides 47 independent events, split into two categories, configurable events, and direct events. Applications benefit through smarter use of low power modes, taking advantage of the STM32WL5's capability to wake up each CPU independently via external communication or requests. This is the block diagram of the Extended Interrupt and Event Controller. Configurable events are generated by peripherals without interrupt capability, but which are able to issue a pulse. The EXTI Controller provides interrupt detection, masking, and software trigger. Direct events are generated by peripherals supporting interrupt requests. In this case, the EXTI Controller is used to generate events to the CPU and to request system wakeups. The Extended Interrupt and Event Controller provides a single interrupt per configurable event to both CPUs. The individual CPU wakeups are provided to allow independent wakeup of both processors. The Extended Interrupt and Event Controller can generate interrupts and events as well as wake up the processors from stop modes. Configurable events are linked with external interrupts from GPIOs, PVD, PVM, Comparators Comp, CPU Sant event, and sub-gigahertz radio busy. Direct events are linked with RTC, TAMP, I2C, USARTS, LPUART, LP-TIM, sub-gigahertz radio, IPCC, HSEM, FLASH, and DEBUG. With WFE, the first instruction executed after a wakeup event is the next sequential one, INSTR N plus 1 in the sequence on the left. By implementing WFI, the processor jumps to the interrupt service routine when an enabled interrupt request is received. Note that an interrupt request is a WFI exit condition, but an event received on RxEV is not a WFI exit condition. For the STM32 WL5 series, the event generation is only available from the listed peripherals. This figure aims to explain the various stages enabling the conversion of a configurable event active edge into an interrupt request. The first stage is the asynchronous edge detection circuit configured by two registers, EXTI-RTSR1 and EXTI-FTSR1. Any edge, possibly both, can be chosen. The software can emulate a configurable event by setting the corresponding bit in the EXTI SWIER register. The bit is auto-cleared by hardware. An AND gate is used to mask or enable the generation of the interrupt to the CPU and VIC. Finally, a flag is set in the EXTI-PR1 register when the interrupt is generated to the CPU and VIC. This flag enables the software to determine the cause of the interrupt. This flag is expected to be cleared by the interrupt service routine. This figure aims to explain the various stages enabling the conversion of a configurable event active edge into a processor event. Both configurable and direct events can be configured to issue events to the CPU, steered to its RxEV input. Unlike interrupt requests, the CPU has a unique event input, so all event requests are OR'd together before entering the event pulse generator. The registers used to mask the generation of events are different from the ones used to mask the generation of interrupts. EXTI-EMR instead of EXTI-IMR. The dual-core STM32WL5 microcontroller has an independent event generation logic for each CPU. The CPU's wake-up signals generated by the EXTI block are connected to the PWR block and are used to wake up the system and CPU subsystem's bus clocks. Both configurable and direct events are able to request a wake-up. A wake-up occurs when an asynchronous edge detection circuit has detected an active edge. Consequently, software is expected to clear the flag in the EXTI-PR1 register to disable the wake-up request when the source of the wake-up is a configurable event. For direct events, the flag is located in the peripheral unit. These flags enable the software to find the cause of the wake-up. The wake-up indication is asserted when either the wake-up or the event generation is enabled. See the OR gate combining EXTI-IMR and EXTI-EMR registers. All CPU wake-up signals are OR'd together and then OR'd with the event requests. CIS wake-up is asynchronous and wakes up the clocks. Once HCLK is running, the synchronous C1 wake-up and or C2 wake-up is generated to wake up the respective CPU. A direct event is able through the EXTI controller to generate a CPU event and trigger a system wake-up. The active edge of direct events is the rising edge. Direct events do not rely on the EXTI controller to assert interrupt requests because they have their dedicated lines to the NVIC. Otherwise, the same circuit as the one described in the previous slides are implemented. Direct events can be independently masked for event generation and interrupt generation. The interrupt mask in the EXTI controller is only used as a wake-up mask. The extended interrupt and event controller is linked with the nested vector interrupt controller of the Cortex-M4 CPU and Cortex-M0 Plus CPU. Please refer to the related presentations. For detailed information, please refer to the programming manual for the STM32 F3, F4, L4 and L4 Plus series and the reference manual of the STM32 WL5 series.