 Hello, and welcome to this presentation of the STM32 system window watchdog. It will cover the main features of this peripheral used to detect software faults. The window watchdog is used to detect the occurrence of software faults. The window watchdog can be programmed to detect abnormally late or early application behaviour. It's best suited for applications required to react within an accurate timing window. Once enabled, it can only be disabled by a device reset. An early wake-up interrupt can be generated before a reset happens to perform a system recovery or manage certain actions before a system restart. The window watchdog offers several features. The user can program the timeout value and the window width according to application needs. It can generate a reset under two conditions. When the down-counter value becomes less or equal to 0x3f, or when the watchdog is refreshed outside the time window. It can generate an early wake-up interrupt when the down-counter reaches 0x40. The early wake-up interrupt can be used to reload the down-counter in order to avoid a reset generation or to manage system recovery and context backup operations. As shown in the figure, the window watchdog uses the APB clock called P-Clock as reference clock for its timebase. The P-Clock is provided by the RCC block. This clock is divided by 4096 and by a value programmed by the application. The application can also program the reload value of the down-counter bit's T. The window width is controlled by bit's W. This diagram illustrates how the window watchdog operates. When the 7-bit down-counter rolls over from 0x40 to 0x3f, it initiates a reset. This happens if the application software does not refresh the window watchdog on time. The early interrupt, if enabled, can be generated when the down-counter reaches 0x40. If the software refreshes the watchdog while the down-counter is greater than the value stored in bit's W, a reset is generated. This happens when the application refreshes the watchdog too early. No interrupt is generated in this case. To prevent a window watchdog reset, the watchdog refresh must happen while the down-counter value is lower than the time window value and greater than 0x3f. This is illustrated by the green area. The refresh operation consists on reloading the down-counter with bit's T. Writing 0 to T can be used to enforce an immediate reset. To enable the window watchdog clock, the corresponding window watchdog enable bit in the RCC block must be set to 1. Note that once the APB clock for the watchdog is enabled, the application cannot disable it. Only a system reset can disable the watchdog clock. A low-power enable bit can be set as well if the application wishes to keep the window watchdog activated. Even if the CPU is in sleep or stop mode, the down-counter uses the APB clock p-clock divided by 4096 and again divided by a division ratio selected by the application. It can be 1, 2, 4, 8, 16, 32, 64 or 128 as defined in the WWDG CFR register. The formula shown in this slide lets you determine the watchdog time-out value. When a system reset occurs, it's possible to identify the cause of the reset thanks to status flags provided by the RCC block. The window watchdogs can be one of the sources. The early wake-up interrupt can be used in order to perform emergency tasks before the reset occurs such as data logging, data protection, watchdog refresh in order to prevent the reset or other emergency tasks. The EWI interrupt occurs whenever the down-counter value reaches 0x40. It's enabled by setting the EWI bit in the WWDG CFR register. The EWI interrupt is cleared by writing 0 to the EWIF bit in the WWDG SR register. The window watchdog is active in run modes. In sleep and stop modes, it can be frozen by clearing the corresponding bit in the RCC block. In stand-by and shutdown modes, the window watchdog is not available. The format of the WWDG CFR is not identical in the STM32F0 and STM32G0 window watchdogs. The STM32G0 microcontroller supports an additional bit to extend the pre-scaler ratio value to 128.