 This time we're going to begin building some memory structures. We're going to be interested in producing some hardware that can hold data for us so that once we put some data in, this set of hardware will retain its state until we tell it to have a different value. The simplest way to do this is by using an SR latch. There's a couple different ways we can build these, but in both cases they involve two cross-coupled gates so that both of these gates feed their results into the other one. The NOR version of the SR latch is perhaps the easier one, so we will begin with that one. As it is based on NOR gates, I will have two of those, and these are cross-coupled, which means that I will take the output of one gate and pass it in as the input to the other one. Now I will have two inputs. I can have a set and a reset. The value that's being held in here will be shown on this line as Q, but this line will have the negation of Q on it. So we could potentially read either one if we are interested, but generally we'll be interested in this bit because that tells us what is actually in here, what did we put in there. So our SR latch starts out in an unreliable state. When we just first initialize this, it's not going to have any meaningful value in it. We have to actually set the state of the SR latch before we can do anything with it. And in this case we set the state by either asserting the S line or the R line. We don't want to assert both at once. Assume that I put in one for S and a zero for R. So one or anything will give me one, but not one is zero. So this zero will come back around here. Now I'll have zero or zero is zero, not zero is one. So then the one would feed back around here and I'd have one or one is one, but not one is zero. So now it's reached a nice stable state. You can see I put one in here. I get a one out here, but I get a zero for the negation of one. If I now go through and set my set line to zero, now I've got two zeroes coming in. So zero or one is one, but not one is zero. So it won't change its state when I have two zeroes. And if I change my reset line to one, then I've got zero or one gives me one, but not one is zero. Down here I've got zero or one, which gives me one, but not one is zero. So the zero feeds back around here. Then I have zero or zero is zero, not zero is one, and the one feeds back around here. So now I'd have one or one is one, but not one is zero. So now it's reached another stable state where the latch has been reset so that we've got zero for our output or one for the negation of our output. We can also do this by using NAND gates. And that actually gives us something a little different. So we'll start by having two NAND gates, and the construction will be pretty similar. They'll again be cross-coupled, but this time I will have the negation of s as one of my inputs and the negation of reset as the other input. And this will also move around where we've got our results. So Q will now be on the top and negation of Q will be on the bottom. This time I'm only allowed to set one of these two gates to be zero. If we want to change the state of our SR latch, then we actually need to de-assert one of these two lines rather than asserting it the way we did with the NOR gates. So I will start by putting in one for s, which means the negation of s will be zero, and zero for r, so the negation of r will be one. Now I get zero and anything will be zero, so not zero is one. Then I've got one and one would be one, so not one is zero. Zero feeds back around and I have zero and zero is zero, so not zero is one. So that would be a stable state. If I turn off my set line so that negation of s becomes one, now I've got one and zero is zero, so not zero is still one. Then one and one is one, so not one is zero. So this will still be a stable state because I haven't tried to assert either my set or my reset. Now if I assert the reset, then the negation of reset becomes zero. So I've got zero and one gives me zero, not zero is one. Now I've got one and one gives me one, so not one is zero. Then I again have zero and zero is zero and not zero is one. So both of these have about the same ideas. We're interested in either setting the output to one or resetting it, in which case it turns into zero. But they work a little differently. With the NAND gates, if we want to assert either the set or the reset, we actually have to de-assert that line. Whereas with the NOR gates, we can assert those two lines, but we've flipped around where the output comes. Either of these will be useful for building more complex memory structures, but these two simple gates are enough to hold a piece of data for us.